ECE 445 Computer Organization and Design Fall 2010 MPLab: MIPS Register File

Electrical and Computer Engineering George Mason University September 24, 2010

Objective

The objective of this lab is to design a MIPS Register-File using structural VHDL code as illustrated in Figures 1 and 6. The register le consists of thirty two 32-bit registers. Each register is uniquely addressable using a 5-bit register number. Two registers can be read simultaneously and only one can be written at a time.
read_reg1 read_reg2 write_reg write_data clock RegWrite 5 5 5 32

32

Register File

read_data1 read_data2

32

Figure 1: Register le

Required Reading
Before beginning work on the lab, read sections 3 and 8 of appendix C, which is included on the CD that accompanied the text book. Review the MIPS reference card(green card) that was included with the text book.

Required Knowledge
How to write VHDL code using the behavioral and structural models. How to use packages in VHDL. How to use the Xilinx ISE 12.1 toolkit to write VHDL code and test benches.

Design

Design the register le using D ip-ops, multiplexers and decoders as illustrated in Figure 6. The type of VHDL model to be used for design of each module and the delay introduced by them are specied in Table 1. The modules are shown in Figures 2, 3, 4 and 5. Note:Use the HDL-based model for the design of all the components (refer to Section 3 of Xilinx tutorial).

D clock

D flipflop

Q Qnot

D we

0 1

D flipflop

Q Qnot

clock

Figure 2: D ip-op

Figure 3: D ip-op with write enable

32 32

enable dec_in 5

32

Decoder

dec_out

din we clock

Register

dout

Figure 4: 5-to-32 Decoder

Figure 5: 32-bit register

No 1 2 3 4 5 6 7

Table 1: Modules to Module D ip-op (Figure 2) 2x1 multiplexer D ip-op with write enable (Figure 3) Register Using D ip-op with write enable (Figure 5) 32x1 multiplexer 5 to 32 decoder (Figure 4) Register File (Figures 1 and 6)

Design Model Delay(ps) Behavioral 20 Behavioral 20 Structural 40 Structural Behavioral Behavioral Structural 60 20 20 100

32

Decoder
enable 32 dec_out dec_in

dec_out(0) clock 32 dec_out(1) clock

din we

dout

32

R0
din we dout 32

read_reg1(4:0) read_reg2(4:0) write_reg(4:0) write_data(n:0) clock RegWrite

5 5

R1
32

read_data1(31:0) read_data2(31:0)
32

32

32 dec_out(31) clock

din we

dout

32

R31

Figure 6: Register-File with thirty two 32-bit registers

No 1 2 3 4 5 6 7 8

Table 2: Test Vectors read reg1 read reg2 write reg write datahex RegWrite 00000 00001 11011 456789AB 0 11011 00001 00001 7CE39BFC 0 00000 00001 11011 456789AB 1 11011 00001 00001 7CE39BFC 1 00001 00011 00010 83887483 1 00000 00001 00011 83887484 1 00011 00010 00100 83887485 1 00100 00101 00101 83887486 1
n

Decoder
enable 32 dec_out dec_in

dec_out(0) clock n dec_out(1) clock

din we

dout

R0
din we dout n

read_reg1(4:0) read_reg2(4:0) write_reg(4:0) write_data(n:0) clock RegWrite

5 5

R1
n

read_data1(n:0) read_data2(n:0)
n

n dec_out(31) clock

din we

dout

R31

Figure 7: Register le with thirty two n-bit registers

Testing

Write a test-bench to test your design for the given inputs in Table 2. The test values should be applied in the same order as they are listed.

Extra Credit

Extend your VHDL model of the register le for to n-bits as illustrated in Figure 7, where n can be 8, 16, 32, 64,...

Deliverables

Once completed, submit a ZIPPED le with the following syntax regle FIRST LAST.zip where FIRST LAST is your rst and last name. For instance, le should be named like this regle JohnDoe EmilyWatts.zip. The zipped le should include the following les : 1. pack.vhd (package containing instantiations of all components used in the design). 2. d.vhd( D ip-op). 3. mux2.vhd( one-bit 2x1 multiplexer). 4. dwe.vhd( D ip-op with write enable). 5. reg.vhd( thirty two -bit register). 6. mux32.vhd(thirty two -bit 32x1 multiplexer). 7. dec.vhd (one-bit 5 to 32 decoder). 8. regle.vhd( register le). 9. Your test-bench to simulate for the given values in Table 2. 10. Your simulation waveform. 11. Commnets.txt (if you have any). Submit the zipped le through the blackboard WARNING: Points will be taken o if you do not follow the above instructions