Process Technology and Design Parameter Impact on SRAM Bit-Cell Sleep Effectiveness

Guru Shamanna, B.S. Kshatri, R. Gaurav, Y.S. Tew, P. Marfatia, Y. Raghavendra, V.Naik
Intel Corporation #136 Airport Road, Bangalore 560017, India ABSTRACT SRAM Bit-Cell Sleep technique is extensively used in processors to minimize SRAM leakage power. However, magnitude of leakage power savings from SRAM bit-cell sleep technique is dependent on process technology and various design parameters. This paper analyzes influence of design parameters like VCCMIN_RET, DVS, ITD and NBTI on effectiveness of SRAM bit-cell sleep scheme. Impact of Process Technology on SRAM bit-cell sleep scheme effectiveness, due to transition from SiO2 to Hafnium based High-K gate dielectric material is also discussed in this paper. Silicon measurement results of a 3MByte SRAM array designed in 32nm High-K CMOS process is used to demonstrate diminishing effectiveness of SRAM bit-cell sleep technique. INTRODUCTION In this era of green computing, there is increased emphasis on power reduction, since power is constraining products from realizing their full potential. Amongst different options [1] that exist to reduce leakage power, supply voltage scaling has been the most effective technique. Scaling (or lowering) voltage has significant impact on leakage power, since transistor leakage current decreases exponentially [1] with supply voltage. SRAM bit-cell sleep technique extends this concept of voltage scaling, to reduce leakage power in 6T SRAM bit-cells. A sleep transistor is used in SRAM bit-cell sleep technique to lower (or scale) voltage across SRAM bit-cell, thus reducing SRAM bit-cell leakage power. Previous [2-3] work published on SRAM bit-cell sleep describes merits of different bit-cell sleep implementation schemes. Zhang etal., [4] quantify leakage power savings from bitcell sleep scheme based on a discrete SRAM chip designed in 65nm process technology. However, none of these prior works analyze effectiveness of SRAM bit-cell sleep scheme, comprehending I. design constraints existing in commercial microprocessors. In this paper, authors analyze impact of design parameters and process technology on SRAM bit-cell sleep scheme effectiveness on SRAM Arrays, embedded in microprocessors. II. SRAM Bit-Cell Sleep Overview Conventional SRAM bit-cell sleep techniques use a sleep transistor to lower voltage across 6T SRAM bit-cell. A sleep transistor is usually a high threshold voltage (Vt) PMOS [5] transistor inserted between regular power supply grid and SRAM bitcell as illustrated in Figure-1. In a typical PMOS transistor based sleep scheme, voltage across bitcell and resulting bit-cell leakage is dependent on sleep transistor width (Z). Voltage across SRAM bit-cell (VCC_SRAM) reduces with decrease in width of sleep transistor due to higher IR drop across sleep transistor. This implies that a smaller Z sleep transistor is preferred to minimize bit-cell leakage, since a lower VCC_SRAM value results in lower SRAM bit-cell leakage. In summary, SRAM bit-cell sleep effectiveness increases, if VCC_SRAM floor decreases or sleep transistor width decreases. A wake-up transistor is connected in parallel with sleep transistor (Figure-1) to minimize exit latency from sleep state and to mitigate performance degradation due to IR drop across sleep transistor.
Z1 < Z2 < Z3 <Z4

Sleep Transistors of different sizes (width)

VCC
Z1 Z2 Z3 Z4

VCC_SRAM

WAKE-UP TRANSSITOR
I_LEAK

WL

BL

BL#

Figure-1: Bit-Cell Sleep implementation using PMOS sleep transistor(s)

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III. Impact of Process Technology Scaling Gate Leakage (Igate) was a major contributor (Figure-2) to leakage power in 90/65nm process technology nodes due to aggressive scaling of gate oxide (Tox). Hence, SRAM arrays designed in 90nm and 65nm process technology nodes relied extensively upon SRAM bit-cell sleep technique to minimize gate leakage current. SRAM bit-cell sleep scheme minimized Igate, by lowering voltage (VCC_SRAM) across SRAM bit-cell using sleep transistor. Lowering VCC_SRAM resulted in an exponential decrease in Igate, as described by Equation-1:
V T
ox ox

gate

(1)

A is a constant, Tox is the gate oxide thickness Vox is the voltage (VCC_SRAM) across gate of the transistors in 6T SRAM bit-cell

Gate Leakage Percentage

V = A ox T ox

dielectric was non-availability of sufficient number of SiO2 atoms for continued Tox scaling. Transition to High-K gate dielectric material in 45nm process node, resulted in 25X reduction (Figure-3) of gate leakage current in SRAM bit-cell, when compared to 65nm process technology. In summary, a radical change in process technology resulted in bit-cell sleep technique losing its effectiveness in minimizing Igate, beyond 65nm process technology node. Even though, Igate reduction due to High-K transition is based on Intel proprietary Hi-K metal gate CMOS process [6], similar reduction in Igate has been reported in other commercially available Hi-K CMOS process [7] technologies.
40 35 30 25 20 15 10 5 0
90nm

It is also possible to achieve reduction in Igate by increasing Tox as described in Eqn-1. However, increasing Tox, affects electrical characteristics of transistor and has far reaching implications on transistor performance and process node scaling. Hence, the preferred option to reduce Igate in 90nm and 65nm process technology nodes was to lower VCC_SRAM using SRAM bit-cell sleep technique.

65nm

45nm

32nm

Figure-3: SRAM gate leakage contribution in Intel CMOS process

IV. Impact of Retention VCCMIN Data Retention Voltage (VCCMIN_RET) is the minimum voltage required by an SRAM bit-cell to retain stored data. This implies that power savings from SRAM bit-cell sleep scheme is maximum when voltage (VCC_SRAM) across SRAM bit-cell equals VCCMIN_RET. However, VCCMIN_RET for SRAM Arrays is a distribution (Refer Figure-4), due to Vt variation in transistors of SRAM bit-cell. Due to VCCMIN_RET distribution, VCC_SRAM floor increases, since worst case VCCMIN_RET value has to be chosen. A high VCC_SRAM floor increases bit-cell leakage due to larger voltage across bit-cell. Bit-cell leakage increases further in large SRAM arrays, as large SRAM arrays have a

Figure-2: Gate Leakage & Tox scaling in Intel CMOS process

However, effectiveness of SRAM bit-cell sleep in minimizing Igate reduced significantly in 45nm process node, due to adoption of Hafnium based High-K gate dielectric material. Transition to HighK dielectric material was essential in 45nm process node since SiO2 (gate oxide dielectric material used in 65nm process node) could not be scaled further due to prohibitive increase in Igate. Another factor influencing transition to High-K

Figure-4: Impact of SRAM Array Size on VCCMIN_RET

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wide VCCMIN_RET distribution as illustrated in Figure-4. Large SRAM Arrays have a wide VCCMIN_RET distribution, since spread in Vt variation increases as bit-cell count increases. In summary, VCCMIN_RET distribution results in a higher VCC_SRAM floor, due to which SRAM bitcell sleep effectiveness diminishes. V. Impact Of Dynamic Voltage Scaling (DVS) Supply Voltage (VCC) floor for SRAM Arrays with SRAM Bit-Cell sleep feature depend upon; Data Retention Voltage (VCCMIN_RET) of SRAM bit-cell and IR drop across PMOS sleep transistor. This dependence is given below in Equation-2:

Figure-5: Impact of Sleep Transistor Size on VCC Floor

VCC = {I leak Rsleep ( Z )} + VCCMIN _ RET

(2)

VCCMIN_RET = Bit-Cell Data Retention Voltage VCC = Supply Voltage Ileak = Bit-cell Leakage Current at VCCMIN_RET Rsleep= Sleep Transistor Resistance Z = Sleep Transistor Width (Z 1/ Rsleep) Equation-2 is critical since it establishes the relationship between sleep transistor width and supply voltage floor. It can be inferred from Eqn-2 that a high Rsleep, (or small Z) increases IR drop across sleep transistor, resulting in a higher VCC floor. This inference is also validated from silicon measurements shown in Figure-5. For example, it can be observed from Figure-5 that a Z1 sleep transistor width results in VCC floor of 700mv whereas a Z4 sleep transistor width (Z4 greater than Z1) results in a VCC floor of ~500mv. It is crucial to determine VCC floor associated with sleep transistor width a priori, since modern processors dynamically scale voltage to maximize performance per watt. For example, it can be observed from Figure-6, that the microprocessor can support dynamic voltage scaling (DVS) up to 700mv, if sleep transistor width Z1 is chosen. However the same processor can support DVS up to 600mv, if sleep transistor width Z2 is chosen (Z2 > Z1). SRAM Arrays embedded in processors supporting DVS, are compelled to select a sleep transistor with a large Z to improve DVS range. However, a large Z (or low Rsleep) reduces bit-cell sleep effectiveness, since VCC_SRAM floor increases as described in Section-2.

VI. Impact Of Inverse Temperature Dependence Optimizing SRAM bit-cell sleep design over a wide temperature spectrum is challenging, since VCCMIN_RET of bit-cell and Rsleep, exhibit strong temperature dependence. Relationship between supply voltage (VCC), Rsleep and VCCMIN_RET is comprehended in Equation-3 given below:

VCC = {I leak (T ) Rsleep (T )} + VCCMIN _ RET (T ) (3)

T = Junction Temperature Rsleep(T) and VCCMIN_RET(T) have an inverse dependence on temperature (ITD), since threshold voltage (Vt) of sleep transistor and SRAM bit-cell transistors increase with decrease in temperature. As a result of this increase in Vt, supply voltage (VCC) floor required to maintain equilibrium condition, as described in Equation-3 increases. It can be observed from Figure-6 that supply voltage floor required for retaining data stored in SRAM Bit-Cell increases by 50mv at -5C when compared to 75C, due to ITD effect. Since higher supply voltage floor has implications on other design metrics like power; microprocessors increase width (Z) of sleep transistor, to mitigate ITD effect. A large Z reduces SRAM Bit-Cell sleep effectiveness, since voltage across SRAM bit-cell increases as discussed in Section-2.

Figure-6: Impact of Temperature on VCC Floor

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VII. Impact Of NBTI Threshold Voltage (Vt) shift due to Negative Bias Temperature Instability (NBTI) is more pronounced on SRAM sleep transistor since gate of PMOS sleep transistor is constantly held at logic 0 level, which is the worst case stress condition for NBTI. A constant 0 bias, does not allow sleep transistor to recover from Vt drift, thus making PMOS sleep transistor more susceptible to NBTI, than regular digital circuits that switch between logic 0 and logic 1 levels. Due to NBTI, PMOS sleep transistor Vt, slowly drifts over time, resulting in a gradual increase in sleep transistor resistance. In scenarios where Vt drift is high, SRAM bit-cell may not be able to retain stored data, since VCC_SRAM level may drift below data retention voltage (VCCMIN_RET) of SRAM bit-cell. To prevent such silent data failures, operating voltage has to be gradually increased over time as illustrated in Figure-7, to compensate for drift in VCC_SRAM level. Instead of tracking drift in VCC_SRAM level, processors guard-band Time-0 VCCMIN_RET value, to minimize circuit design complexity. Guard-banding VCCMIN_RET, compel microprocessors to choose sleep transistor with a larger width (Z), as given by Equation-2. Sleep transistor with a large Z reduce bit-cell sleep scheme effectiveness, since voltage across bit-cell increases as described in section-2.

SRAM bit-cell sleep scheme. SRAM bit-cell sleep scheme effectiveness can be improved by leveraging upon the very same design constraints that have rendered bit-cell sleep technique ineffective. For example, leakage power savings from SRAM bit-cell sleep scheme can be increased by disabling bit-cell sleep at lower VCC in processors supporting DVS feature. Disabling SRAM bit-cell sleep at lower VCC levels enables sleep design to be optimized for higher VCC.
Leakage Power Savings (mw)
55 50 45 40 35 30 25 20 15 10 5 VCC = 0.90V VCC = 0.95V VCC = 1.0V

Z1 < Z2 < Z3 .. < Z6 Z1 Z2 Z3

Z4

Z5

Z6

Sleep Transistor Size

Figure-8: Leakage Power Savings with SRAM bit-cell sleep in 3MByte SRAM (32nm Silicon Data) Array

Another factor contributing to bit-cell sleep ineffectiveness is a wide spread in data-retention voltage as discussed in Section-4. Since spread in VCCMIN_RET is function of array size (Figure-4), a region based sleep transistor width selection scheme can be adopted. Region based sleep transistor width selection approach improves bitcell sleep effectiveness, since sleep transistor resistance selection can be better optimized due to a narrower VCCMIN_RET distribution. REFERENCES
1. V. Venkatachalam et al., Power Reduction Techniques in Microprocessor Systems ACM Computing Surveys, Vol 3, pp 195237, September 2005. 2. M. Powell et al., Gated Vdd: A circuit technique to reduce leakage power in deep-submicron cache memories Proceedings of ISLPED, pp 90-95 , 2000. 3. N. Kim et al., Circuit and Microarchitectural Techniques for reducing cache leakage power IEEE Transactions on VLSI, vol 12, number 2, pp 167-182, Feb 2004. 4. K. Zhang et al., SRAM Design on 65nm CMOS Technology with Dynamic Sleep Transistor for leakage reduction IEEE JSSCC, Vol 40, pp 895-900, April 2005. 5. F. Hamzaoglu, K.Zhang et al., A 3.8 GHz 153 Mb SRAM Design in 45nm High-K Metal Gate CMOS Technology IEEE JSSCC, Vol 44, pp 148-154, January 2009. 6. K. Kuhn et al., Intels 45nm CMOS Process Technology, Intel Technology Journal, Vol 12, Issue-2, June 2008. 7. H.S Yang et al., Scaling of 32nm low power SRAM with high-k metal gate Proc of IEDM, 2008 pp 237-240, 2008.

Figure-7: Increase in Supply Voltage (VCC) due to NBTI

VIII. SUMMARY A major reason for diminishing effectiveness of SRAM bit-cell technique is inherent goodness of High-K Gate Dielectric used in modern CMOS process along with processor design constraints like NBTI, ITD and VCCMIN_RET distribution. Diminishing effectiveness of SRAM bit-cell sleep is evident by the fact that a meager 10-50mw leakage power savings (Figure-8) is attained from

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