A New Single-Phase Single Source Nine Level Boost

Inverter Topology
ABSTRACT
In this, a new single-phase single stage single source nine-level boost
inverter topology is proposed with selfvoltage balancing along with the reduce
switch count. The proposed topology is aimed to design for the renewable
energy sources interfacing to the loads, which require higher voltage
magnitudes. The proposed topology gives twice voltage booting feature without
using any dc-dc converter. The topology proposed in this paper uses a single dc
voltage source with two capacitors to generate a nine-level output voltage
waveform. Nearest level control modulation technique has been used for the
generation of gate pulse for the different switches used in the proposed
structure. The number of levels are increased to 11 with introduction of one
more capacitor without compromising of self voltage balancing of capacitors.
The proposed system is simulated in MATLAB/Simulink software.

INTRODUCTION
For medium and high voltage/power applications, multilevel inverters (MLIs)
have been widely accepted power converter for the dc-ac power conversion
with applications related to renewable energy resources, industrial motor drives,
power system applications including FACTS and HVDC transmission system,
etc. The acceptability of the MLI is due to the several advantages associated
with it. These advantages include improved output voltage (higher fundamental
voltage and reduced harmonic distortion), reduced voltage stress the switches,
low voltage rating of switches for high voltage application, and reduced size of
filters. Diode-clamped MLI (DCMLI), flying capacitor MLI (FCMLI) and
cascade Hbridge (CHB) have been the traditional MLI topology. However, for a
higher number of levels, these topologies suffer from a higher number of
components and capacitor voltage balancing. However, several MLI topologies
have been proposed with the reduce switch count. The output voltage of most of
the renewable energy resources has been of low level. For higher voltage
application, the boosting has been the essential feature for the topologies to be
used for high voltage applications. One such category of the multilevel inverter
topologies has been the switched capacitor based boost inverter topologies. This
category of topologies uses single dc voltage source with capacitors. Multiple
capacitors are used in different charging and discharging mode to give the
boosting of the input voltage. However, with switched capacitor-based
topologies, the reduced number of components (capacitors and power
semiconductor devices) have been an important aspect. Several switched
capacitor-based topologies have been proposed in the literature. One such
topology has been proposed. For nine-level output voltage waveform, the
topology proposed uses 19 switches with three capacitors. The high number of
the component has been the main issue the topology. Similarly, uses 16
switches and two capacitors for seven-level inverter output. Another topology
based on switched capacitor concept has been proposed, which uses 13 switches
with three capacitors for nine-level output voltage. A new boost topology has
been proposed with a single source; however, for nine-level output voltage, four
capacitors are required with 17 switches and four diodes. Apart from the higher
component count, in the topology, the capacitors are charged in the only
positive half cycle. This causes a higher voltage ripple of the capacitor voltages.
A seven-level boost topology with a single source structure has been proposed.
However, the higher switch count has been the main issue.

PROBLEM STATEMENT
In this paper, a new single-source nine-level boost inverter topology has been
proposed. The proposed topology uses 13 switches and two capacitors for nine-
level generations. The proposed topology exhibits the self-voltage balancing of
the capacitor without any auxiliary circuit. The operation of the proposed
topology with the modulation scheme has been described in this. The number of
levels can be increased with increase in number of capacitors along with
switching devices.

LITERATURE SURVEY
H. Akagi, “Multilevel Converters: Fundamental Circuits and Systems,”. This
paper provides a chronological overview of the topology for multilevel
converters, and discusses their different terminology usages and characteristics.
The multilevel converters include three-level neutral-point-clamped (NPC) and
neutral-point-piloted (NPP) inverters, three-level and four-level flying-capacitor
(FLC) inverters, and a family of modular multilevel cascade converters. Some
have already been put into commercial use, some have been on a research and
development stage, and others have been on an academic research stage. This
paper pays much attention to six family members of the modular multilevel
cascade converters, intended for grid-tied applications and medium-voltage
high-power motor drives.
M. D. Siddique, S. Mekhilef, N. M. Shah, and M. A. Memon, “Optimal Design
of a New Cascaded Multilevel Inverter Topology with Reduced Switch Count,”.
Multilevel inverters (MLIs) are a great development for industrial and
renewable energy applications due to their dominance over conventional two-
level inverter with respect to size, rating of switches, filter requirement, and
efficiency. A new single-phase cascaded MLI topology is suggested in this
paper. The proposed MLI topology is designed with the aim of reducing the
number of switches and the number of dc voltage sources with modularity while
having a higher number of levels at the output. For the determination of the
magnitude of dc voltage sources and a number of levels in the cascade
connection, three different algorithms are proposed. The optimization of the
proposed topology is aimed at achieving a higher number of levels while
minimizing other parameters. A detailed comparison is made with other
comparable MLI topologies to prove the superiority of the proposed structure. A
selective harmonic elimination pulse width modulation technique is used to
produce the pulses for the switches to achieve high-quality voltage at the output.
Finally, the experimental results are provided for the basic unit with 11 levels
and for cascading of two such units to achieve 71 levels at the output.

M. Vijeh, M. Rezanejad, E. Samadaei, and K. Bertilsson, “A General Review of

Multilevel Inverters Based on Main Submodules: Structural Point of View,”.
Multilevel inverters (MLIs) are being used in wide range of power electronic
applications. These converters have attracted a lot of attention during recent
years and exist in different topologies with similar basic concepts. This paper
presents five main submodules (SMs) to be used as the basic structures of MLIs.
The paper reviews the common MLI topologies from the structural point of
view. The topologies are divided into the different SMs to show conventional
MLI configurations and future topologies that can be created from the main
SMs. A comparative study between different topologies is performed in detail.
The MLIs are categorized and investigated with from different perspectives
such as the number of components, the ability to create inherent negative
voltage, working in regeneration mode and using single dc source.

K. K. Gupta, A. Ranjan, P. Bhatnagar, L. K. Sahu, and S. Jain, “Multilevel

Inverter Topologies With Reduced Device Count: A Review,”. Multilevel
inverters have created a new wave of interest in industry and research. While
the classical topologies have proved to be a viable alternative in a wide range of
high-power medium-voltage applications, there has been an active interest in
the evolution of newer topologies. Reduction in overall part count as compared
to the classical topologies has been an important objective in the recently
introduced topologies. In this paper, some of the recently proposed multilevel
inverter topologies with reduced power switch count are reviewed and analyzed.
The paper will serve as an introduction and an update to these topologies, both
in terms of the qualitative and quantitative parameters. Also, it takes into
account the challenges which arise when an attempt is made to reduce the
device count. Based on a detailed comparison of these topologies as presented
in this paper, appropriate multilevel solution can be arrived at for a given
application.

A. Ioinovici, "Switched-capacitor power electronics circuits", One of the main

orientations in power electronics in the last decade has been the development of
switching-mode converters without inductors and transformers. Light weight,
small size and high power density are the result of using only switches and
capacitors in the power stage of these converters. Thus, they serve as ideal
power supplies for mobile electronic systems (e.g. cellular phones, personal
digital assistants, and so forth). Switched-capacitor (SC) converters, with their
large voltage conversion ratio, promise to be a response to such challenges of
the 21st century as high-efficiency converters with low EMI emissions and the
ability to realize steep step-down of the voltage (to 3 V or even a smaller supply
voltage for integrated circuits) or steep step-up of the voltage for automotive
industry or Internet services in the telecom industry. This paper is a tutorial of
the main results in SC-converter research and design.

Y. Hinago and H. Koizumi, "A Switched-Capacitor Inverter Using

Series/Parallel Conversion With Inductive Load", A novel switched-capacitor
inverter is proposed. The proposed inverter outputs larger voltage than the input
voltage by switching the capacitors in series and in parallel. The maximum
output voltage is determined by the number of the capacitors. The proposed
inverter, which does not need any inductors, can be smaller than a conventional
two-stage unit which consists of a boost converter and an inverter bridge. Its
output harmonics are reduced compared to a conventional voltage source single
phase full bridge inverter. In this paper, the circuit configuration, the theoretical
operation, the simulation results with MATLAB/SIMULINK, and the
experimental results are shown. The experimental results accorded with the
theoretical calculation and the simulation results.

Y. Ye, K. W. E. Cheng, J. Liu and K. Ding, "A Step-Up Switched-Capacitor

Multilevel Inverter With Self-Voltage Balancing", The objective of this paper is
to propose a new inverter topology for a multilevel voltage output. This
topology is designed based on a switched capacitor (SC) technique, and the
number of output levels is determined by the number of SC cells. Only one dc
voltage source is needed, and the problem of capacitor voltage balancing is
avoided as well. This structure is not only very simple and easy to be extended
to a higher level, but also its gate driver circuits are simplified because the
number of active switches is reduced. The operational principle of this inverter
and the targeted modulation strategies are presented, and power losses are
investigated. Finally, the performance of the proposed multilevel inverter is
evaluated with the experimental results of an 11-level prototype inverter.

E. Babaei and S.S. Gowgani, "Hybrid Multilevel Inverter Using Switched

Capacitor Units", In this paper, two new topologies are proposed for multilevel
inverters. The proposed topologies consist of a combination of the conventional
series and the switched capacitor inverter units. The proposed topologies reduce
the number of switches and isolated dc voltage sources, the variety of the dc
voltage source values, and the size and cost of the system in comparison with
the conventional topologies. In addition, the proposed topologies can double the
input voltage without a transformer. There is no need for complicated methods
to balance the capacitor voltage. The simulation and experimental results of
single-phase 25- and 17-level inverters are given to prove the correct operation
of the proposed topologies.

W. Peng, Q. Ni, X. Qiu and Y. Ye, "Seven-Level Inverter With Self-Balanced

Switched-Capacitor and Its Cascaded Extension", A switched-capacitor based
seven-level inverter is proposed in this work. It consists of two capacitors, two
diodes, and eight transistors. The eight transistors form two H-bridges resulting
in a simple structure and easy design of gate drivers. Capacitors' voltages are
balanced automatically as they operate in parallel with the input voltage source
a few times during each cycle of output voltage. Voltage ripples and power loss
are analyzed in detail. To obtain more output levels, the cascaded structure of
the seven-level inverter is also investigated and a power balancing strategy is
used to simplify design work. Finally, the effectiveness of the work is
experimentally demonstrated by both the seven-level and 13-level prototypes. It
indicates that the proposed inverter is capable of powering different types of
loads, and its efficiency is up to above 97%.

R. Barzegarkhoo, M. Moradzadeh and F. Blaabjerg, "A new boost switched-

capacitor multilevel converter with reduced circuit devices", In this paper, a
novel platform for the single phase switched-capacitor multilevel inverters
(SCMLIs) is presented. It has several advantages over the classical topologies,
such as an appropriate boosting property, higher efficiency, lower number of
required dc voltage sources, and other accompanying components with less
complexity and lower cost. The basic structure of the proposed converter is
capable of making nine-level of the output voltage under different kinds of
loading conditions. Hereby, by using the same two capacitors paralleled to a
single dc source, a switched-capacitor (SC) cell is made that contributes to
boosting the value of the input voltage. In this case, the balanced voltage of the
capacitors can be precisely provided on the basis of the series-parallel technique
and the redundant switching states. Afterward, to reach the higher number of
output voltage levels, two suggested SC cells are connected to each other with a
new extended configuration. Therefore, by the use of a reasonable number of
required power electronic devices, and also by utilizing only two isolated dc
voltage sources, which their magnitudes can be designed based on either
symmetric or asymmetric types, a 17- and 49-level of the output voltage are
obtained. Based on the proposed extended configuration, a new generalized
version of SCMLIs is also derived. To confirm the precise performance of the
proposed topologies, apart from the theoretical analysis and a complete
comparison, several simulation and experimental results are also given.

METHODOLOGY

The structure of 1ϕ proposed multi level inverter is shown below.

The proposed single-phase nine-level boosting inverter, which is powered by a

single dc voltage source, consists of 13 unidirectional switches from S1 to S11
and two capacitors C1 and C2. The input dc voltage source with magnitude Vdc
is used to change both capacitors in series, thus resulting in the capacitor
voltage equal to half of dc voltage source, i.e., VC1 = VC2 = 0.5Vdc with VC1
and VC2 is the capacitor voltage of capacitor C1 and C2 respectively.
Both capacitors are charged during zero, and Vdc voltage states up to the
magnitude of 0.5Vdc with series connection to the input dc voltage source of
magnitude Vdc. On the other hand, capacitor C2 is discharged at voltage levels
of 0.5Vdc and 1.5Vdc while capacitor C1 is discharged only during voltage
level of 2Vdc. Both capacitors are connected in series to the input dc voltage
source to produce the peak of the output voltage, i.e., Vdc. A similar operation
occurs for the negative half cycle with the discharging of the capacitors are
interchanged.

From the swi9tching table, over a complete fundamental period, the charging
and discharging times for both capacitors are the same, results in the self-
voltage balancing of both capacitors. For the proposed topology, nearest level
control (NLC) pulse width modulation technique is used [22]. The graph
provided below shows the NLC method in which, the staircase waveform Vstair
is produced based on the reference signal, which is a purely sinusoidal, i.e.,
Vref.
The switching angles can be estimated based on the midpoint between two
nearest voltage level. The modulation index for the NLC method is given by

The maximum voltage ripple is attained approximately by

The capacitance of C1 can be calculated by

The number of levels can be extended by increasing the number of switched

capacitors.

REFERENCES

H. Akagi, “Multilevel Converters: Fundamental Circuits and Systems,” Proc.

IEEE, vol. 105, no. 11, pp. 2048–2065, Nov. 2017.

M. D. Siddique, S. Mekhilef, N. M. Shah, and M. A. Memon, “Optimal Design

of a New Cascaded Multilevel Inverter Topology with Reduced Switch Count,”
IEEE Access, pp. 24498–24510, 2019.

M. Vijeh, M. Rezanejad, E. Samadaei, and K. Bertilsson, “A General Review of

Multilevel Inverters Based on Main Submodules: Structural Point of View,”
IEEE Trans. Power Electron., pp. 1–1, 2019.

K. K. Gupta, A. Ranjan, P. Bhatnagar, L. K. Sahu, and S. Jain, “Multilevel

Inverter Topologies With Reduced Device Count: A Review,” IEEE Trans.
Power Electron., vol. 31, no. 1, pp. 135–151, Jan. 2016.

A. Ioinovici, "Switched-capacitor power electronics circuits", IEEE Circuits

Syst. Mag., vol. 1, no. 3, pp. 37-42, Jul./Sep. 2001.
Y. Hinago and H. Koizumi, "A Switched-Capacitor Inverter Using
Series/Parallel Conversion With Inductive Load", IEEE Trans. Ind. Electron.,
vol. 59, no. 2, pp. 878-887, Feb. 2012.

Y. Ye, K. W. E. Cheng, J. Liu and K. Ding, "A Step-Up Switched-Capacitor

Multilevel Inverter With Self-Voltage Balancing", IEEE Trans. Ind. Electron.,
vol. 61, no. 12, pp. 6672-6680, Dec. 2014.

E. Babaei and S.S. Gowgani, "Hybrid Multilevel Inverter Using Switched

Capacitor Units", IEEE Trans. Ind. Electron., vol. 61, no. 9, pp. 4614-4621,
Sept. 2014.

W. Peng, Q. Ni, X. Qiu and Y. Ye, "Seven-Level Inverter With Self-Balanced

Switched-Capacitor and Its Cascaded Extension", IEEE Trans. Power Electron.,
vol. 34, no. 12, pp. 11889-11896, Dec. 2019.

R. Barzegarkhoo, M. Moradzadeh and F. Blaabjerg, "A new boost switched-

capacitor multilevel converter with reduced circuit devices", IEEE Trans.
Power Electron., vol. 33, no. 8, pp. 6738-6754, Aug. 2018.