Ray Hueting
Power electronics & EMC (PE) Group
EEMCS department
Building Carré, CR2613
[Link]@[Link]
MOSFET/switch: motivation
Most common in advanced IC technology
CMOS
RF analogue:
RF switches
Sensing:
Pressure, gas sensor
Biosensor
MOS Memory devices
DRAM
Flash
…
(RF) Power devices:
Switches
Synchronous rectifiers
Emerging devices (I), Electrostatic integrity
Operation principle MOSFET
Diffusion: high barrier Drift: low barrier, resistance
Emerging devices (I), Electrostatic integrity
Figures of merit (FOMs)(I)
VDS=VDD
Dynamic/active power loss
2
𝑃𝑃dyn ∝ 𝐶𝐶ins 𝑉𝑉DD
A. Chandrakasan and R. Brodersen, Proc. IEEE, 83(4), 1995
On-current ION should be maximal (VDS=VDD, saturation)
Dynamic power loss, hence supply voltage VDD, minimal
3/10/2023 Emerging devices (I), Electrostatic integrity
FOMs (II)
Diffusion, thermionic emission:
𝑽𝑽TH 𝑉𝑉GS
𝐼𝐼D ∝ exp
𝑰𝑰ON 𝑚𝑚 � 𝑢𝑢 𝑇𝑇
Ideality factor:
𝑑𝑑𝑉𝑉𝐺𝐺𝐺𝐺
𝑚𝑚 = ≥1
𝑑𝑑𝜓𝜓𝑠𝑠
Log (ID)
“Boltzmann Tyranny”
−1
~1/m 𝑑𝑑log 𝐼𝐼D
𝑰𝑰OFF 𝑆𝑆𝑆𝑆 ≡ =
𝑑𝑑𝑉𝑉GS
VDS=VDD m 𝑘𝑘𝑘𝑘 � ln 10
≥ 60 mV/dec
𝑞𝑞
0 𝑽𝑽DD
VGS
Off-current IOFF should be minimal
Hence, ION/IOFF should be maximal (>105)
3/10/2023 Emerging devices (I), Electrostatic integrity
FOMs (III)
𝑽𝑽TH
𝑰𝑰ON
Log (ID)
Static power loss
𝑰𝑰OFF 𝑃𝑃stat = 𝐼𝐼OFF � 𝑉𝑉DD
~1/m
VDS=VDD
0 𝑽𝑽DD
VGS
Simply reducing VTH increases IOFF (possibly m as well)
ION/IOFF to be maximized A. Chandrakasan and R. Brodersen, Proc. IEEE 83(4), 1995
3/10/2023 Emerging devices (I), Electrostatic integrity
FOMs (IV)
Delay
𝑄𝑄GG 𝐶𝐶ins � 𝑉𝑉DD
𝜏𝜏 = 𝑓𝑓o ∝
𝐼𝐼D 𝑉𝑉GS =𝑉𝑉DD
𝐼𝐼ON
QGG = gate charge
… or more accurately
𝑉𝑉DD
𝐶𝐶GG 𝑉𝑉DS , 𝑉𝑉GS
𝜏𝜏 = � 𝑓𝑓o 𝑊𝑊𝐿𝐿G 𝑑𝑑𝑉𝑉DS
0 𝐼𝐼D 𝑉𝑉DS , 𝑉𝑉GS
Tradeoff between power and delay (Energy)
2
𝑃𝑃dyn � 𝜏𝜏 ∝ 𝐶𝐶ins � 𝑉𝑉𝐷𝐷𝐷𝐷
P. Packan, “Device and Circuit Interactions”, IEDM 2007 Short Course
3/10/2023 Emerging devices (I), Electrostatic integrity
Downscaling according to Moore’s law
Moore’s law:
number of transistors in IC doubles every 2 years
Motivation: cost reduction & more functionality & speed
power
Emerging devices (I), Electrostatic integrity
Downscaling limit
Issues:
Minimum dimension lithography (~193-13.5 nm)
Gate control for small dimensions, ballistic transport
Power consumption (VDD~0.7V)
Other approaches?
Alternative electron device architectures + new materials
Beyond CMOS, emerging devices
Radical different physics (e.g., spin, photons)
Still under debate and a lot is happening!
Emerging devices (I), Electrostatic integrity
Short channel effects (“Early effect”)
Long channel MOSFET: Short channel MOSFET:
+ +
G
S
++
D S
G
++
D
N+ N+ N+ N+
P- P-
L ≈ LG L << LG
𝑊𝑊 2
𝐼𝐼D = 𝜇𝜇𝑛𝑛 𝐶𝐶ins 𝑉𝑉GS − 𝑉𝑉T
2𝐿𝐿
Emerging devices (I), Electrostatic integrity
Short channel transistor (I)
Long channel: 1µm Short channel: 65nm
Hole concentration << doping concentration (low VT)
Increased electron concentration: high subthreshold ID
Less gate control: charge affected by drain/source
Emerging
Possible solution: high devices
(“halo”) (I), Electrostatic
doping in channel integrity
region, but…
Short channel transistor (II)
Long channel: 1µm Short channel: 65nm
Potential barrier is reduced in the channel
… VT drops
Emerging devices (I), Electrostatic integrity
Short channel transistor (III)
VT drops for small gate lengths
VT drops for high drain bias (DIBL)
… Ideality factor m > 1
Emerging devices (I), Electrostatic integrity
Non-ideal subthreshold current
Diffusion (or thermionic emission):
𝑑𝑑𝑄𝑄i 𝑄𝑄i,D − 𝑄𝑄i,S
𝐼𝐼D = 𝑊𝑊𝑊𝑊𝑢𝑢 𝑇𝑇 � = −𝑊𝑊𝑊𝑊 �
𝑑𝑑𝑑𝑑 𝐿𝐿
𝜓𝜓s 𝑞𝑞𝑞𝑞
𝑢𝑢𝑇𝑇 − DS
∝ 𝐼𝐼0 � 𝑒𝑒 1−e 𝑘𝑘𝑘𝑘
Similar to BJT/diode, however: 1) Gate and 2) 2D/3D
Complicated relation between surface potential and VGS:
𝑉𝑉GS 𝑞𝑞𝑞𝑞 𝜕𝜕𝑉𝑉GS
𝑚𝑚 𝑢𝑢𝑇𝑇 − DS with 𝑚𝑚 = ≥1
∝ 𝐼𝐼0 � 𝑒𝑒 1−e 𝑘𝑘𝑘𝑘
𝜕𝜕𝜓𝜓s
caused by:
Voltage division capacitances (Long channel)
Short-channel effects
S.M. Sze and K.K. Ng, “Physics of Semiconductor Devices”, 3rd ed., Wiley, 2007
Emerging devices (I), Electrostatic integrity
Subthreshold current
Diffusion, thermionic emission:
𝑽𝑽TH 𝑉𝑉GS
𝐼𝐼D ∝ exp
𝑰𝑰ON 𝑚𝑚 � 𝑢𝑢 𝑇𝑇
Ideality factor:
𝑑𝑑𝑉𝑉𝐺𝐺𝐺𝐺
𝑚𝑚 = ≥1
𝑑𝑑𝜓𝜓𝑠𝑠
Log (ID)
“Boltzmann Tyranny”
−1
~1/m 𝑑𝑑log 𝐼𝐼D
𝑰𝑰OFF 𝑆𝑆𝑆𝑆 ≡ =
𝑑𝑑𝑉𝑉GS
m 𝑘𝑘𝑘𝑘 � ln 10
≥ 60 𝑚𝑚𝑚𝑚/dec
𝑞𝑞
0 𝑽𝑽DD
VGS
How to obtain a relation for m?
3/10/2023 Emerging devices (I), Electrostatic integrity
Subthreshold Long channel bulk MOSFET
MOS capacitor: voltage divider
M
O 𝑉𝑉GS = 𝑉𝑉ins + 𝜓𝜓s + 𝜙𝜙m − 𝜙𝜙s
S 𝑄𝑄d
𝜓𝜓s = + 𝑉𝑉GS − 𝜙𝜙m − 𝜙𝜙s
𝐶𝐶ins
Surface potential complicated function of VGS
Alternatively,
𝐶𝐶t 1
𝐶𝐶s � 𝜓𝜓s = 𝐶𝐶t � 𝑉𝑉GS 𝜓𝜓s = 𝑉𝑉GS � = 𝑉𝑉GS �
𝐶𝐶s 𝑚𝑚
𝐶𝐶ins � 𝐶𝐶s 𝐶𝐶ins + 𝐶𝐶s
𝐶𝐶t = 𝑚𝑚 = ≥1
𝐶𝐶s + 𝐶𝐶ins 𝐶𝐶ins
Both Cs and m not necessarily constant, depend on ψs
S.M. Sze and K.K. Ng, “Physics of Semiconductor Devices”, Wiley, 3rd ed., 2007
Emerging devices (I), Electrostatic integrity
2-D effects: Natural length (I)
Long channel: 1µm Short channel: 65nm
λ
λ
Important measure for SCE: natural length λ
natural length λ: that length when potential drops by factor 1/e
Emerging devices (I), Electrostatic integrity
2-D effects: Natural length (II)
Bulk MOSFET:
𝜌𝜌 𝑞𝑞𝑁𝑁𝐴𝐴
𝛻𝛻 2 𝜓𝜓 =− =
𝜀𝜀s 𝜀𝜀s
At the surface (y = 0) can be derived
𝜕𝜕 2 𝜓𝜓s 𝜓𝜓s ±
𝑥𝑥
2
− 2 = 0 or 𝜓𝜓s = 𝜓𝜓s0 � 𝑒𝑒 𝜆𝜆
𝜕𝜕𝑥𝑥 𝜆𝜆
with surface potential 𝜓𝜓s and natural (or device characteristic) length
1 𝜀𝜀s
𝜆𝜆 = � 𝑡𝑡ins 𝑡𝑡d
𝜂𝜂 𝜀𝜀ins
𝜂𝜂 = channel field parameter (~1.2), 𝑡𝑡d = channel thickness (𝑡𝑡d ≈ 𝑥𝑥j )
High 𝐶𝐶ins = 𝜀𝜀ins ⁄𝑡𝑡ins results in small λ hence better EI
K.W. Terrill, C. Hu and P.K. Ko, IEEE Electr. Dev. Lett., 5(11), 1984
Emerging devices (I), Electrostatic integrity
Electrostatic integrity factor (I)
VT drops for small gate lengths
VT drops for high drain bias (DIBL)
“Early effect”
Emerging devices (I), Electrostatic integrity
Electrostatic integrity factor (II)
Threshold voltage roll-off:
𝑉𝑉T = 𝑉𝑉T∞ − 𝑆𝑆𝑆𝑆𝑆𝑆 − 𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷
with 𝑉𝑉T∞ = threshold voltage long channel device (L=LG), and
𝑆𝑆𝑆𝑆𝑆𝑆 = 0.64 � 𝐸𝐸𝐸𝐸 � 𝑉𝑉BI 𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 = 0.80 � 𝐸𝐸𝐸𝐸 � 𝑉𝑉DS
and the (adjusted) EI factor:
2
𝑥𝑥j 2 λ
𝐸𝐸𝐸𝐸 = 1 + 𝜂𝜂
𝐿𝐿 𝐿𝐿
The higher the EI factor, the poorer EI
T. Skotnicki, G. Merckel, and T. Pedron, IEEE Electr. Dev. Lett., 9(11), 1988
J.-P. Colinge, “FinFETs and Other Multi-Gate Transistors”, Springer, 2008
Emerging devices (I), Electrostatic integrity
Short channel transistor (IV)
𝑊𝑊 2
𝐼𝐼D = 𝜇𝜇𝑛𝑛 𝐶𝐶ins 𝑉𝑉GS − 𝑉𝑉T
2𝐿𝐿
long channel
SCE: Low output resistance (“Early effect”)
Emerging devices (I), Electrostatic integrity
Technology overview
disruptive/invasive device physics (“Beyond Moore”)
+ + +
AlN
- - -
I-MOS,
TunnelFET SGFET FerroFET
Power
Electrostatics
Strain, High-κ
Fin’s, NWs, Schottky
III-Vs, CNTs Gate
NRs
noninvasive miniaturization (“more Moore”)
… or combinations of proposed architectures
Emerging devices (I), Electrostatic integrity
Short channel effects (experiment, II)
Ion
Ioff
Gate
S D
Gate looses control.
10nm device cannot be switched off
Dr. M.J.H. van Dal, TSMC, with courtesy
Emerging devices (I), Electrostatic integrity
Improved electrostatic integrity (EI)
Ion Ion
Ioff
Better gate control
@ short gate length
Ioff
Dr. M.J.H. van Dal, TSMC, with courtesy
Employ ultrathin body (UTB) layers for better gate control (EI)
Fully-depleted (FD)-SOI (Silicon-On-Insulator) technology
24
(FD) FinFET technology
Emerging devices (I), Electrostatic integrity
The FinFET (I)
Tri-Gate
FinFET:
more gate control (“Electrostatic integrity”, EI) than SOI-FET
EI: high (gate “fringing”) capacitances (see also power FETs)
High series resistance
Gate width not easy to scale (“Discrete design”)
D. Hisamoto et al., IEEE Trans. Electr. Dev., 47(12), 2000; J.-P. Colinge et al., “FinFETs and Other Multi-Gate Transistors”,
Springer, 2008
Emerging devices (I), Electrostatic integrity
FinFET examples
22nm FinFET process: Intel (IEDM 2012)
HfSiO + TiN
Gate
Fin
10 nm
Dr. M.J.H. van Dal, TSMC research, with courtesy
Emerging devices (I), Electrostatic integrity
The FinFET (II)
103
102
101 WFIN =
IDDS(µA/µm)
8 nm
42 nm
5 nm 100 22 nm
WFIN ↓ 32 nm
10 nm 32 nm
22 nm
10-1 42nm
nm
8
15 nm
10-2
LG = 40 nm
10-3
0.0 0.2 0.4 0.6 0.8 1.0
VG (V)
Fin width scaling reduces IOFF with some compromising on ION
Dr. M. van Dal, TSMC Research, Belgium, with courtesy
Emerging devices (I), Electrostatic integrity
FD-SOI examples
FD-SOI by ST resp. GlobalFoundries
Source:
[Link]
Emerging devices (I), Electrostatic integrity
FD UTB FETs
Single gate Double gate
(e.g., SOI thick BOX): (e.g., SOI thin BOX, FinFET) :
oxide
semiconductor
Buried oxide (BOX)
Surrounding gate
(e.g., quadruple gate & cylindrical gate):
J.-P. Colinge, “FinFETs and Other Multi-Gate Transistors”, Springer, 2008
Emerging devices (I), Electrostatic integrity
Multiple gate devices
Ultimate gate control: gate all around (GAA), nanowire
~2.5 µm
~0.7 µm
Nanowires (NWs) for flash memories
Emerging devices (I), Electrostatic integrity
Subthreshold Long channel FD UTB FET
M MOS capacitor: voltage divider
O 𝑉𝑉GS = 𝑉𝑉ins + 𝜓𝜓s + 𝜙𝜙m − 𝜙𝜙s
𝑄𝑄d
S 𝑉𝑉GS = + 𝜓𝜓s + 𝜙𝜙m − 𝜙𝜙s
𝐶𝐶ins
Depletion charge in body is negligible:
1) No energy bandbending (“volume inversion”) Electrostatic
2) 𝜓𝜓s ∝ 𝑉𝑉GS and strongly depends on WFs doping*
𝐶𝐶ins + 𝐶𝐶s
𝐶𝐶s ≈ 0 ⇒ 𝑚𝑚 = =1
𝐶𝐶ins
However, more interfaces, possibly more interface traps:
𝐶𝐶ins + 𝐶𝐶it
𝑚𝑚 = ≥1
𝐶𝐶ins
Y. Taur, IEEE Electr. Dev. Lett., 21(5), 2000; *G. Gupta, B. Rajasekharan, and R.J.E. Hueting, IEEE TED, 64(8), 2017
Emerging devices (I), Electrostatic integrity
Natural length
UTB FET: 𝜌𝜌
𝛻𝛻 2 𝜓𝜓 =− ≈0
𝜀𝜀s
𝑥𝑥
Hence, 𝜓𝜓s = 𝜓𝜓s0 � 𝑒𝑒
±
𝜆𝜆
with surface potential 𝜓𝜓s and natural length
1 𝜀𝜀s
𝜆𝜆 = � 𝑡𝑡ins 𝑡𝑡s
𝜂𝜂 𝜀𝜀ins
𝜂𝜂 = 1 (SG),2 (DG) & 4 (QG), and 𝑡𝑡s = semiconductor thickness
More gates & UTBs result in a small λ hence better EI
… towards small devices with high ION/IOFF!
J.-P. Colinge, “FinFETs and Other Multi-Gate Transistors”, Springer, 2008
Emerging devices (I), Electrostatic integrity
Short channel effects (experiment)
180-nm (Rodder, IEDM 1995) 14-nm (Natarajan, IEDM 2014)
Ion
Ioff
Prof. dr. J. Schmitz, UT, with courtesy
Emerging devices (I), Electrostatic integrity
Heterostructures: narrow gap, high mobility & DOS
Emerging devices K.
(I),Saraswat, IEDM Short course, 2007
Electrostatic integrity
Multiple gate devices in CMOS
Intel, Samsung, TSMC: Nanowire devices
Emerging devices (I), Electrostatic integrity
Backup slides
3/10/2023 Emerging devices (I), Electrostatic integrity
Definition full depletion, UTB
Fully depleted (FD-)body: No/hardly energy band bending
Debye length greater than semiconductor dimensions ⊥ current flow.
So,
𝜀𝜀s 𝑢𝑢 𝑇𝑇
𝑡𝑡s ≲ 𝐿𝐿D = 𝜂𝜂
𝑞𝑞 𝑁𝑁
𝜂𝜂 = 1 (SG),2 (DG), 𝑡𝑡s = SOI thickness/fin width, N = concentration
UTB = Ultra Thin Body
Body dimensions smaller than thermal de Broglie wavelength
(quantum confinement, Si: ~15nm):
2𝜋𝜋𝜋
𝑡𝑡s ≲ λ = ∗
𝑚𝑚𝑐𝑐,𝑣𝑣 𝑘𝑘𝑘𝑘
∗
𝑚𝑚𝑐𝑐,𝑣𝑣 = DOS effective mass, ℏ = reduced Planck constant (h/2π)
So, an UTB is a FD-body, but not the other way around.
S.M. Sze and K.K. Ng, “Physics of Semiconductor Devices”, 3rd ed., Wiley, 2007;
Emerging
R.F. Pierret, “Advanced Semiconductor devicesvolume
Fundamentals“, (I), Electrostatic integrity
VI, 2nd ed., Prentice Hall, 2003.
GAA structure: Si3N4 charge trapping FG
Cell pitch: 2140nm/32 ~ 60nm ~ 52nm
Memory size: 83.5 Gb/84.3 mm2 384 Gb/168.2 mm2
Nano-pillar/wire electron devices
2017: Intel’s 3D Xpoint memory (phase-change)
38 3/10/2023
Nano-pillar/wire electron devices
3/10/2023 39
Electrostatic integrity factor
Threshold voltage roll-off in UTB devices:
Use the (adjusted) EI factor:
2 2
𝑡𝑡s λ
𝐸𝐸𝐸𝐸 = 1 +
𝜂𝜂𝜂𝜂 𝐿𝐿
𝜂𝜂 = 1 (SG) and 2 (DG)
The higher the EI factor, the poorer EI
More gates and UTB result in improved EI, hence ION/IOFF
T. Skotnicki, G. Merckel, and T. Pedron, IEEE Electr. Dev. Lett., 9(11), 1988
Emerging devices (I), Electrostatic integrity
Non-ideal subthreshold current (II)
More accurate, includes SCE:
𝑞𝑞 𝑊𝑊 𝑞𝑞𝑞𝑞
− DS
𝐼𝐼D ≈ − 1 − e 𝑘𝑘𝑘𝑘
𝐺𝐺
with Gummel number
𝐿𝐿G 𝑡𝑡Si −1
2 𝐷𝐷𝑛𝑛 (𝑥𝑥, 𝑦𝑦)
𝐺𝐺 = � � 𝑛𝑛i (𝑥𝑥, 𝑦𝑦) 𝑑𝑑𝑦𝑦 𝑑𝑑𝑑𝑑
0 0 𝑝𝑝(𝑥𝑥, 𝑦𝑦)
and majorities depend exponentially on potential (slide 10, SCE: VDS):
𝜓𝜓(𝑥𝑥,𝑦𝑦)
−
𝑝𝑝(𝑥𝑥, 𝑦𝑦) = 𝑁𝑁𝐴𝐴 (𝑥𝑥, 𝑦𝑦) � 𝑒𝑒 𝑢𝑢𝑇𝑇
H.C. Pao and C.T. Sah, SSE, 9(10), 1966; R.J.E. Hueting and A. Heringa, IEEE TED, 53(7), 2006;
Q. Xie, X. Yu, and Y. Taur, IEEE TED, 59(6), 2012
Emerging devices (I), Electrostatic integrity
Non-ideal subthreshold current (I)
More accurate, includes SCE:
𝑞𝑞 𝑊𝑊 𝑞𝑞𝑞𝑞
− DS
𝐼𝐼D ≈ − 1 − e 𝑘𝑘𝑘𝑘
𝐺𝐺
with Gummel number
𝐿𝐿G 𝑡𝑡Si −1
2 𝐷𝐷𝑛𝑛 (𝑥𝑥, 𝑦𝑦)
𝐺𝐺 = � � 𝑛𝑛i (𝑥𝑥, 𝑦𝑦) 𝑑𝑑𝑦𝑦 𝑑𝑑𝑑𝑑
0 0 𝑝𝑝(𝑥𝑥, 𝑦𝑦)
and majorities depend exponentially on potential:
𝜓𝜓(𝑥𝑥,𝑦𝑦)
−
𝑝𝑝(𝑥𝑥, 𝑦𝑦) = 𝑛𝑛i (𝑥𝑥, 𝑦𝑦) � 𝑒𝑒 𝑢𝑢𝑇𝑇
Volume inversion (DG): 𝜓𝜓 𝑥𝑥, 𝑦𝑦 ≈ 𝜓𝜓s (𝑥𝑥)
Note: for FinFETs 𝑊𝑊 = 2 � 𝐻𝐻fin
X. Liang and Y. Taur, IEEE TED, 51(8), 2004; R.J.E. Hueting and A. Heringa, IEEE TED, 53(7), 2006;
Q. Xie, X. Yu, and Y. Taur, IEEE TED, 59(6), 2012
Emerging devices (I), Electrostatic integrity
