EE3011 MULTILEVEL POWER

CONVERTERS

Dr.P.PALANIVEL
Prof & Head
Dept. of EEE
Roever Engineering College

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 EE3011 MULTILEVEL POWER CONVERTERS LTPC
2 0 2 3
COURSE OBJECTIVES:
 To learn multilevel topology (Symmetry & Asymmetry) with common DC bus link.
 To study the working of cascaded H Bridge, Diode Clamped and Flying Capacitor MLI.
 To study the working of MLI with reduced switch count.
 To simulate three level diode clamped MLI and three level flying capacitor based MLI with resistive
and reactive load
 To simulate the MLI with reduced switch count.

UNIT I MULTILEVEL TOPOLOGIES 6

Introduction – Generalized Topology with a Common DC bus – Converters derived from the generalized
topology – symmetric topology without a common DC link – Asymmetric topology.

UNIT II CASCADED H-BRIDGE MULTILEVEL INVERTERS 6

Introduction -H-Bridge Inverter, Bipolar Pulse Width Modulation, Unipolar Pulse Width Modulation.
Multilevel Inverter Topologies, CHB Inverter with Equal DC Voltage, H-Bridges with Unequal DC
Voltages – PWM, Carrier-Based PWM Schemes, Phase-Shifted Multicarrier Modulation, Level- Shifted
Multicarrier Modulation, Comparison Between Phase- and Level-Shifted PWM Schemes- Staircase
Modulation.

UNIT III DIODE CLAMPED MULTILEVEL CONVERTER 6

Introduction – Converter structure and Functional Description – Modulation of Multilevel converters –
Voltage balance Control – Effectiveness Boundary of voltage balancing in DCMC converters – Performance
results.

UNIT IV FLYING CAPACITOR MULTILEVEL CONVERTER 6

Introduction – Flying Capacitor topology – Modulation scheme for the FCMC – Dynamic voltage balance of
FCMC.

UNIT V MULTILEVEL CONVERTER WITH REDUCED SWITCH COUNT 6

Multilevel inverter with reduced switch count-structures, working principles and pulse generation methods.
30 PERIODS
LAB COMPONENT: 30 PERIODS
1. Simulation of Fixed PWM, Sinusoidal PWM for an inverter,
2. Simulation of H bridge inverter with R load .
3. Simulation of three level diode clamped MLI with R load.
4. Simulation of three level capacitor clamped MLI with R load
5. Simulation of MLI with reduced switch configuration.
TOTAL: 30+30 = 60 PERIODS
COURSE OUTCOMES:
At the end of the course, students should be able to:
CO1: Examine the different topologies of multilevel inverters (MLIs) with and without DC link capacitor.

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CO2: Examine the performance of MLIs with Bipolar Pulse Width Modulation (PWM) Unipolar PWM
Carrier-Based PWM Schemes Phase Level Shifted Multicarrier Modulation
CO3: Demonstrate the working principles of Cascaded H-Bridge MLI, diode clamped MLI, flying capacitor
MLI and MLI with reduced switch count
CO4: Analyze the voltage balancing performance in Diode clamped MLI.
CO5: Simulate three level, capacitor clamed and diode clamped MLI with R and RL load.
CO6: Simulate MLI with reduced switch configuration using fundamental switching scheme

TEXT BOOKS:
1. Rashid M.H,”Power Electronics Circuits, Devices and Applications”, Prentice Hall India, Third Edition,
New Delhi, 2014 Pearson 4th edition.
2. Sergio Alberto Gonzalez, Santiago Andres Verne, Maria Ines Valla,”Multilevel Converters for Industrial
Applications”, CRC Press, 22-Jul-2013, 20171st Edition.
3. BinWu, Mehdi Narimani,High Power Converters and AC drives by IEEE press 2017, 2nd Edition.

REFERENCEBOOKS:
1. Thomas A. Lipo, Pulse Width Modulation for Power Converters: Principles and Practice, D.Grahame
Holmes, John Wiley & Sons, Oct-2003, 1st Edition.
2. Fang Lin Luo, Hong Ye,Advanced DC/AC Inverters: Applications in Renewable Energy, CRC Press, 22-
Jan-2013, 2017, 1st Edition.
3. Hani Vahedi, Mohamed Trabelsi, Single-DC-Source Multilevel Inverters, Springer, 2019, 1st Edition.
4. Ersan Kabalcı, Multilevel Inverters Introduction and Emergent Topologies, Academic Press Inc,2021, 1st
Edition.
5. Iftekhar Maswood, Dehghani Tafti, Advanced Multilevel Converters and Applications in Grid Integration,
Wiley, 2018, 1st Edition.

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UNIT I MULTILEVEL TOPOLOGIES 6
Introduction – Generalized Topology with a Common DC bus – Converters derived from the generalized
topology – symmetric topology without a common DC link – Asymmetric topology.

1.1 INTRODUCTION
Power electronics is a discipline increasingly involved in all processing stages of electric power, like
generation, conversion, transmission distribution, and conditioning.
But the power converters are restricted in their operational capacities by the switching devices, whose
limitations are imposed by the physical characteristics of the semiconductor materials.
In this sense, large amounts of research are taking place around the development of new semiconductor
switching devices with larger voltage withstanding capabilities.
However, the aim of increasing the working voltage of the converters with the existing power switches also
finds its own way with the introduction of multilevel converters.

1.2 MULTILEVEL INVERTER

In recent years, the need for high power apparatus has been derived by numerous industrial applications.
Multilevel converters present great advantages compared with typical and very well known two-level
converters. These advantages are fundamentally focused on improvements in the output signals quality and a
nominal power increase in the converter.
These properties make multilevel converters very attractive to the industry and nowadays, researchers all
over the world are spending great efforts trying to improve multilevel converters performance as the control
simplification and the performance of different optimisation algorithms in order to enhance the Total
Harmonic Distortion (THD) of the output signals.

Q1: What is meant by multilevel inverter?

The elementary concept of a multilevel converter is to achieve higher power by using a series of power
semiconductor switches with several lower voltage sources. The power conversion is performed by
synthesizing a staircase voltage waveform.

A three level inverter produces output voltage level of 0, +Vdc and -Vdc. This three level inverter posses
more limitations in operating at high frequency mainly due to switching losses and constraints of device
rating.

Q2: What are the advantages, features, disadvantages and applications of Multilevel Inverters?
The advantages Multilevel inverters is to produce high power, high voltage and controlling voltage stresses.

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The attractive features of a multilevel converter can be briefly summarized as follows.
Staircase waveform quality: Multilevel converters not only can generate the output voltages with very low
distortion, but also can reduce the dv/dt stresses; therefore electromagnetic compatibility (EMC) problems
can be reduced.
Common-mode (CM) voltage: Multilevel converters produce smaller CM voltage; therefore, the stress
in the bearings of a motor connected to a multilevel motor drive can be reduced. Furthermore, CM voltage
can be eliminated by using advanced modulation.
Input current: Multilevel converters can draw input current with low distortion.
Switching frequency: Multilevel converters can operate at both fundamental switching frequency and high
switching frequency PWM. It should be noted that lower switching frequency usually means lower
switching loss and higher efficiency.

Disadvantages
 One particular disadvantage is the greater number of power semiconductor switches needed.
 Although lower voltage rated switches can be utilized in a multilevel converter, each switch requires
a related gate drive circuit. This may cause the overall system to be more expensive and complex.

Applications
 Power Quality Improvement
 Renewable Energy Interconnection
 Variable Speed Drives

The term multilevel began with the three-level converter. Subsequently, several multilevel topologies have
been developed.
History of multilevel inverters began in 1975 by Baker and Bannister.

This first patent describes a converter topology capable of producing multilevel voltage by connecting single
phase inverter in series. The topology called series connected H-Bridge inverter also known as cascaded H-
bridge inverter.

Q3: What are the classifications of multilevel inverters?

The multilevel inverters can be classified in to three types
1.Diode clamped MLI
2. Flying capacitors MLI
3.Cascaded MLI

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(a) Two‐level converter with series‐connected switches. b) Neutral point clamp converter (three‐level).

(c) Flying capacitor converter (three-level) (d) Five-level cascaded converter

Q4: Explain about the Generalized Topology with a Common DC Bus.

 It is named the generalized topology introduced by Peng in 2001.

 It has a cellular structure in which the number of voltage levels is increased by adding basic cells.
 The basic cell is the functional unit of the generalized topology, and it is built with two
complementary power switches and one capacitor.
 An n-level converter has n – 1 stages. Each stage is formed by a stack of basic cells.
 This cellular structure allows us to increase the number of voltage levels by implementing a
symmetrical growth, in both vertical and horizontal directions.

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 One leg of a symmetric n-level Voltage source multilevel converters (VSMC) with a common DC bus

Q5: Explain about the Basic Cell (a) topology and (b) graphic representation of cell states

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Q6: Explain about the Generalized Topology Characteristics.

Every basic cell should have the same voltage (VC) in order to synthesize a symmetric output voltage.
The voltage level VC is fixed by the capacitor voltage divider of the first stage.
Assuming that all the capacitors have the same capacitance, then VC is

A constant and equal voltage source for each cell VC in every stage is guaranteed when all the cells in one
stage use the same switching function.
Parallel connection of basic cells

Figure shows the mechanism to equalize the

voltages in each cell of every stage.
The figure represents a portion of the first
three stages of an n-level leg.
The power switches that are OFF are
indicated in gray, while those that are ON are
drawn in black.
The voltage VC is maintained in all the cells
of the generalized topology.
It is important to remark that the voltage on
every capacitor is preserved when all the cells
in the same stage commutate simultaneously
with the same switching function.
All the cells in each stage are controlled with the same switching function, and it defines two possible states.
Then, an n-level topology with (n – 1) stages has possible states.

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Three-Level Generalized Topology

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Q7: Explain about the Converters Derived from the Generalized Topology.
The generalized topology allows increasing the number of voltage levels by simply adding new basic cells.
For example, to increase the voltage levels from n to n + 1 it is necessary to add a new stage with n cells.
It is an easy way to increase the voltage levels, but it requires a lot of devices.
Then, the implementation complexity of the topology also increases.
Moreover, the number of possible states increases more than the voltage levels, also increasing the number
of redundant states.
So, the generalized topology is useful to understand the operation of multilevel topologies, but its practical
implementation is not convenient when the number of levels increases.

Converter states of a three-level generalized topology: state 00, (b) state 01 (c) state 11, and (d) state 10

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Q8: Explain about the Symmetric Topologies and Asymmetric Topologies.

Symmetric Topologies without a Common DC Link

Figure shows one leg of an n-level multilevel topology

with independent and isolated power sources.

This topology does not have a common DC link for all the
legs of the topology.
Each stage has two basic cells connected in parallel and
sharing a common DC source or capacitor.
The different stages are connected in series to obtain an n-
level voltage at the output.
This topology is known as n-level cascaded cell multilevel
converter (CCMC).
The voltage of each stage is calculated as the voltage difference of each basic cell.
Then, each stage is controlled with two independent switching functions and the stage voltage.

Asymmetric Topologies

The hybrid multilevel converter (HMC) is a topology

with a cascade of different stages connected in series but
with different values of DC voltages, as shown in Figure.
Each stage may be built with a different topology, which
in turn generates a different number of voltage levels (n1,
n2, …, nP).
This fact, together with the different values of the DC
sources, generates asymmetric topologies in which there
are no equal stages. The term hybrid is related to the
modulation of each stage.
The asymmetry of the DC voltage sources also
determines the power handled by each stage.
The stages with higher DC voltage manage higher power
than those with a lower DC voltage.
Then it is possible to implement the power switches of the
different stages with different devices.

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Q9: Explain the five level Diode clamped Multilevel inverter.
The Diode clamped Multilevel inverter invented by A.Nabae and I.Takahashi, 1981.
The main concept of Diode clamped Multilevel inverter is to use diodes to limit the power devices voltage
stress.
M-level inverter typically consists of
 Main switching Devices – (m-1)x 2 = (5-1)X2 = 8 devices.
 Main Diodes - (m-1)x 2 = (5-1)X2 = 8 diodes.
 Clamping Diodes- (m-1) x (m-2) = (5-1)X(5-2) = 12 diodes.
 Dc bus capacitors – (m-1) = (5-1) = 4 capacitors.

To produce a staircase output voltage, let us consider only

one leg of the five level inverter, as shown in figure.
The steps to synthesize the five level voltages are as
follows:
 For an output voltage level V0 = Vdc, turn on all
upper half switches S1 through S4.
 For an output voltage level V0 = Vdc/2, turn on
three upper switches S2 through S4 and one lower switch
S5.
 For an output voltage level V0 = 0, turn on two
upper switches S3 & S4 and two lower switch S5 & S6.
 For an output voltage level V0 = -Vdc/2, turn on
one upper switch S4 and three lower switches S5 through
S7.
 For an output voltage level V0 = -Vdc, turn on all
lower half switches S5 through S8.

Advantages:
 Inverter efficiency is high because all devices are switched at the fundamental frequency.
 The control method is simple.

Disadvantages:
 Excessive clamped diodes are required when the number of levels is high.
 It is difficult to control the real power flow of the individual converter in multilevel inverter systems.

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Q10: Explain the five level Flying capacitor Multilevel inverter.
The Flying capacitor Multilevel inverter invented by Meynard and Foch ,1992.
This inverter uses capacitors to limit the voltage of the power devices.
M-level inverter typically consists of
 Main switching Devices – (m-1)x2 = (5-1)X2 = 8 devices.
 Main Diodes - (m-1)x2 = 8 diodes.
 Dc bus capacitors – (m-1) = (5-1) = 4 capacitors.
 Balancing Capacitor – ( m-1)x(m-2)/2 = (5-1)X(5-2)/2 = 6 capacitors.

To produce a staircase output voltage, let us

consider only one leg of the five level inverter, as shown
in Figure.
The steps to synthesize the five level voltages are
as follows:
 For an output voltage level V0 = Vdc,
turn on all upper half switches S1 through S4.
 For an output voltage level V0 = Vdc/2,
turn on three upper switches S1 through S3 and one
lower switch S5.
 For an output voltage level V0 = 0, turn
on two upper switches S1 & S2 and two lower switch S5
& S6.
 For an output voltage level V0 = -Vdc/2,
turn on one upper switch S1 and three lower switches S5
through S7.
 For an output voltage level V0 = -Vdc, turn on all lower half switches S5 through S8.

Advantages:
 Large amount of storage capacitors can provide capabilities during power outages.
 Both real and reactive power flow can be controlled.

Disadvantages:
 Excessive number of storage capacitors are required when the number of levels are high.
 The inverter control is very complicated, and the switching frequency and switching losses are high
for real power transmission.

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Q11: Explain the five level Cascaded multilevel inverter.

The Cascaded Multilevel inverter invented by K.Corzine and Y.Familiant, 2002.

A cascaded multilevel inverter consists of a series of H-bridge (single phase, full bridge) inverter units.
The general function of this multilevel inverter is to synthesize a desired voltage from several separate
DC sources.
 M-level inverter typically consists of
 Main switching Devices – (m-1)x2 = (5-1)X2 = 8 devices.
 Main Diodes - (m-1)x2 = (m-1)x2 = 8 diodes.
 Dc bus capacitors – (m-1)/2 = (5-1)/2 = 2 capacitors.

A single-phase structure of a five level cascaded

inverter is illustrated in Figure.
Each separate DC source is connected to an H-bridge
inverter.
 Each inverter level can generate three different
voltage outputs +Vdc, 0, and –Vdc by connecting the dc source
to the ac output by different combinations of the four switches,
S1, S2, S3, and S4.
 To obtain +Vdc, switches S1, S2, S5 and S6 are
turned on, whereas –Vdc can be obtained by turning on
switches S3, S4, S7 and S8.
 By turning on S1 and S3 or S2 and S4, ‘0’
output voltage can be obtained.

Advantages:
 The number of possible output voltage levels are more than twice the number of dc sources
(m = 2s + 1).
 The series of H-bridges make for modularized layout and packaging. This will enable the
manufacturing process to be done more quickly and cheaply.
 Compared with the diode clamped and flying capacitor inverters, it requires the least number of
components to achieve the same number of voltage levels.

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Q12: Compare the design formula of types of multilevel inverter.

Review Questions

Short answer:

1. What is meant by multilevel inverter?

2. What are the advantages, features, disadvantages and applications of Multilevel Inverters?
3. What are the classifications of multilevel inverters?
4. What are the difference between Symmetric Topologies and Asymmetric Topologies?
5. What is the Diode clamped multilevel inverter? And what are the advantages, disadvantages of
Diode clamped multilevel inverter?
6. What is the flying capacitor multilevel inverter? And what are the advantages, disadvantages of
flying capacitor multilevel inverter?
7. What is the function of cascaded multilevel inverter? And what are the advantages, disadvantages of
cascaded multilevel inverter?

Long answers:

8. Explain the Generalized Topology with a Common DC Bus.

9. Write the short notes on the Basic Cell.
10. Explain about the Generalized Topology Characteristics.
11. Describe the Converters Derived from the Generalized Topology.
12. Explain about the Symmetric Topologies and Asymmetric Topologies.
13. Explain the Diode clamped Multilevel inverter.
14. Explain the Flying capacitor Multilevel inverter.
15. Explain the Cascaded multilevel inverter.
16. Compare the design formula of types of multilevel inverter.

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UNIT II CASCADED H-BRIDGE MULTILEVEL INVERTERS 6

Introduction -H-Bridge Inverter, Bipolar Pulse Width Modulation, Unipolar Pulse Width Modulation.
Multilevel Inverter Topologies, CHB Inverter with Equal DC Voltage, H-Bridges with Unequal DC
Voltages – PWM, Carrier-Based PWM Schemes, Phase-Shifted Multicarrier Modulation, Level- Shifted
Multicarrier Modulation, Comparison Between Phase- and Level-Shifted PWM Schemes- Staircase
Modulation.

Introduction
The inverter gain may be defined as the ratio of the ac output voltage to dc input voltage.
The output voltage waveforms of ideal inverters should be sinusoidal. However, the waveforms of practical
inverters are nonsinusoidal and contain certain harmonics. For low- and medium-power applications, square-
wave or quasi-square-wave voltages may be acceptable; for high-power applications, low distorted
sinusoidal waveforms are required. These inverters generally use PWM control signals for producing an ac
output voltage.

Q1: What is meant by Inverter? And what are types & applications of inverters?
 It converts fixed dc voltage to variable ac voltage is known as inverter.
 Inverters can be broadly classified into two types: (1) single-phase inverters (2) three-phase inverters.
 Inverters are widely used in industrial applications: variable-speed ac motor drives, renewable
energy, transportation, induction heating, standby power supplies and uninterruptible power supplies.

Q2: Explain about the single phase H-Bridge Inverter.

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Voltage Control of Inverters
In many industrial applications, the control of the output voltage of inverters is often necessary
(1) to cope with the variations of dc input voltage,
(2) to regulate voltage of inverters, and
(3) to satisfy the constant volts and frequency control requirement.

Q3: What are the PWM techniques using inverters?

The commonly used following PWM techniques are:
1. Single-pulse-width modulation
2. Multiple-pulse-width modulation
3. Sinusoidal pulse-width modulation

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Q4: What is meant by Sinusoidal Pulse-Width Modulation and types?
The gating signals as generated by comparing a sinusoidal reference signal with a triangular carrier wave of
frequency is known as Sinusoidal Pulse-Width Modulation.
This sinusoidal pulse-width modulation (SPWM) is commonly used in industrial applications.
There are two types
A) Bipolar PWM
B) Unipolar PWM

Q5: Explain the bipolar pulse width modulation.

The gating signals as generated by comparing a sinusoidal reference signal of both positive &
negative half cycles with a triangular carrier wave of frequency is bipolar sinusoidal pulse-width
modulation.

Q6: Explain the unipolar pulse width modulation.

The gating signals as generated by comparing a sinusoidal reference signal of either positive or negative half
cycles with a triangular carrier wave of frequency is bipolar sinusoidal pulse-width modulation.

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Q7: Explain the five level single phase Cascaded multilevel inverter.

The Cascaded Multilevel inverter invented by K.Corzine and Y.Familiant, 2002.

A cascaded multilevel inverter consists of a series of H-bridge (single phase, full bridge) inverter units.
The general function of this multilevel inverter is to synthesize a desired voltage from several separate DC
sources.
For single phase M-level inverter typically consists of
• Main switching Devices – (m-1)x2 = (5-1)X2 = 8 devices.
• Main Diodes - (m-1)x2 = 8 diodes.
• Dc bus capacitors – (m-1)/2 = (5-1)/2 = 2 capacitors.

A single-phase structure of a five level cascaded inverter is illustrated

in Figure.
Each separate DC source is connected to an H-bridge inverter.
• Each inverter level can generate three different voltage outputs
+Vdc, 0, and –Vdc by connecting the dc source to the ac output by
different combinations of the four switches, S1, S2, S3, and S4.
• To obtain +Vdc, switches S1, S2, S5 and S6 are turned on,
whereas –Vdc can be obtained by turning on switches S3, S4, S7 and S8.
• By turning on S1 and S3 or S2 and S4, ‘0’ output voltage can be obtained.

The main features are as follows:

• For real power conversions from ac to dc and then dc to ac, the cascaded inverters need separate dc
sources. The structure of separate dc sources is well suited for various renewable energy sources such as fuel
cell, photovoltaic, and biomass.
• Connecting dc sources between two converters in a back-to-back fashion is not possible because a short
circuit can be introduced when two back-to-back converters are not switching synchronously.

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The major advantages of the cascaded inverter can be summarized as follows:
• Compared with the diode-clamped and flying-capacitors inverters, it requires the least number of
components to achieve the same number of voltage levels.
• Optimized circuit layout and packaging are possible because each level has the same structure and there
are no extra clamping diodes or voltage-balancing capacitors.
• Soft-switching techniques can be used to reduce switching losses and device stresses.
The major disadvantage of the cascaded inverter is as follows:
• It needs separate dc sources for real power conversions, thereby limiting its applications.

Q8: Explain the five level three phase Cascaded multilevel inverter.
For three phase M-level inverter typically consists of
• Main switching Devices – 3((m-1)x2) = 3((5-1)X2) = 24 devices.
• Main Diodes - 3((m-1)x2) = 24 diodes.
• Dc bus capacitors – 3(m-1)/2 = 3(5-1)/2 = 6 capacitors.

Each separate DC source is connected to an H-bridge inverter.

• Each inverter level can generate three different voltage outputs +Vdc, 0, and –Vdc by connecting the
dc source to the ac output by different combinations of the four switches, S1, S2, S3, and S4.
• To obtain +Vdc, switches S1, S2, S5 and S6 are turned on, whereas –Vdc can be obtained by turning
on switches S3, S4, S7 and S8.
• By turning on S1 and S3 or S2 and S4, ‘0’ output voltage can be obtained.
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Q9: Explain the seven level three phase Cascaded multilevel inverter.
For three phase M-level inverter typically consists of
• Main switching Devices – 3((m-1)x2) = 3((7-1)X2) = 36 devices.
• Main Diodes - 3((m-1)x2) = 36 diodes.
• Dc bus capacitors – 3(m-1)/2 = 3(7-1)/2 = 9 capacitors.

Two phase and line voltages of three-phase seven-level cascaded inverter

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Q10: What are the Classification of PWM multilevel converter modulation strategies?
Two major carrier based techniques used in a conventional inverter that can be applied in a multilevel
inverter. Carrier based strategies are of major interest due to their simplicity and flexibility.
The carrier based PWM techniques are:
a) Level Shifted Multicarrier PWM
b) Phase shifted Multicarrier PWM

Q11:What is meant by Level Shifted Multicarrier PWM and What are the types of level shifted
carrier PWM?
The gating signals are generated by comparing a sinusoidal reference with a ( N is a number of level) N-1
carrier wave sets. The carriers are inphase across all the bands.

The level shifted carrier based PWM techniques are:

Phase Disposition (PD) PWM

Phase Opposition Disposition (POD) PWM
Alternate Phase Opposition Disposition (APOD) PWM
Q12:What is meant by Phase Shifted Multicarrier PWM? And Explain.
In this PWM technique, the gating signals are generated by comparing a sinusoidal reference with a N-1
shifted carrier waves of amplitude.
The carriers between the full bridge inverters are phase shifted by 180º/M.
M is the number of full bridge inverters in a multilevel phase leg.

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Q13:Explain about the types of level shifted carrier PWM of five level MLI?
The level shifted carrier based PWM techniques are:
 Phase Disposition (PD) PWM
 Phase Opposition Disposition (POD) PWM
 Alternate Phase Opposition Disposition (APOD) PWM

Phase Disposition (PD) PWM

 In this PWM technique, the gating signals are generated by comparing a sinusoidal reference of
amplitude with a N-1 carrier wave sets of amplitude.
 Phase disposition where all the carriers are inphase.

Phase Opposition Disposition (POD) PWM

 In this PWM technique, the gating signals are generated by comparing a sinusoidal reference with a
N-1 carrier wave sets.
 For POD modulation, where the carriers above the zero reference are inphase, but shifted by 180º
from those carriers below the zero reference.
 The phase modulation signal is compared with four (n-1 in general) triangle waveforms.

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Alternate Phase Opposition Disposition (APOD) PWM
 In this PWM technique, the gating signals are generated by comparing a sinusoidal reference with a
N-1 carrier wave sets.
 For APOD PWM, where each carrier band is shifted by 180º from the adjacent bands.

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Review Questions:

Short Answer:
1. What is meant by Inverter? And what are types & applications of inverters?
2. What are the PWM techniques using inverters?
3. What is meant by Sinusoidal Pulse-Width Modulation and types?
4. What are the Classification of PWM multilevel converter modulation strategies?
5. What is meant by Level Shifted Multicarrier PWM and What are the types of level shifted carrier
PWM?
6. What is meant by Phase Shifted Multicarrier PWM? And Explain.

Long Answer:
7. Explain about the single phase H-Bridge Inverter.
8. Explain the bipolar pulse width modulation
9. Explain the unipolar pulse width modulation
10. Explain the five level single phase Cascaded multilevel inverter
11. Explain the five level three phase Cascaded multilevel inverter
12. Explain the seven level single phase Cascaded multilevel inverter
13. Explain the seven level three phase Cascaded multilevel inverter
14. Explain about the types of level shifted carrier PWM of five level MLI?
15. Explain about the types of level shifted carrier PWM of seven level MLI?

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UNIT III DIODE CLAMPED MULTILEVEL CONVERTER 6

Introduction – Converter structure and Functional Description – Modulation of Multilevel converters –

Voltage balance Control – Effectiveness Boundary of voltage balancing in DCMC converters – Performance
results.
Q1: What is the concept of diode clamped multilevel inverter?
The main concept of Diode clamped multilevel inverter is to use diodes to limit the power devices voltage
stress.
Q2: Explain the five level Diode clamped multilevel inverter.
The Diode clamped multilevel inverter invented by A.Nabae and I.Takahashi, 1981.
The main concept of Diode clamped multilevel inverter is to use diodes to limit the power devices
voltage stress.
M-level inverter typically consists of
• Main switching Devices – (m-1)x 2 = (5-1)X2 = 8 devices.
• Main Diodes - (m-1)x 2 = (5-1)X2 = 8 diodes.
• Clamping Diodes- (m-1) x (m-2) = (5-1)X(5-2) = 12 diodes.
• Dc bus capacitors – (m-1) = (5-1) = 4 capacitors.

To produce a staircase output voltage, let us consider only one leg of

the five level inverter, as shown in figure.
The steps to synthesize the five level voltages are as follows:
• For an output voltage level V0 = Vdc, turn on all upper half
switches S1 through S4.
• For an output voltage level V0 = Vdc/2, turn on three upper
switches S2 through S4 and one lower switch S5.
• For an output voltage level V0 = 0, turn on two upper switches S3 & S4 and two lower switch S5 &
S6.
• For an output voltage level V0 = -Vdc/2, turn on one upper switch S4 and three lower switches S5
through S7.
• For an output voltage level V0 = -Vdc, turn on all lower half switches S5 through S8.
Advantages:
• Inverter efficiency is high because all devices are switched at the fundamental frequency.
• The control method is simple.
Disadvantages:
• Excessive clamped diodes are required when the number of levels is high.
• It is difficult to control the real power flow of the individual converter in multilevel inverter systems.

26
Q3: What is the importance of clamping diode in DLMC?
 The original switching functions it was possible to eliminate redundant capacitors and also active
power switches to finally come together with a common DC bus topology.
 Moreover, a parts-count improvement could also be made toward a more compact and practical
implementation by considering different blocking voltages for the clamping diodes.
 The high number of forbidden states and the nonexistence of redundant states for leg voltage
synthesis prevent their use to address voltage balance.
 In addition, the dynamical switching behavior of the diode-clamped multilevel converter also
imposes particular constraints in order to ensure safe operation of the power devices.

Q4: Explain the Converter Structure and Functional Description.

 The original switching functions it was possible to eliminate redundant capacitors and also active
power switches to finally come together with a common DC bus topology.
 Moreover, a parts-count improvement could also be made toward a more compact and practical
implementation by considering different blocking voltages for the clamping diodes.
 The high number of forbidden states and the nonexistence of redundant states for leg voltage
synthesis prevent their use to address voltage balance.
 In addition, the dynamical switching behavior of the diode-clamped multilevel converter also
imposes particular constraints in order to ensure safe operation of the power devices.

Voltage Clamping
 Figure1 shows one leg of the five-level converter,
which is composed of the active switching devices with their
integrated freewheeling diodes, the clamping diodes, and the
DC bus with its intermediate nodes.
 The nodes between the active switches are labeled with
the letters A to F in the same figure.
 The capability of the DCMC topology to increase the
output voltage beyond the maximum blocking voltage of the
individual switching devices lies on the voltage-limiting action
that the clamping diodes have on the internal nodes of the leg.

27
 Switching Logic
 In Figure 2, the forbidden and
valid states are respectively denoted as
solid and hollow circles on each corner of
the cubes, and the corresponding leg
voltages are specified.
 As it was mentioned, a great
number of forbidden states are observed
(11 in total), while the allowed states are
reduced to only five, which coincides with
the number of converter levels (this is
general for the DCMC topology).

 Table 1 summarizes the leg output voltages as a

function of the gating signals where it can be seen
that no redundancy exists, provided that each output
voltage level is synthesized by only one gating
pattern.
 The switching logic of Table allows us to synthesize
a functional model of the leg that consists of a
single-pole multiple-throw switch whose inputs are
the intermediate taps of the DC bus, and the cursor defines the leg output voltage.
 Figure 3. It is clear that the load current circulates through the cursor of the switch and is injected or
drained from the capacitor nodes of the DC bus.
 The voltage balance problem can be visualized by considering the flow of the output current into the
DC bus using the switching pattern.
 The switching times
(T1, T2, T3) set up the
duration of the cursor in
each node of the DC bus,
thus defining the shape of
the voltage waveform.

28
Q5: What are the main aspects that should be taken into account for control of a three-phase DCMC
driving three-phase three-wire loads?
1. A modulation strategy is necessary for the determination of the line voltages to be synthesized by the
converter and to be applied to the load.
2. A switching strategy is necessary to control the voltage balance of the DC bus respecting the previously
determined line voltages combinations.
3. The entire control algorithm should have enough flexibility to incorporate the operational switching
constraints.

Q6: What are the classifications of multilevel modulators?

Q7: Explain about the Modulation of Multilevel Converters.

 The modulation of switching converters has the objective of reproducing a continuous reference
signal from a digital pulse train whose average value coincides with the reference.
 The level-shifted carrier modulation was mainly applied to the DCMC converter and consists of the
comparison of the modulating reference signal with a set of (n – 1) triangular carriers
associated with the n
levels of the converter.
 The gating signals
S1, S2, S3, and S4 are the
result of the comparison
between the modulating
signal Sref and the
corresponding carriers,
which are shifted in level
to span the complete range
of Sref, as shown in Figure
1.

29
The level shifted carrier based PWM techniques are:
• Phase Disposition (PD) PWM
• Phase Opposition Disposition (POD) PWM
• Alternate Phase Opposition Disposition (APOD) PWM
Phase Disposition (PD) PWM
• In this PWM technique, the gating signals are generated by comparing a sinusoidal reference of
amplitude with a N-1 carrier wave sets of amplitude.
• Phase disposition where all the carriers are inphase.

Phase Opposition Disposition (POD) PWM

• In this PWM technique, the gating signals are generated by comparing a sinusoidal reference with a
N-1 carrier wave sets.
• For POD modulation, where the carriers above the zero reference are inphase, but shifted by 180º
from those carriers below the zero reference.
• The phase modulation signal is compared with four (n-1 in general) triangle waveforms.

30
Alternate Phase Opposition Disposition (APOD) PWM
• In this PWM technique, the gating signals are generated by comparing a sinusoidal reference with a
N-1 carrier wave sets.
• For APOD PWM, where each carrier band is shifted by 180º from the adjacent bands.

Q8: Explain the Multilevel Space Vector Modulation.

 Space Vector Modulation (SVM) is a digital modulating technique where the objective is to generate
PWM load line voltages that are in average equal to a given (or reference) load line voltage.
 This is done in each sampling period by properly selecting the switch states of the inverter and the
calculation of the appropriate time period for each state.
 The selection of the states and their time periods are accomplished by the space vector (SV)
transformation.

SVM implementation

31
32
Q9: Describe the Voltage Balance Control.

 In order to keep the balance of the DC bus, it is necessary to evaluate how a given switching
combination will modify the capacitor voltages.
 For this, we have to provide a method to calculate the voltage deviations of the DC bus for the
different switching combinations. A method to compute the capacitor voltage deviation is presented
in the next section.
The following hypotheses apply:
 All capacitors have the same value (C1 = C2 = … = Cn–1 = C).
 The load is modelled as a three-wire current source.

Capacitor Voltage Calculation

Figure shows the three-phase DCMC functional model where it can be seen that the position of the single-
pole multiple throw switches determines each leg voltage with respect to the negative of the DC bus.
33
The voltage variation in a given node of the DC bus is calculated by considering the equivalent capacitance
between the node and the negative terminal of the DC bus. When F = 1 the current im flows to node m as
shown in Figure. Also, im flows into an equivalent capacitance Ceq_m given by

When considering that the current is almost constant along the integration interval, the voltage increment
can be simplified to

The voltage deviation ΔVm is divided among all the capacitors of the DC bus, and the polarity of the
individual voltage deviation depends on the relative position of each capacitor with respect to node m, that
is, if it is above or below node m. Then, the capacitor Cj (j = 1, …, n – 1) will suffer a voltage variation
ΔVCj, given by

34
Optimization Flow Diagram

35
Review Questions:

Short Answer:
1. What is the concept of diode clamped multilevel inverter?
2. What is the importance of clamping diode in DLMC?
3. What are the main aspects that should be taken into account for control of a three-phase DCMC
driving three-phase three-wire loads?
4. What are the classifications of multilevel modulators?
5. What is meant by Level Shifted Multicarrier PWM and What are the types of level shifted carrier
PWM?
6. What is meant by Space vector modulation?

Long Answer:
7. Explain the diode clamped multilevel inverter.
8. Explain the Converter Structure and Functional Description.
9. Explain about the Modulation of Multilevel Converters.
10. Explain the Multilevel Space Vector Modulation.
11. Describe the Voltage Balance Control.

36
UNIT IV FLYING CAPACITOR MULTILEVEL CONVERTER
Introduction – Flying Capacitor topology – Modulation scheme for the FCMC – Dynamic voltage balance of
FCMC.

Introduction
 The flying capacitor multilevel converter (FCMC) has been introduced by Meynard and Foch.

Q1: What is flying capacitor multilevel inverter?

 This inverter uses capacitors to limit the voltage of the power devices.
 This topology was conceived to implement high-voltage converters without series connection of the
power switches.

Q2: What are the advantages and disadvantages of FCMC over DCMC?
 It was possible to see that the FCMC has some advantages when compared to the diode-clamped
multilevel converter (DCMC).
 It is easy to increase the number of voltage levels by simply adding basic cells in the load end of
each leg.
 The same as the DCMC, it has a single voltage supply that constitutes the DC bus, allowing the
back-to-back connection of these converters.
 As with the DCMC, the FCMC requires some strategy to maintain the voltage balance on the
different capacitors, but in this case, this is easily overcome using the redundant states in each leg of
the converter with an adequate modulation strategy.
 The main disadvantage of this topology is that it requires a large number of capacitors since it
builds the voltage levels with flying capacitors in each leg of the converter.

Q3: Why output voltage of a FCMC is generated through different connections of the flying
capacitors?
 It is very important that all the FCs reach a constant and stable voltage, so the net charge variation on
each of them should be null.
 There are two important reasons for this.
 The first is to reduce the harmonic distortion on the output voltage.
 The second is to guarantee the same blocking voltage of each power switch equals the same fraction
of the total DC bus voltage.

37
Q4: Explain the five level Flying capacitor Multilevel inverter.
The Flying capacitor Multilevel inverter invented by Meynard and Foch ,1992.
This inverter uses capacitors to limit the voltage of the power devices.
n-level inverter typically consists of
• Main switching Devices – (n-1)x2 = (5-1)X2 = 8 devices.
• Main Diodes - (n-1)x2 = 8 diodes.
• Dc bus capacitors – (n-1) = (5-1) = 4 capacitors.
• Balancing Capacitor – ( n-1)x(n-2)/2 = (5-1)X(5-2)/2 = 6 capacitors.
• The voltage across each capacitor (VC) preserves the same value as in the generalized topology. For
an n-level converter,

To produce a staircase output voltage, let us consider

only one leg of the five level inverter, as shown in
Figure.
The steps to synthesize the five level voltages are as
follows:
• For an output voltage level V0 = Vdc, turn on
all upper half switches S1 through S4.
• For an output voltage level V0 = Vdc/2, turn on
three upper switches S1 through S3 and one lower
switch S5.
• For an output voltage level V0 = 0, turn on two
upper switches S1 & S2 and two lower switch S5 &
S6.
• For an output voltage level V0 = -Vdc/2, turn
on one upper switch S1 and three lower switches S5
through S7.
• For an output voltage level V0 = -Vdc, turn on all lower half switches S5 through S8.

Advantages:
• Large amount of storage capacitors can provide capabilities during power outages.
• Both real and reactive power flow can be controlled.
Disadvantages:
• Excessive number of storage capacitors are required when the number of levels are high.
• The inverter control is very complicated, and the switching frequency and switching losses are high
for real power transmission.
38
Q5: Explain the Modulation Scheme for the FCMC.

 The phase-shifted carrier pulse width modulation (PSPWM) naturally provides the required charge
and voltage balance of all the capacitors of the FCMC.
 This modulation travels along the redundant states of the FCMC providing self-charge balancing
without additional controllers.

Phase-Shifted Carrier Pulse Width Modulation

 The PSPWM of an n-level FCMC requires n – 1 carriers with a phase displacement as shown in
Figure.
 Each carrier is a triangular wave with an amplitude AP and a frequency fS much higher than the
modulating frequency.
 The phase shift among them is equal to

 A single modulating signal is compared

with each carrier generating n – 1 switching
functions.
 The modulation index (m) is defined as
the ratio between the amplitudes of the modulating
signal and the carrier,

 In this PWM technique, the gating signals are generated by comparing a sinusoidal reference with a
N-1 shifted carrier waves of amplitude.

39
Q6: What are the mechanisms through which these harmonics can appear on the flying capacitors?
 There exist two mechanisms through which these harmonics can appear on the flying capacitors.
 The first one deals with the load current as was analyzed.
 In this way, the time of convergence to the steady state depends on the load.
 The other method consists in generating the balancing harmonics with passive networks tuned at the
switching frequency.

Q7: Explain the Dynamic Voltage Balance of the FCMC.

 The dynamic behavior of the voltage in the flying capacitors has been through the harmonics
components.
 It has been demonstrated that the voltage unbalances on the flying capacitors of an n-level FCMC
can be corrected introducing harmonic currents at frequencies equal to k.fS (where k is an integer but
not a multiple of the number of levels n).
 There exist two mechanisms through which these harmonics can appear on the flying capacitors.
 The first one deals with the load current as was analyzed.
 In this way, the time of convergence to the steady state depends on the load.
 The other method consists in generating the balancing harmonics with passive networks tuned at the
switching frequency.
 This network not only allows the dynamic balance of flying capacitors, it can also fix the
convergence time to the steady state, through a proper design of the passive network.

Dynamic Model
It is better to use a time domain model to analyze the dynamic behavior of the currents through the flying
capacitors.

Averaged model of a three-level FCMC

40
The averaged voltage of the leg is
 During start-up, the flying capacitor is initially discharged.
 So it is necessary to introduce a difference in the duty cycles in order to reach the steady-state value.
 In this case the phase-shifted carrier modulation is not capable of generating the charge of the flying
capacitor.

 So it is convenient to find a different way to charge the capacitor so that reaches its steady-state
value independently of the duty cycles of the power switches and the load current.

Review Questions:

Short Answer:
1. What is flying capacitor multilevel inverter?
2. What are the advantages and disadvantages of FCMC over DCMC?
3. Why output voltage of a FCMC is generated through different connections of the flying capacitors?
4. What are the mechanisms through which these harmonics can appear on the flying capacitors?

Long Answer:
5. Explain the five level Flying capacitor Multilevel inverter.
6. Explain the Modulation Scheme for the FCMC.
7. Explain the Dynamic Voltage Balance of the FCMC.

41
UNIT V MULTILEVEL CONVERTER WITH REDUCED SWITCH COUNT 6
Multilevel inverter with reduced switch count-structures, working principles and pulse generation methods.

Introduction
 The MLI Concept was first introduced in the early 1975 followed by different variations .
Conventional MLI topologies are classified into three namely: Flying Capacitor MLI (FC-MLI),
Diode clamped MLI (DC-MLI) and Cascaded H-bridge MLI (CHB-MLI).
 The key features of MLIs are: it produces output waveform with low harmonic distortion, it
operates both fundamental switching frequency and high switching frequency PWM, etc.;
Q1: What is the necessity of multilevel inverter with reduced switch count?
 The disadvantage of requirement of large number of power switching which increases the
complexity and makes the system bulky.
 In order to overcome this MLI topology with reduced switch count has come into focus.
 These are used in various applications such as renewable energy sources, drives, FACTS and
electric vehicles.

Conventional Multilevel Inverter Topologies

 Conventional MLI topologies are extensively used in various industrial and grid connected
renewable energy applications.
 The popularity of these topologies is outstanding to several advantages such as lower harmonic
distortion, lower switching losses, modular structure and ease of control.
Classical MLI topologies are categorized into three types:
a. Diode clamped MLI (DC MLI)
b. Flying Capacitor MLI (FC MLI)
c. Cascaded H-Bridge MLI (CHB MLI)
Q2: What are the various conventional and reduced switch MLI topologies?

Fig
42
Conventional Multilevel Inverter Topologies

Reduced Switch Multilevel Inverter Topologies

 Although above mentioned classical multilevel inverters have numerous applications these
topologies need more number of power components.
 So from last few decades the focus of the research is to reduce the switches, diodes and voltage
sources that can improve the quality as well as reduce the switching losses and overall cost.
 In this regard various new reduced switch topologies have been introduced that are suitable for
various applications such as drives, Renewable energy systems and FACTs. These are used in grid
tied and standalone systems.
Q3: What are the classifications of Reduced Switch Multilevel Inverter Topologies?
 These are classified as Reduced Switch Symmetrical (RSS) MLI, Reduced switch asymmetrical
(RSA) MLI, Reduced switch modified (RSM) MLI.
 The modified type contains all the hybrid and topologies that are not based on Hbridge.

Q4: Explain the Reduced Switch MLI.

 As the name itself indicates it consists of all
DC sources with equal magnitude MLI shown in fig (a). This
topology was designed with reduced cost and installation area
and has used fundamental switching technique. When
compared to conventional MLI there is significant reduction
in switches.


43
 A novel MLI topology shown in fig 4 (b) and 4 (c), This is used for low voltage applications.






 The MLI shown in fig 4 (d) can be operated

both in symmetric and asymmetric modes, this is developed
a new cascaded H-bridge topology with four switches
connected in cascaded form and two DC sources using
vertical phase shifted sinusoidal PWM.



 Another MLI topology shown in fig 4
(e), which contains three dc sources of
equal magnitude with four switches
which uses Multi carrier sub harmonic
PWM. This can be used in high power
and high voltage applications. It is used
as an alternative to conventional
topology for RES applications.

44
  New switched diode MLI shown in fig 4 (f) with
reduced size, cost and removal of high voltage spikes from the
output voltage and has used clock phase shifted one cycle
control.

 The developed MLI based on

switched capacitor in order to
improve the power density and
energy conversion efficiency
and has used basic SPWM
technique shown in fig 4(g).

 The improved sub module based MLI with

reduced number of switches using SHE-PWM. It can be
used in renewable energy applications, especially PV and
fuel cells which is shown in fig 4 (h).

 The developed a reduced a reduced switch MLI which require

less number of active switches and mitigate dominant lower
order harmonics using Modified PSO based SHE technique.
This is used in renewable energy and drive applications. The
topology is shown in Fig 4 (i).

45
Q5: What are the Modulation Techniques of Reduced Switch Multilevel Inverter Topologies?
A. Phase Disposition PWM Strategy
B. Phase Opposition and Disposition PWM Strategy
C. Alternate Phase Opposition Disposition PWM Strategy
D. Carrier Overlapping PWM Strategy
E. Variable Frequency Carrier PWM Strategy
F. Phase Shift PWM Strategy

Q6: Explain the Modulation Techniques of Reduced Switch Multilevel Inverter Topologies.

A. Phase Disposition PWM Strategy: In this method, all the carrier signals above and below zero reference
are in same phase.

B. Phase Opposition and Disposition PWM Strategy: In this method, all the carriers have same amplitude
and frequency. All the carriers above zero reference are in same phase and all the carriers below zero
reference are in same phase but 180 degrees’ phase shifted with respect the above carriers

46
C. Alternate Phase Opposition Disposition PWM Strategy: In this method, all the carriers have same
amplitude and frequency. All the alternate carriers are in same phase and the others are phase shifted by 180
degrees.

D. Carrier Overlapping PWM Strategy: In this method, the carriers are overlapped with each other

E. Variable Frequency Carrier PWM Strategy: In this method, the frequency of the carriers is not same.
Some carriers have same frequency others have different frequency.

47
F. Phase Shift PWM Strategy:In this phase shift multicarrier PWM strategy four carrier signals are phase
shifted by 90 degrees, which has same frequency and amplitude to generate a five level output.

Review Questions

1. What is the necessity of multilevel inverter with reduced switch count?

2. What are the various conventional and reduced switch MLI topologies?
3. What are the classifications of Reduced Switch Multilevel Inverter Topologies?
4. Explain the Reduced Switch MLI.
5. What are the Modulation Techniques of Reduced Switch Multilevel Inverter Topologies?
6. Explain the Modulation Techniques of Reduced Switch Multilevel Inverter Topologies.

48