Topics Barrel Shifter: N N N N N

Topics
Shifters. n Adders and ALUs.

n n
Barrel shifter
Can perform n-bit shifts in a single cycle. n Efficient layout. n Does require transmission gates and long wires.
Modern VLSI Design 3e: Chapter 6
Copyright 1998, 2002 Prentice Hall PTR
Combinational shifters
Useful for arithmetic operations, bit field extraction, etc. n Latch-based shift register can shift only one bit per clock cycle. n A multiple-shift shifter requires additional connectivity.
n
Barrel shifter structure

Accepts 2n data inputs and n control signals, producing n data outputs.
n bits
data 1
output
n bits
n bits
data 2
Barrel shifter operation

n
Barrel shifter cell
Selects arbitrary contiguous n bits out of 2n input buts. n Examples:

right shift: data into top, 0 into bottom; left shift: 0 into top, data into bottom; rotate: data into top and bottom.
Barrel shifter layout

n
Barrel shifter in action
Two-dimensional array of 2n vertical X n horizontal cells. n Input data travels diagonally upward. Output wires travel horizontally. n Control signals run vertically. Exactly one control signal is set to 1, turning on all transmission gates in that column.
Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 6 Copyright 1998, 2002 Prentice Hall PTR
Analysis
Large number of cells, but each one is small. n Delay is large, considering long wires and transmission gates.
n n
Full adder
Computes one-bit sum, carry:
si = ai XOR bi XOR ci ci+1 = aibi + aici + bici
Ripple-carry adder: n-bit adder built from full adders. n Delay of ripple-carry adder goes through all carry bits.
n
Modern VLSI Design 3e: Chapter 6 Copyright 1998, 2002 Prentice Hall PTR
Adders
Adder delay is dominated by carry chain. n Carry chain analysis must consider transistor, wiring delay. n Modern VLSI favors adder designs which have compact carry chains.
n n
Carry-lookahead adder
First compute carry propagate, generate:
Pi = ai + bi Gi = ai bi
n
Compute sum and carry from P and G:

si = ci XOR Pi XOR Gi ci+1 = Gi + Pici
Carry-lookahead expansion
n
Analysis
Deepest carry expansion requires gates with large fanin: large, slow. n Carry-lookahead unit requires complex wiring between adders and lookahead unit values must be routed back from lookahead unit to adder. n Layout is even more complex with multiple levels of lookahead.
n
Can recursively expand carry formula:

ci+1 = Gi + Pi(Gi-1 + Pi-1ci-1) ci+1 = Gi + PiGi-1 + PiPi-1 (Gi-2 + Pi-1ci-2)
Expanded formula does not depend on intermerdiate carries. n Allows carry for each bit to be computed independently.
n
Depth-4 carry-lookahead
n
Carry-skip adder
Looks for cases in which carry out of a set of bits is identical to carry in. n Typically organized into m-bit stages. n If ai = bi for every bit in stage, then bypass gate sends stages carry input directly to carry output.
Two-bit carry-skip structure
Carry-select structure
Carry-select adder
Computes two results in parallel, each for different carry input assumptions. n Uses actual carry in to select correct result. n Reduces delay to multiplexer.
n n
Manchester carry chain

Precharged carry chain which uses P and G signals. n Propagate signal connects adjacent carry bits. n Generate signal discharges carry bit. n Worst-case discharge path goes through entire carry chain.
Manchester carry chain circuit
Serial adder structure

LSB control signal clears the carry shift register:
Serial adder
May be used in signal-processing arithmetic where fast computation is important but latency is unimportant. n Data format (LSB first):
n 0 1 1 0 n
ALUs
ALU computes a variety of logical and arithmetic functions based on opcode. n May offer complete set of functions of two variables or a subset. n ALU built around adder, since carry chain determines delay.
LSB
Modern VLSI Design 3e: Chapter 6 Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 6 Copyright 1998, 2002 Prentice Hall PTR
Function block circuit
ALU structure
Function blocks and ALUs

Function block may be used to compute required intermediate signals for a fullfunction ALU. n Requires little area. n Transmission gates may introduce significant delay.
n n
ALU design
P and G compute intermediate values from inputs. May not correspond to carry lookahead P and G for non-addition functions. n Add unit is adder of choice. n Output unit computes from sum, propagate signal.
Topics
n
Word serial multiplier
Multipliers.
Elementary school algorithm

0110 x1001 0110 +0000 00110 +0000 000110 +0110 0110110
Combinational multiplier
Uses n adders, eliminates registers:
multiplicand multiplier
partial product
Array multiplier
Array multiplier is an efficient layout of a combinational multiplier. n Array multipliers may be pipelined to decrease clock period at the expense of latency.
n
xny0
Unsigned array multiplier

x2y0
0
x1y0
0
x0y0 x0y1
+ +
x1y2
x1y1 x0y2
+
P(2n-1)
+
P(2n-2)
0 P0
Array multiplier organization

0110 x1001 multiplicand 0110 +0000 multiplier 00110 +0000 000110 +0110 0110110 product
Baugh-Wooley multiplier
Algorithm for twos-complement multiplication. n Adjusts partial products to maximize regularity of multiplication array. n Moves partial products with negative signs to the last steps; also adds negation of partial products rather than subtracts.
n
skew array for rectangular layout
Booth multiplier
Encoding scheme to reduce number of stages in multiplication. n Performs two bits of multiplication at once requires half the stages. n Each stage is slightly more complex than simple multiplier, but adder/subtracter is almost as small/fast as adder.
n
Booth actions
yi yi-1 yi-2 000 001 010 011 100 101 110 111
increment 0 x x 2x -2x -x -x 0
Booth encoding
n n
Booth example
x = 011001 (2510), y = 101110 (-1810). n y1y0y-1 = 100, P1 = P0 - (10 011001) = 11111001110. n y3y2y1= 111, P2 = P1+ 0 = 11111001110. n y5y4y3= 101, P3 = P2 - 0110010000 = 11000111110.
n
Twos-complement form of multiplier:

y = -2nyn + 2n-1yn-2 + 2n-2yn-2 + ...
Rewrite using 2a = 2a+1 - 2a:

y = -2n(yn-1-yn) + 2n-1(yn-2 -yn-1) + 2n-2(yn-3 -yn-2) + ...
Consider first two terms: by looking at three bits of y, we can determine whether to add x, 2x to partial product.
Booth structure
Wallace tree structure
Wallace tree
Reduces depth of adder chain. n Built from carry-save adders:
n n
Wallace tree operation

At each stage, i numbers are combined to form ceil(2i/3) sums. n Final adder completes the summation. n Wiring is more complex. n Can build a Booth-encoded Wallace tree multiplier.
three inputs a, b, c produces two outputs y, z such that y + z = a + b+c

n
Carry-save equations:
yi = parity(ai,bi,ci) zi = majority(ai,bi,ci)
Serial-parallel multiplier
Used in serial-arithmetic operations. n Multiplicand can be held in place by register. n Multiplier is shfited into array.
n n
Topics
Memories:
ROM; SRAM; DRAM.
Datapaths. n PLAs.
n
Serial-parallel multiplier structure
High-density memory architecture
Memory operation
n
ROM core circuit
Address is divided into row, column.

Row may contain full word or more than one word.
Selected row drives/senses bit lines in columns. n Amplifiers/drivers read/write bit lines.
Read-only memory (ROM)

n
Static RAM (SRAM)

Core cell uses six-transistor circuit to store value. n Value is stored symmetrically both true and complement are stored on crosscoupled transistors. n SRAM retains value as long as power is applied to circuit.
n
ROM core is organized as NOR gates pulldown transistors of NOR determine programming. n Erasable ROMs require special processing that is not typically available. n ROMs on digital ICs are generally maskprogrammed placement of pulldowns determines ROM contents.
SRAM core cell
SRAM sense amp
SRAM core operation

n
Sense amp operation

n
Read:
precharge bit and bithigh; set select line high from row decoder; one bit line will be pulled down.
Write:
set bit/bitto desired (complementary) values; set select line high; drive on bit lines will flip state if necessary.
Differential pair takes advantage of complementarity of bit lines. n When one bit line goes low, that arm of diff pair reduces its current, causing compensating increase in current in other arm. n Sense amp can be cross-coupled to increase speed.
3-transistor dynamic RAM (DRAM)

First form of DRAM modern commercial DRAMs use one-transistor cell. n 3-transistor cell can easily be made with a digital process. n Dynamic RAM loses value due to charge leakage must be refreshed.
n n
3-T DRAM operation

Value is stored on gate capacitance of t1. n Read:
read = 1, write = 0, read_datais precharged; t1 will pull down read_dataif 1 is stored.
n
Write:
read = 0, write = 1, write_data = value; guard transistor writes value onto gate capacitance.
3-T DRAM core cell

n
Data paths
A data path is a logical and a physical structure:
bitwise logical organization; bitwise physical design.
Datapath often has ALU, registers, some other function units. n Data is generally passed via busses.
n
Modern VLSI Design 3e: Chapter 6 Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 6 Copyright 1998, 2002 Prentice Hall PTR
Typical data path structure

Slice includes one bit of function units, connected by busses:
n
Abutting and pitch-matching

Cells in bit-slice may be abutted together requires matching positions on terminals. n Pitch-matching is designing cells to ensure that pins are at proper positions for abutting.
registers
shift
ALU
bus
Bit-slice structure
Many arithmetic and logical functions can be defined recursively on bits of word. n A bit-slice is a one-bit (or n-bit) segment of an operation of minimum size to ensure regularity. n Regular logical structure allows regular physical structure.
n
Wiring plans
A wiring plan shows layer assignments and directions for major signals. n Put most important signals on lowestimpedance, accessible layers.
n
VDD
cell1
cell2
cell3
VSS
Bus circuits
Cannot support full connectivity between all data path elements must choose number of transfers per cycle allowed. n A bus circuit is a specialized multiplexer circuit. n Two major choices: pseudo-nMOS, precharged.
n
Modern VLSI Design 3e: Chapter 6 Copyright 1998, 2002 Prentice Hall PTR Modern VLSI Design 3e: Chapter 6
Precharged bus circuit
Pseudo-nMOS bus circuit
Programmable logic array (PLA)

Used to implement specialized logic functions. n A PLA decodes only some addresses (input values); a ROM decodes all addresses. n PLA not as common in CMOS as in nMOS, but is used for some logic functions.
n
PLA organization
p1 p2 AND plane p3 p4 OR plane output 2 output 1
PLA AND/OR cell

input 1 input 2 programming tab
no tab VSS
i0 i0
i1 i1
product term
f0
f1
PLA structure
AND plane, OR plane, inverters together form complete two-level logic functions. n Both AND and OR planes are implemented as NOR circuits. n Pulldown transistors form programming/personality of PLA. Transistors may be referred to as programming tabs.
n

Topics Barrel Shifter: N N N N N

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Topics

Shifters. n Adders and ALUs.

Modern VLSI Design 3e: Chapter 6

Copyright 1998, 2002 Prentice Hall PTR

Modern VLSI Design 3e: Chapter 6

Copyright 1998, 2002 Prentice Hall PTR

Barrel shifter structure

Modern VLSI Design 3e: Chapter 6

Copyright 1998, 2002 Prentice Hall PTR

Modern VLSI Design 3e: Chapter 6

Copyright 1998, 2002 Prentice Hall PTR

Barrel shifter operation

Barrel shifter cell

Selects arbitrary contiguous n bits out of 2n input buts. n Examples:

Modern VLSI Design 3e: Chapter 6

Copyright 1998, 2002 Prentice Hall PTR

Modern VLSI Design 3e: Chapter 6

Copyright 1998, 2002 Prentice Hall PTR

Barrel shifter layout

Barrel shifter in action

Modern VLSI Design 3e: Chapter 6

Modern VLSI Design 3e: Chapter 6

Copyright 1998, 2002 Prentice Hall PTR

Compute sum and carry from P and G:

Modern VLSI Design 3e: Chapter 6

Copyright 1998, 2002 Prentice Hall PTR

Modern VLSI Design 3e: Chapter 6

Copyright 1998, 2002 Prentice Hall PTR

Can recursively expand carry formula:

Modern VLSI Design 3e: Chapter 6

Copyright 1998, 2002 Prentice Hall PTR

Modern VLSI Design 3e: Chapter 6

Copyright 1998, 2002 Prentice Hall PTR

Two-bit carry-skip structure

Modern VLSI Design 3e: Chapter 6

Copyright 1998, 2002 Prentice Hall PTR

Modern VLSI Design 3e: Chapter 6

Copyright 1998, 2002 Prentice Hall PTR

Manchester carry chain

Modern VLSI Design 3e: Chapter 6

Copyright 1998, 2002 Prentice Hall PTR

Manchester carry chain circuit

Serial adder structure

Modern VLSI Design 3e: Chapter 6

Copyright 1998, 2002 Prentice Hall PTR

Modern VLSI Design 3e: Chapter 6

Copyright 1998, 2002 Prentice Hall PTR

Function block circuit

Modern VLSI Design 3e: Chapter 6

Copyright 1998, 2002 Prentice Hall PTR

Modern VLSI Design 3e: Chapter 6

Copyright 1998, 2002 Prentice Hall PTR

Function blocks and ALUs

Modern VLSI Design 3e: Chapter 6

Copyright 1998, 2002 Prentice Hall PTR

Word serial multiplier

Modern VLSI Design 3e: Chapter 6

Copyright 1998, 2002 Prentice Hall PTR

Modern VLSI Design 3e: Chapter 6

Copyright 1998, 2002 Prentice Hall PTR

Elementary school algorithm

Copyright 1998, 2002 Prentice Hall PTR