Advanced Digital System Design
Concurrent Statements
DR. DIPALI BORAKHADE
ASSISTANT PROFESSOR
ST. VINCENT PALLOTTI COLLEGE OF ENGINEERING AND TECHNOLOGY ,
NAGPUR
v Signal assignment statement can appear inside a process or directly in an
architecture.
v Accordingly, sequential signal assignment statements and concurrent signal
assignment statements can be distinguished.
v The latter can be divided into simple concurrent signal assignment, conditional
signal assignment and selected signal assignment.
Concurrent vs. Sequential Signal Assignment
Statements
Concurrent Signal Assignment Sequential Signal Assignment
1) Ordering of the statement is not important 1) These are executed serially one after the other.
and architecture body can contain any number Final output depends on order of statements.
of statements
2) These are event triggered statements. i.e. 2) These are not event triggered and are
whenever there is an event on signal, the executed in sequence in relation to other
statement is executed. sequential statements.
3) The statement that appears outside the 3) Signal assignment statement that appears
process body are called concurrent signal within the process body are called sequential
assignment statement. signal assignment statement
concurrent ----> when...else
----> with …..select
sequential ----> if...else
----> case...when
Selected Signal Assignment
q The most specific way to do this is with as selected signal
assignment.
q A selected signal assignment is a clear way of assigning a signal
based on a specific list of combinations for one input signal.
q These statements selects different values for target signal based
on values of select expression.
With Select Statement
with selection_expression select
signal <= expression_1 when options_1,
...
expression_n when options_n,
[expression when others];
Write the VHDL Code for 4:1 multiplexer using Selected signal
Assignment Statement(Concurrent statement)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
With S Select
entity multiplexer4_1 is Y<= I(0) WHEN “00”,
port ( i : in std_logic_vector(3 downto 0); I(1) WHEN “01”,
S : in std_logic_vector(1 downto 0); I(2) WHEN “10”,
Y : out std_logic); I(3) WHEN “11”;
end multiplexer4_1; END Behavioral;
architecture Behavioral of multiplexer4_1 is
begin
Write the VHDL Code for 3:8 Decoder using Selected signal
Assignment Statement(Concurrent statement)
architecture dataflow of decoder is
begin
library IEEE; with A select
use IEEE.STD_LOGIC_1164.ALL; y<="00000001" when "000",
"00000010" when "001",
"00000100" when "010",
entity decoder is "00001000" when "011",
Port ( A : in STD_LOGIC_VECTOR (2 downto 0); "00010000" when "100",
y : out STD_LOGIC_VECTOR (7 downto 0)); "00100000" when "101",
"01000000" when "110",
end decoder;
"10000000" when "111",
"00000000" when others;
end dataflow;
Conditional Signal Assignment
q The concurrent signal assignment statements can appear inside
an architecture. Concurrent signal assignments are activated
whenever any of the signals in the associated waveforms
change their value.
q If there are multiple assignments to the same signal then
multiple drivers will be created for it.
When – Else Statement
signal_name <= expression_1 when condition_1 else
expression_2 when condition_2
else expression_3 ;
architecture COND of BRANCH is
begin
Z <= A when X > 5 else
B when X < 5 else
C;
end COND;
Design 8:1 Mux using conditional signal assignment
statement
Architecture dataflow of MUX is
Library ieee; Begin
Use ieee.std_logic_1164.all; Y < = I (0) when S = “000” else
I (1) when S = “001” else
Entity MUX8to1 is I (2) when S = “010” else
Port ( I in std_logic_vector (7 downto 0); I (3) when S = “011” else
S in std_logic_vector (2 downto 0); I (4) when S = “100” else
Y out std_logic ); I (5) when S = “101” else
End MUX8to1; I (6) when S = “110” else
I (7) ;
End dataflow
Design 3:8 Decoder using conditional signal assignment
statement
Architecture dataflow of MUX is
Begin
Library ieee;
Y < = “00000001” when S = “000” else
Use ieee.std_logic_1164.all;
“00000010” when S = “001” else
“00000100” when S = “010” else
Entity MUX8to1 is
“00001000” when S = “011” else
Port ( S in std_logic_logic (2 downto 0);
“00010000” when S = 100” else
Y in std_logic_logic (7 downto 0));
“00100000” when S = “101” else
End MUX8to1;
“01000000” when S = “110” else
“10000000” when S = “111” else
“xxxxxxxx” ; End dataflow
