VIETNAM NATIONAL UNIVERSITY HANOI (VNU)

INFORMATION TECHNOLOGY INSTITUTE

Data Flow Modeling of Combinational

Logic

Xuan-Tu Tran

Vietnam National University, Hanoi

Email: tutx@vnu.edu.vn

Contents

• Describing Conbinational Logic Using Dataflow Design Style

• Minimum Logic Unit Example

September 11, 2022 Xuan-Tu Tran 2

1
 Register Transfer Level (RTL) Design Description

Today’s Topic

Combinational
Logic
Combinational …
Logic

Registers

September 11, 2022 Xuan-Tu Tran 3

Describing
Combinational Logic
Using
Dataflow Design Style

September 11, 2022 Xuan-Tu Tran 4

2
 VHDL Design Styles

VHDL Design
Styles

dataflow structural behavioral

Concurrent Components and Sequential statements

statements interconnects • Registers
• State machines
• Test benches

September 11, 2022 Xuan-Tu Tran 5

Data-flow VHDL

Major instructions

Concurrent statements
• concurrent signal assignment ()
• conditional concurrent signal assignment
(when-else)
• selected concurrent signal assignment
(with-select-when)
• generate scheme for equations
(for-generate)

September 11, 2022 Xuan-Tu Tran 6

3
 Data-flow VHDL

Major instructions

Concurrent statements
• concurrent signal assignment ()
• conditional concurrent signal assignment
(when-else)
• selected concurrent signal assignment
(with-select-when)
• generate scheme for equations
(for-generate)

September 11, 2022 Xuan-Tu Tran 7

xi yi
ci 00 01 11 10

0 1 1
ci xi yi si xi yi
c

i
ci
+ 1

xi yi 1 00 011 11 10
1
Data-flow VHDL:0 Example
0 0
c
0 0
c i x y 00 01 11 10 0 1 1
0 0 1 i 0i 1 i si
i si = xi  yi  ci
c

+ 1

0 1 0 0 1 1 1 1
0 1 1 0 10 0 0 0 0 1 0 1
ci xi yi si 0x i y i0 1 xi yi
i 1 0 0 0 1 0 1
si = xi  yi  ci
c

+ 1

0 1 000 0 1 10 ci
1 0 1 c i 0 11 1 1
1001 1 11 0
1 00 01 11 10
0 0 0 0 0 1 1 0 1 0 xi yi
10 0 0 1 0 1 1 0 ci
1
0 0 ci 1x i 0 1 1 1 1 1 10 1 1 1 00 01 11 10
yi c

i + 1
si si = x i 0 y i  ci
0 1 0 0 1 1 1 0 1 0 1 1 1 11
1 1 1 0
1 1 1 1 1
0 10 10 0 1 0 0 0
xi yi
(a) Truth table 1 1 1 1
1 00 00 1
0 0
1 1
i i s = x  y  ci
i
ci + 1 = xi yi + xici + yici
0 10 0 1 c i (a) Truth
00 table01 11 10
1 00 11 1
1 1
0 0 ci + 1 = xi yi + xici + yici
xi yi
1 11 00 0 1 0 0 1 0 00 1 (b) Karnaugh maps
ci 01 11 10
1 11 10 1 1 1 1 0 (b) Karnaugh maps
1 1 0 1 0 xi
Truth table 0 1 xi 11 1 1
1 1 1 1 1
yi si
(a) Truth table 1 yi 1 1 1 si
ci
ci + 1 = xi yi + xici + yici
(a) Truth table c
c i + 1 = x ii y i + x i c i + y i c i

(b) Karnaugh maps

(b) Karnaugh maps
xi
xi
c i + 1c i + 1
yi yi si si

ci ci
September 11, 2022 Xuan-Tu Tran 8

(c) Circuit
(c) Circuit

ci + 1
ci + 1

(c) Circuit
4
 Data-flow VHDL: Example (1)

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY fulladd IS
PORT ( x : IN STD_LOGIC ;
y : IN STD_LOGIC ;
cin : IN STD_LOGIC ;
s : OUT STD_LOGIC ;
cout : OUT STD_LOGIC );
END fulladd ;

September 11, 2022 Xuan-Tu Tran 9

Data-flow VHDL: Example (2)

ARCHITECTURE fulladd_dataflow OF fulladd IS

BEGIN
s <= x XOR y XOR cin ;
cout <= (x AND y) OR (cin AND x) OR (cin AND y) ;
END fulladd_dataflow ;

September 11, 2022 Xuan-Tu Tran 10

5
 Logic Operators

• Logic operators
and or nand nor xor not xnor

• Logic operators precedence

only in VHDL-93

Highest
not
and or nand nor xor xnor
Lowest

September 11, 2022 Xuan-Tu Tran 11

No Implied Precedence

Wanted: y = ab + cd
Incorrect
y <= a and b or c and d ;
equivalent to
y <= ((a and b) or c) and d ;
equivalent to
y = (ab + c)d

Correct
y <= (a and b) or (c and d) ;

September 11, 2022 Xuan-Tu Tran 12

6
 Concatenation

SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL c, d, e, f: STD_LOGIC_VECTOR(7 DOWNTO 0);

a <= ”0000”;
b <= ”1111”;
c <= a & b; -- c = ”00001111”

d <= ‘0’ & ”0001111”; -- d <= ”00001111”

e <= ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘1’ & ‘1’ &
‘1’ & ‘1’; -- e <= ”00001111”
f <= (‘0’,‘0’,‘0’,‘0’,‘1’,‘1’,‘1’,‘1’) ;
-- f <= ”00001111”
September 11, 2022 Xuan-Tu Tran 13

Rotations in VHDL

a<<<1

a(3) a(2) a(1) a(0)

a(2) a(1) a(0) a(3)

a_rotL <= a(2 downto 0) & a(3)

September 11, 2022 Xuan-Tu Tran 14

7
 Arithmetic Operators in VHDL (1)

To use basic arithmetic operations involving

std_logic_vectors you need to include the
following library packages:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
or
USE ieee.std_logic_signed.all;

September 11, 2022 Xuan-Tu Tran 15

Arithmetic Operators in VHDL (2)

You can use standard +, - operators

to perform addition and subtraction:

signal A : STD_LOGIC_VECTOR(3 downto 0);

signal B : STD_LOGIC_VECTOR(3 downto 0);
signal C : STD_LOGIC_VECTOR(3 downto 0);
……
C <= A + B;

September 11, 2022 Xuan-Tu Tran 16

8
 Mixing Signed and Unsigned arithmetic

To mix signed and unsigned arithmetic in the same

design, use the following library:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
signal A : UNSIGNED(3 downto 0);
signal B : UNSIGNED(3 downto 0);
signal C : UNSIGNED(3 downto 0);
signal D : SIGNED(3 downto 0);
……
C <= A + B;
D <= SIGNED(A) + SIGNED(B);

September 11, 2022 Xuan-Tu Tran 17

Data-flow VHDL

Major instructions

Concurrent statements
• concurrent signal assignment ()
• conditional concurrent signal assignment
(when-else)
• selected concurrent signal assignment
(with-select-when)
• generate scheme for equations
(for-generate)

September 11, 2022 Xuan-Tu Tran 18

9
 Conditional concurrent signal assignment

When - Else
target_signal <= value1 when condition1 else
value2 when condition2 else
. . .
valueN-1 when conditionN-1 else
valueN;

0
Value N
.… … 0
1
Value N-1 0
1 Target Signal
1
Value 2
Value 1
Condition N-1

Condition 2
Condition 1
September 11, 2022 Xuan-Tu Tran 19

Operators

• Relational operators
= /= < <= > >=

• Logic and relational operators precedence

Highest not
= /= < <= > >=
Lowest and or nand nor xor xnor

September 11, 2022 Xuan-Tu Tran 20

10
 Priority of logic and relational operators

compare a = bc
Incorrect
… when a = b and c else …
equivalent to
… when (a = b) and c else …

Correct
… when a = (b and c) else …

September 11, 2022 Xuan-Tu Tran 21

Tri-state Buffer – example (1)

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY tri_state IS
PORT ( ena: IN STD_LOGIC;
input: IN STD_LOGIC_VECTOR(7 downto 0);
output: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END tri_state;

September 11, 2022 Xuan-Tu Tran 22

11
 Tri-state Buffer – example (2)

ARCHITECTURE tri_state_dataflow OF tri_state IS

BEGIN
output <= input WHEN (ena = ‘0’) ELSE
(OTHERS => ‘Z’);
END tri_state_dataflow;

September 11, 2022 Xuan-Tu Tran 23

Data-flow VHDL

Major instructions

Concurrent statements
• concurrent signal assignment ()
• conditional concurrent signal assignment
(when-else)
• selected concurrent signal assignment
(with-select-when)
• generate scheme for equations
(for-generate)

September 11, 2022 Xuan-Tu Tran 24

12
 Selected concurrent signal assignment

With –Select-When
with choice_expression select
target_signal <= expression1 when choices_1,
expression2 when choices_2,
. . .
expressionN when choices_N;

expression1 choices_1
expression2 choices_2
target_signal

expressionN choices_N

choice expression
September 11, 2022 Xuan-Tu Tran 25

Allowed formats of choices_k

WHEN value

WHEN value_1 to value_2

WHEN value_1 | value_2 | .... | value N

September 11, 2022 Xuan-Tu Tran 26

13
 Allowed formats of choice_k - example

WITH sel SELECT

y <= a WHEN "000",
b WHEN "011" to "110",
c WHEN "001" | "111",
d WHEN OTHERS;

September 11, 2022 Xuan-Tu Tran 27

Minimum Logic Unit (MLU) Example

September 11, 2022 Xuan-Tu Tran 28

14
 MLU: Block Diagram

MUX_0
A1
A

IN 0
MUX_1
NEG_A IN 1
Y1
MUX_2
IN 2

IN 3 O U T PU T Y
S E L1

S E L0

B1 NEG_Y
B MUX_4_1

MUX_3

NEG_B
L1 L0

September 11, 2022 Xuan-Tu Tran 29

MLU: Entity Declaration

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY mlu IS
PORT(
NEG_A : IN STD_LOGIC;
NEG_B : IN STD_LOGIC;
NEG_Y : IN STD_LOGIC;
A: IN STD_LOGIC;
B: IN STD_LOGIC;
L1 : IN STD_LOGIC;
L0 : IN STD_LOGIC;
Y: OUT STD_LOGIC
);
END mlu;

September 11, 2022 Xuan-Tu Tran 30

15
 MLU: Architecture Declarative Section

ARCHITECTURE mlu_dataflow OF mlu IS

SIGNAL A1 : STD_LOGIC;
SIGNAL B1 : STD_LOGIC;
SIGNAL Y1 : STD_LOGIC;
SIGNAL MUX_0 : STD_LOGIC;
SIGNAL MUX_1 : STD_LOGIC;
SIGNAL MUX_2 : STD_LOGIC;
SIGNAL MUX_3 : STD_LOGIC;
SIGNAL L: STD_LOGIC_VECTOR(1 DOWNTO 0);

September 11, 2022 Xuan-Tu Tran 31

MLU - Architecture Body

BEGIN
A1<= NOT A WHEN (NEG_A='1') ELSE
A;
B1<= NOT B WHEN (NEG_B='1') ELSE
B;
Y <= NOT Y1 WHEN (NEG_Y='1') ELSE
Y1;

MUX_0 <= A1 AND B1;

MUX_1 <= A1 OR B1;
MUX_2 <= A1 XOR B1;
MUX_3 <= A1 XNOR B1;

L <= L1 & L0;

with (L) select

Y1 <= MUX_0 WHEN "00",
MUX_1 WHEN "01",
MUX_2 WHEN "10",
MUX_3 WHEN OTHERS;

END mlu_dataflow;

September 11, 2022 Xuan-Tu Tran 32

16
 Exercise

• Prove that the MLU design works as expected by writing a

testbench for it and run the simulation in Modelsim

September 11, 2022 Xuan-Tu Tran 33

17