EEE 531: Semiconductor Device Theory I

EEE 531: Semiconductor Device Theory I

Instructor: Dragica Vasileska
(Notes provided by: Prof. Dieter Schroder)
Department of Electrical Engineering
Arizona State University
Topic covered:
Introduction to some general concepts for PN-
junctions
EEE 531: Semiconductor Device Theory I
1. PN-junctions - General Consideration:
PN-junction is a two terminal device.
Based on the doping profile, PN-junctions can be
separated into two major categories:
- step junctions
- linearly-graded junctions
p-side n-side
A D
N N
p-side n-side
A D
N N
ax
Step junction Linearly-graded junction
EEE 531: Semiconductor Device Theory I
(A) Equilibrium analysis of step junctions
(a) Built-in voltage V
bi
:
(b) Majority- minority carrier
relationship:
C
E
V
E
i
E
F
E
bi
qV
W
) (x
x
-qN
A
qN
D
) (x V
x
bi
V
) (x E
x
max
E
p
x
n
x
+
-
p-side
n-side
( ) ( )
( ) [ ]
[ ]

,
_

,
_

+
2 2
0 0
0
0
ln ln
exp
exp
i
D A
T
i
n p
B
bi
B F i i p
B i F i n
n
i F
p
F i bi
n
N N
V
n
n p
q
T k
V
T k E E n p
T k E E n n
E E E E qV
[ ]
[ ]
T bi n p
T bi p n
V V n n
V V p p
/ exp
/ exp
0 0
0 0


EEE 531: Semiconductor Device Theory I
(c) Depletion region width:
Solve 1D Poisson equation using depletion charge
approximation, subject to the following boundary condi-
tions:
p-side:
n-side:
Use the continuity of the two solutions at x=0, and
charge neutrality, to obtain the expression for the depletion
region width W:
0 ) ( ) ( , ) ( , 0 ) (
p n bi n p
x E x E V x V x V
( )
2
0
2
) (
p
s
A
p
x x
k
qN
x V +

( )
bi n
s
D
n
V x x
k
qN
x V +

2
0
2
) (
D A
bi D A s
n D p A
n p
p n
N qN
V N N k
W
x N x N
V V
W x x
) ( 2
) 0 ( ) 0 (
0
+

+
EEE 531: Semiconductor Device Theory I
(d) Maximum electric field:
The maximum electric field, which occurs at the
metallurgical junction, is given by:
(e) Carrier concentration variation:
) (
0 0
max
D A s
D A
x
N N k
W N qN
dx
dV
E
+

10
5
10
7
10
9
10
11
10
13
10
15
0 0.5 1 1.5 2 2.5 3 3.5
n [cm
-3
]
p [cm
-3
]
C
o
n
c
e
n
t
r
a
t
i
o
n


[
c
m
-
3
]
Distance [m]
cm kV E
cm kV E
m W
cm N N
sim
DC
calc
D A
/ 93 . 8
/ 36 . 9
23 . 1
10
) max(
) max(
3 15

EEE 531: Semiconductor Device Theory I
cm kV E cm kV E m W
cm N N
sim DC calc
D A
/ 93 . 8 , / 36 . 9 , 23 . 1
10
) max( ) max(
3 15



-10
15
-5x10
14
0
5x10
14
10
15
0 0.5 1 1.5 2 2.5 3 3.5

(
x
)
/
q


[
c
m
-
3
]
Distance [m]
-10
-8
-6
-4
-2
0
0 0.5 1 1.5 2 2.5 3 3.5
E
l
e
c
t
r
i
c

f
i
e
l
d


[
k
V
/
c
m
]
Distance [m]
EEE 531: Semiconductor Device Theory I
cm kV E cm kV E m W
cm N cm N
sim DC calc
D A
/ 67 , / 53 . 49 , 328 . 0
10 , 10
) max( ) max(
3 18 3 16





-10
17
-5x10
16
0
5x10
16
10
17
0.6 0.8 1 1.2 1.4

(
x
)
/
q


[
c
m
-
3
]
Distance [m]
-70
-60
-50
-40
-30
-20
-10
0
10
0.6 0.8 1 1.2 1.4
E
l
e
c
t
r
i
c

f
i
e
l
d


[
k
V
/
c
m
]
Distance [m]
EEE 531: Semiconductor Device Theory I
(f) Depletion layer capacitance:
Consider a p
+
n, or one-sided junction, for which:
The depletion layer capacitance is calculated using:
( )
D
bi s
qN
V V k
W
m
0
2

0
2
0
) ( 2 1
) ( 2

s D
bi
bi
s D D c
k qN
V V
C
V V
k qN
dV
dW qN
dV
dQ
C
m
m
V V
bi

V
2
1 C
D
N
slope
1

Forward bias
Reverse
bias
Measurement setup:
W
dW
~
V
v
ac
EEE 531: Semiconductor Device Theory I
(B) Equilibrium analysis of linearly-graded junction:
(a) Depletion layer width:
(c) Maximum electric field:
(d) Depletion layer capacitance:
Based on accurate numerical simulations, the depletion
layer capacitance can be more accurately calculated if V
bi
is replaced by the gradient voltage V
g
:
( )
3 / 1
0
12
1
]
1

qa
V V k
W
bi s
m
( )
3 / 1
2
0
2
12
1
]
1

V V
qak
C
bi
s
m
0
2
max
8

s
k
qaW
E
1
]
1

3
0
2
8
ln
3
2
i
T s
T g
qn
V k a
V V