List of Experiments

Date Lab Aim

14.08.2025 1 Introduction of the Lab experiments.
21.08.2025 2 Introduction of the SEMulator3D tool.
27.08.2025 3 To study different types of semiconductor wafers and substrates by observing their
structural and material properties.
03.09.2025 4 To perform wafer cutting and cleaning of a glass slide substrate in order to remove
contaminants and prepare it for thin-film deposition.
10.09.2025 5 To design and study a lithography mask pattern for Shallow Trench Isolation (STI),
illustrating line-space structures within a defined boundary for device isolation.

17.09.2025 6 To deposit a uniform thin film of precursor solution on a glass substrate using the
spin-coating technique, with control of parameters such as acceleration time,
control/holding/dwelling time.
24.09.2025 7 To design and study a lithography mask pattern for Local Oxidation of Silicon
(LOCOS), demonstrating selective oxidation for device isolation.
30.09.2025 8 To study the oxidation process using a vacuum oven and a muffle furnace.
Demonstration-based Experiments (Fab Lab Visit)
•Experiment 3 (Wafers)
•Experiment 4 (Cleaning)
•Experiment 6 (Spin coating)
•Experiment 8 (Oxidation process with vacuum oven & muffle furnace)

What to write:
•Aim (as given, e.g., To study the oxidation process using a vacuum oven and a muffle furnace.)
•Apparatus: Mention actual equipment (wafer samples, DI water, spin coater, vacuum oven,
muffle furnace, etc.)
•Procedure: Write the steps observed in the demonstration (cutting, cleaning, loading wafer,
heating, calibration, spin coating recipe, etc.)
•Observation: Notes on how the process looked (e.g., “Spin speed affected film uniformity,”
“Surface became hydrophilic after cleaning”).
•Result: Students understand the principle and working of the demonstrated process.
Design-based Experiments (with Simulator/3D Tool)
•Experiment 5 (STI mask design)
•Experiment 7 (LOCOS mask design)

What to write:
•Aim (as given, e.g., To design and study a lithography mask pattern for Shallow Trench
Isolation...)
•Apparatus/Software: 3D Layout Design Tool / Semiconductor Process Simulator
•Procedure: Steps followed in the simulator (open software, set boundary, define mask
dimensions, run simulation, visualize layout, etc.)
•Observation: Layout diagrams / screenshots from simulator
•Result: The required mask pattern was successfully designed and analyzed.
 Experiment-1
Shallow Trench Isolation (STI)
 Shallow trench isolation

• Shallow Trench Isolation (STI) is an integrated

circuit fabrication technique that creates electrical
insulation between neighboring semiconductor
devices, preventing current leakage.

• It involves etching shallow trenches into a silicon

wafer, filling them with a dielectric material like
silicon dioxide, and then using chemical
mechanical polishing (CMP) to create a flat
surface.

• STI is generally used on CMOS process

technology nodes of 250 nanometers and smaller.
Older CMOS technologies and non-MOS
technologies commonly use isolation based on
LOCOS.
PAD Nitride Etch
PAD Oxide Etch
Create Sequence Remove Materials (Utility)
 Assignment

Design 1: Parallel Line Array (Grating-like Structure)

•Boundary box: 500 nm × 400 nm
•Mask openings:
• Four vertical lines, each 40 nm wide,
• Separated by 60 nm spacing.
•Pattern orientation: Along Y-axis (similar to line-space grating).

Design 2: Cross Pattern (Orthogonal Intersections)

•Boundary box: 500 nm × 500 nm
•Mask openings:
• One horizontal bar: 60 nm wide, spanning full width (500 nm).
• One vertical bar: 60 nm wide, spanning full height (500 nm).
• Both cross at the center.
 Experiment-2
LOCal Oxidation of Silicon
(LOCOS)
 LOCOS

Introduction: Need for Isolation:

• LOCOS (LOCal Oxidation of • Why isolation is required:
Silicon) is a microfabrication process ➢ Prevents electrical interference
where silicon dioxide is formed in between transistors
selected areas on a silicon wafer having ➢ Reduces leakage currents
the Si-SiO2 interface at a lower point ➢ Improves device reliability
than the rest of the silicon surface.
• Purpose: To isolate MOS transistors & • Requirement: Oxide must penetrate
reduce cross-talk beneath surface → not possible by
• Widely used until late 1990s → etching
replaced by Shallow Trench Isolation
(STI) after 2008
 Isolation depth

LOCOS (Recessed oxide):

• Isolation is achieved by oxidizing silicon locally, so the oxide penetrates
beneath the silicon surface.
• Depth depends on oxidation time and temperature (~0.5–1 µm).

STI (Shallow Trench Isolation):

• Instead of oxidizing, a trench is etched into silicon and then filled with oxide.
• Isolation depth can be precisely controlled by trench depth (e.g., 0.2–0.5 µm).

👉 Key Difference: LOCOS uses thermal oxidation, STI uses etched trenches filled
with oxide.
 Scalability
LOCOS:
• Has the Bird’s Beak effect (oxide encroaches under nitride mask).
• Wastes silicon area → limits scaling below ~0.35 µm technology node.

STI:
• No Bird’s Beak issue since oxide is confined within trenches.
• Works well for deep submicron (<0.25 µm) devices.

👉 Key Difference: STI is scalable to modern nanometre CMOS, LOCOS is not.

 Stress
LOCOS:
• High stress develops at the Si/SiO₂ interface during oxidation.
• Can cause defects like dislocations, impacting device reliability.

STI:
• Stress is lower because oxide is deposited in trenches, not grown thermally
inside silicon.
• Better reliability for small devices.

👉 Key Difference: STI reduces mechanical stress compared to LOCOS.

 Process Steps
LOCOS:
• Suitable for older technology nodes (>0.35 µm).
• Still used in high-voltage, power, and analog ICs.

STI:
• Standard for modern CMOS (<0.25 µm, down to nanometer scale).
• Enables higher density and faster devices.

👉 LOCOS is historical; STI is current industry standard.

Technology Node
Design: LOCOS Field-Oxide Layout (Two Trenches in Long Region)

• Boundary box: 2000 nm × 200 nm

• Two rectangular openings, each 500 nm × 200 nm (full height)
 Assignment-2
1. To understand and design mask layouts for LOCOS (Local Oxidation of
Silicon) and STI (Shallow Trench Isolation) isolation methods used in
VLSI technology.
• LOCOS Mask Layout
➢ Active region consists of two windows of size 50 nm (width).
➢ The two windows are separated by 300 nm.
➢ The overall mask width is 100 nm.
➢ The windows must be symmetrically placed, ensuring equal spacing from the left and
right boundary edges.
• STI Mask Layout
➢ Follow the same design principle as in LOCOS.
➢ Replace the LOCOS field-oxide region with a trench isolation mask of equivalent
dimensions.
➢ Ensure correct alignment and symmetry in the drawn mask.
2. Explain LOCOS process and bird beak effect.
3. Draw a graph of achieved isolation trench pitch versus planned
isolation trench pitch (in layout). What is the smallest isolation
trench pitch you can achieve?
4. Comment on the dishing in silicon oxide after CMP.
 Experiment-3
NMOS Mask layout design and
Fabrication
Process Steps for NMOS Fabrication
1.Wafer Setup → start with p-type Si wafer (substrate).
2.Isolation → grow pad oxide + nitride, use Active Area mask, form LOCOS/STI isolation.
3.Gate Oxide Formation → thermally grow thin SiO₂ (~5–10 nm).
4.Polysilicon Deposition & Patterning → deposit polysilicon, lithography with Poly Gate mask, etch
to form gates.
5.Spacer Formation → deposit oxide/nitride and anisotropically etch to form sidewall spacers.
6.N+ Source/Drain Implantation → lithography with N+ mask, implant As/P, anneal to activate.
7.Interlayer Dielectric (ILD) → deposit SiO₂ over wafer.
8.Contact Formation → lithography with Contact mask, etch contact holes to S/D/G.
9.Metallization → deposit Al/Cu, lithography with Metal mask, etch to form interconnects.