VLSI Design

Mrs.T.Sunitha, Asst.Prof
Dept. of Electronics and Telematics Eng.
GNITS, Hyderabad

13 September 2022 VLSI Design Ch. 1 1

 VLSI

• Very-large-scale integration (VLSI) is the process

of creating an integrated circuit (IC) by combining
millions of transistors into a single chip.

• VLSI began in the 1970s when

complex semiconductor and communication tech
nologies were being developed.
The microprocessor and memory chips are VLSI
devices.

13 September 2022 VLSI Design Unit I Session 1 2

 Syllabus
Unit I
Part-1: Introduction

• Introduction to MOS Technology

• MOS, PMOS, NMOS, CMOS, BiCMOS
Technologies

13 September 2022 VLSI Design Syllabus 3

 UNIT-1
PART-2: Basic Electrical Properties
• Basic Electrical Properties of MOS, CMOS and BiCMOS
Circuits: Ids-Vds relationships
• MOS transistor threshold VoltageVt
• gm , gds, figure of merit w0
• Pass transistor, NMOS inverter
• Various pull - ups
• Determination of pull-up to pull-down ratio( Zpu / Zpd )
• CMOS Inverter analysis and design
• Bi CMOS inverters
• Latch-up in CMOS circuits

13 September 2022 VLSI Design Unit I Session 1 4

 UNIT-2
VLSI Circuit Design Processes
• VLSI Design Flow
• MOS Layers, Stick Diagrams
• Design Rules and Layouts - Lambda based design
rules, Contact cuts , CMOS Lambda based design
rules and
• Layout Diagrams for logic gates, Transistor structures,
wires and vias
• Scaling of MOS circuits- Scaling models, scaling
factors, scaling factors for device parameters,
Limitations of Scaling

13 September 2022 VLSI Design Unit I Session 1 5

 UNIT-3
Gate Level Design
• Switch logic networks: Gate logic
• Alternate gate circuit: Pseudo-NMOS, Dynamic CMOS
logic.
• Basic circuit concepts, Sheet Resistance Rs and its
concept to MOS, Area capacitance Units, Calculations
• The delay unit T, Inverter Delays
• Driving large Capacitive Loads
• Wiring Capacitances
• Fan-in and fan-out
• Choice of layers.
13 September 2022 VLSI Design Unit I Session 1 6
 UNIT-4
PART-1
Data Path Subsystems
• Subsystem Design
• Shifters, Adders,
• ALUs, Multipliers,
• Parity generators,
• Comparators, Zero/One Detectors,
• Counters.

13 September 2022 VLSI Design Unit I Session 1 7

 UNIT-4

PART-2
Array Subsystems
• SRAM
• DRAM
• ROM
• Serial Access Memories

13 September 2022 VLSI Design Unit I Session 1 8

 UNIT-5
Programmable Logic Devices:
• PLAs, FPGAs, CPLDs, Standard Cells
• Programmable Array Logic, Design Approach
• Parameters influencing low power design
CMOS Testing:
• Need for testing, Test Principles
• Design Strategies for test
• Chip-level Test Techniques.
13 September 2022 VLSI Design Unit I Session 1 9
 UNIT-1
Introduction to IC Technology

• IC is an electronic device in which many

devices such as Transistors, Diodes, Resistors,
Capacitors e.t.c are fabricated on a single
small chip.

• It differ from discrete circuits, which is built,

by connecting separated devices.

13 September 2022 VLSI Design Unit I Session 1 10

 Characteristics of ICs

• Size: Miniature
• Extremely low weight
• Low power consumption
• Low cost
• High response time & speed of signal transfer
between circuits
• High Reliability

13 September 2022 VLSI Design Ch. 1 11

 History of microelectronics
• Invention of bipolar transistors, MOSFETs
• Invention of ICs
• Level of integration
• Small scale integration SSI
• Medium scale integration MSI
• Large scale integration LSI
• Very Large scale integration VLSI
• Ultra Large scale integration ULSI

13 September 2022 VLSI Design Ch. 1 12

 Integrated Circuit Era

• Moore’s Law:
-This Law gives the relationship between number
of transistors per chip Vs Year.

Fig.System Complexity
Roadmap

13 September 2022 VLSI Design Unit I Session 1 13

 Integrated Circuit Era
• Moore’s Law (From above figure)
The number of transistors on a chip doubles for
every 18 months.
• Lower supply voltage, Lower channel length with
increasing transistor per chip ratios will make the
system More efficient, higher speed, smaller size,
higher package density.

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 MOS Transistor Circuit Symbols

MOSFET

Depletion Enhancement
MOSFET MOSFET

n-channel p-channel n-channel

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 MOS Transistor Circuit Symbols

With
substrate/bulk/well
connection

Without
substrate/bulk/well
connection

Fig. 1.6 MOS transistor circuit symbols

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 MOS VLSI Technology
• In MOS Technology, the Circuits based on
• nMOS, pMOS, CMOS, BiCMOS
• nMOS
- Design methodology and design rules easily
learnt
- Technology and process Provide background
for other technologies
- allows a relatively easy transition to CMOS
Technology and Design

13 September 2022 VLSI Design Ch. 1 17

 nMOS Transistors
nMOSFET
• Formed on lightly doped p-substrate
• Source/Drain – formed by diffusing n-type
impurities to form depletion region
– Depletion regions extended into
lightly-doped substrate
• Gate provides control
• Interconnection using metal
• Types – Enhancement mode, depletion mode

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 nMOS Transistors
nMOSFET – enhancement mode

n+ source and drain

p- substrate

Fig. 1.4 MOS Transistors

13 September 2022 VLSI Design Ch. 1 19

 nMOS Transistors
nMOSFET – Enhancement mode
• Polysilicon gate deposited
on gate dielectric – Silicon dioxide (SiO2)
• When VD = VS = VG = 0 V,
No channel, no conduction between S/D
• When VGS > Vt ,
channel established
conduction between S/D
Depletion mode
• Channel doped with n-type impurities
• Conduction even when VG = 0 V
13 September 2022 VLSI Design Ch. 1 20
 nMOS Transistors
nMOSFET – depletion mode

n+ source and drain

p- substrate
n implant

Fig. 1.4 MOS Transistors

13 September 2022 VLSI Design Ch. 1 21

 pMOS Transistors
pMOSFET – Enhancement mode
• Formed on lightly doped n-substrate
• Source/Drain – formed by diffusing p-type
impurities to form depletion region
• When VD = VS = VG = 0 V,
No channel, no conduction between S/D
• When VGS (negative voltage) > |Vt |,
Channel established
Conduction between S/D
• pMOS slower than nMOS
• Mobility mn = 2.5 mp
13 September 2022 VLSI Design Ch. 1 22
 pMOS Transistors
pMOSFET – enhancement mode

p+ source and drain

n- substrate

Fig. 1.4 MOS Transistors

13 September 2022 VLSI Design Ch. 1 23
 Enhancement Mode pMOS Transistor

(a) Vgs > Vt,

Vds = 0 V
Ids = 0 A

(b) Vgs > Vt,

Vds < Vgs – Vt
Ids a Vds
Fig. 1.5
Enhancement mode
Transistor operation (c) Vgs > Vt,
Vds > Vgs – Vt
Ids ~ constant
13 September 2022 VLSI Design Ch. 1 24
 nMOS Fabrication
Process Si Substrate

Thick oxide (1 mm)

Photoresist (Negative)

UV light
Mask

Window in oxide
Fig. 1.7 nMOS fabrication
process
13 September 2022 VLSI Design Ch. 1 25
 nMOS Fabrication
Thin oxide
Process (800-1000 Ao)
Patterned poly
(1-2 mm)
n+ diffusion (implant)
(1 mm) deep
CVD oxide dep.
Contact holes (cuts)

Patterned
metallization
(Al 1 mm)

Fig. 1.7 nMOS fabrication process (Continued)

13 September 2022 VLSI Design Ch. 1 26
 nMOS Fabrication
Process steps
1. Starting wafer – single-crystalline Si,
Doped with 1015 to 1016 Boron (B) atoms/cm3,
Resistivity 25 to 2 Ohm cm.
2. 1 mm SiO2 grown to serve as insulation and mask
3. Coated with photoresist
4. Exposure to UV light through a mask and develop
-ve photoresist – exposed region hardens
Mask  opaque region – area for processing
+ve photoresist – exposed region softens
Mask  clear region – area for processing
13 September 2022 VLSI Design Ch. 1 27
 nMOS Fabrication
Process steps
5. SiO2 etched away in exposed areas and
photoresist is removed
6. Thin gate oxide (0.1 mm) grown, PolySi deposited
and patterned to form gate electrode
7. Thin gate oxide removed from Source/Drain areas,
n-type impurity diffused at high temp or implanted
PolySi gate acts as mask for S/D diffusion
Known as self-aligned technology (SAT)
8. Thick oxide grown, patterned over gate,
S/D regions to make contacts
13 September 2022 VLSI Design Ch. 1 28
 nMOS Fabrication
Process steps
9. Metal deposited and patterned
to provide interconnect

13 September 2022 VLSI Design Ch. 1 29

 nMOS Fabrication
Process Summary
Mask 1 – Defines active region or thin oxide
Mask 2 – Pattern Ion implantation in active region
for depletion mode devices
Mask 3 – Pattern Poly Si,
remove thin oxide,
diffuse (implant) n+ S/D regions
Mask 4 – Contact cut
Mask 5 – Metal interconnect pattern
Mask 6 – Pad opening in Overglass/passivation layer

13 September 2022 VLSI Design Ch. 1 30

 CMOS Fabrication
Process steps
• Many approaches
- p-well process,
- n-well process,
- twin-tub or twin-well process,
- Silicon-on-Insulator (SOI) process
• p-well process– widely used
n-well process also popular used
Twin-tub (or Twin-well) process
– Currently used
13 September 2022 VLSI Design Ch. 1 53
 CMOS Fabrication
p-well
process p-well (4 - 5 mm)

Thin oxide
and polysilicon

p-implant
p+ mask
(positive)
n-implant
p+ mask
(negative)
Fig. 1.9 CMOS p-well process
13 September 2022 VLSI Design Ch. 1 54
 CMOS Fabrication
Process steps - p-well process
• n-type substrate,
pMOS devices formed using masking and diffusion
• p-well is formed by diffusion,
to make nMOS devices
• p-well dopant concentration and depth affect
threshold voltage and breakdown voltage
• For Vt of 0.6 to 1.0 V,
use deep p-well or high well resistivity
 Larger spacing between transistors and wires
 Larger chip area
13 September 2022 VLSI Design Ch. 1 55
 CMOS Fabrication
Process Summary
Mask 1 – p-well region
Mask 2 – Defines active region or thin oxide
Mask 3 – Pattern Poly Si
Mask 4 – p+ mask for p-diffusion
Mask 5 – Negative form of Mask 4 and
Common to all technologies Mask 2 for n-type diffusion
Mask 6 – Contact cuts
Mask 7 – Metal interconnect pattern
Mask 8 – Pad opening in Overglass/passivation layer
13 September 2022 VLSI Design Ch. 1 56
 CMOS Fabrication
n-well process
• Easy to retrofit nMOS process
• Better than p-well process
• Lower substrate bias effects on
Vt and S/D parasitic capacitance
• n+ mask and its complement used
for defining n+ and p+ regions
• Or p+ mask and its complement can be used
• Also include VDD and VSS contacts

13 September 2022 VLSI Design Ch. 1 57

 CMOS Fabrication
n-well process Steps
1. Formation of n-well regions – masking and
Phosphorus implant and high temp diffusion
2. Define nMOS and pMOS devices, diffusion regions
3. Grow field oxide and gate oxide
4. Deposit and pattern poly Si
5. p+ diffusion for pMOS Source/Drain
6. n+ diffusion for nMOS Source/Drain
7. Deposit interlevel oxide, pattern contact cuts
8. Deposit metal and pattern
9. Overglass/passivation and pad opening
13 September 2022 VLSI Design Ch. 1 58
 CMOS Fabrication
n-well
process

Fig. 1.11 Main steps in a typical n-well process

13 September 2022 VLSI Design Ch. 1 59
 CMOS Fabrication
CMOS process flow :
n-well process

oxide

oxide

Ref: http://en.wikipedia.org/wiki/CMOS
13 September 2022 VLSI Design Ch. 1 60
 CMOS Fabrication
CMOS Structure
n-well process

Structure of CMOS (n-well process)

Ref: http://en.wikipedia.org/wiki/CMOS
13 September 2022 VLSI Design Ch. 1 61
 CMOS Fabrication
Process steps - n-well process
• n+ mask used for n+ Source/Drain
its complement used for p+ Source/Drain
• Same masks for VSS and VDD connections

13 September 2022 VLSI Design Ch. 1 62

 CMOS Fabrication
n-well process
• Latchup problems reduced
by low resistance epitaxial layer,
also acts as a low resistance substrate
• pMOS transistor performance degraded
• Twin-well process used to fix these issues

13 September 2022 VLSI Design Ch. 1 63

 CMOS Fabrication
Twin-tub process
• Start with high resistivity n-type material
• Form both n-well and p-well regions
• Possible to preserve
both nMOS and pMOS transistor characteristics
• Allow separate optimization of
nMOS and pMOS transistors
• Doping control is achieved
• Latchup susceptibility reduced

13 September 2022 VLSI Design Ch. 1 64

 CMOS Fabrication
Twin-tub (or Twin-well) process

pMOSFET nMOSFET

n+ p+ p+ n+ n+ p+

Fig. 1.14 Twin-tub or twin-well CMOS structure

13 September 2022 VLSI Design Ch. 1 65
 CMOS Fabrication
• Silicon on Insulator (SOI) process:
-Two common types of SOI are
• a) Sapphire substrate SOI
• b) Silicon based SOI

13 September 2022 VLSI Design Unit I Session 1 66

 CMOS Fabrication

13 September 2022 VLSI Design Unit I Session 1 67

 BiCMOS Technology

13 September 2022 VLSI Design Unit I Session 1 68

 Introduction

• Bipolar Technology was started in 1980’s.

• CMOS Technology was also started in mid
1980’s.
• Later in 1990 there was a cross over between
bipolar and CMOS Technology.
• In BiCMOS technology, both the MOS and
bipolar device are fabricated on the same chip
.

13 September 2022 VLSI Design Unit I Session 1 69

• The objective of the BiCMOS is to combine
bipolar and CMOS so as to exploit the
advantages of both the technologies.
• Today BiCMOS has become one of the
dominant technologies used for high speed,
low power and highly functional VLSI circuits.
• The primary approach to realize high
performance BiCMOS devices is the addition
of bipolar process steps to a baseline CMOS
process.
13 September 2022 VLSI Design Unit I Session 1 70
• The BiCMOS gates could be used as an
effective way of speeding up the VLSI circuits.
• The applications of BiCMOS are vast.
• Advantages of bipolar and CMOS circuits can
be retained in BiCMOS chips.
• BiCMOS technology enables high performance
integrated circuits (IC’s) but increases process
complexity.

13 September 2022 VLSI Design Unit I Session 1 71

• BiCMOS technology is a combination of
Bipolar and CMOS technology.
• CMOS technology offers less power
dissipation, High noise margins, and higher
packing density.
• Bipolar technology, on the other hand,
ensures high switching and I/O speed and
good noise performance

13 September 2022 VLSI Design Unit I Session 1 72

• BiCMOS technology accomplishes both -
improved speed over CMOS and lower power
dissipation than bipolar technology.
• The main drawback of BiCMOS technology is
the higher costs due to the added process
complexity.
• This greater process complexity in BiCMOS
results in a cost increase compared to
conventional CMOS technology.
13 September 2022 VLSI Design Unit I Session 1 73
 BiCMOS Technology
Comparison between CMOS and Bipolar Technologies
CMOS Technology Bipolar Technology
Low static power consumption High power dissipation
High input impedance Low input impedance
(low input drive current) (high input drive current)
Scalable threshold voltage Almost fixed VBE
High noise margin Low voltage swing logic
High packing density Low packing density
High delay sensitivity to load Low delay sensitivity to load
(fan-out limitations)

13 September 2022 VLSI Design Ch. 1 74

 BiCMOS Technology
Comparison between CMOS and Bipolar Tech.
CMOS Technology Bipolar Technology
Low output drive current High output drive current
Low gm High gm
(gm proportional to Vin) [gm proportional to exp(Vin)]
High fT at low currents
Bidirectional capability Essentially unidirectional
(Drain and source (Collector and Emitter
interchangeable) can NOT be interchanged)
A near ideal switching device

13 September 2022 VLSI Design Ch. 1 75

 BICMOS TECHNOLOGY
ADVANTAGES
• Improved speed over CMOS technology
• Lower power dissipation than bipolar technology
(Lower power consumption than bipolar)
• Flexible I/Os for high performance
• Improved current drive over CMOS
• Improved packing density over bipolar
• High input impedance
• Low output impedance
• High Gain and low noise
13 September 2022 VLSI Design Unit I Session 1 76
 BICMOS TECHNOLOGY
DISADVANTAGES
• Increased manufacturing process complexity
• Higher cost
• Speed degradation due to scaling
• Longer fabrication cycle time
BiCMOS process
• Bipolar process + Well + Gate Oxide & Poly +
CMOS process

13 September 2022 VLSI Design Unit I Session 1 77

 APPLICATIONS OF BICMOS
• Full custom ICs
• ALU’s, Barrel Shifters
• SRAM, DRAM
• Microprocessor, Controller
• Semi custom ICs
• Register, Flip-flops ,Standard cells
• Adders, mixers, ADC, DAC
• Gate arrays
• Flash A/D Converters

13 September 2022 VLSI Design Unit I Session 1 78

 BiCMOS Technology

BiCMOS
npn Transistor
Top view

Cross section

Fig. 1.16 Arrangement of

BiCMOS npn transistor

13 September 2022 VLSI Design Ch. 1 79

 BICMOS Cross section

13 September 2022 VLSI Design Unit I Session 1 80

 BiCMOS Technology
BiCMOS Process : Additional steps
• P+ base
• n+ collector area
• n+ buried subcollector
BiCMOS Fabrication in n-well process
• Adding 2 additional masks to CMOS technology
• p base and n+ buried subcollector
• Parasitic bipolar transistors in CMOS
• Increased cost due to additional process steps

13 September 2022 VLSI Design Ch. 1 81

 BiCMOS Technology
n-well BiCMOS Fabrication process
Single Poly, Single Metal Additional steps for Bipolar
CMOS
Form buried n+ layer
Form n-well
Form deep n+ collector
Form p base for bipolar
Delineate active areas
Channel stop
Threshold voltage Vt
adjustment

13 September 2022 VLSI Design Ch. 1 82

 BiCMOS Technology
n-well BiCMOS Fabrication process
Single Poly, Single Metal Additional steps for Bipolar
CMOS
Delineate poly gate areas
Form n+ active areas
Form p+ active areas
Define contacts
Delineate metal areas

13 September 2022 VLSI Design Ch. 1 83

13 September 2022 VLSI Design Unit I Session 1 84
 BICMOS ICs

13 September 2022 VLSI Design Unit I Session 1 85

13 September 2022 VLSI Design Unit I Session 1 86
 Text Books
1. Essentials of VLSI circuits and Systems,
Kamran Eshraghian, Douglas A. Pucknell,
PHI, 2005 edition (or) Basic VLSI Design
by D. A. Pucknell, K Eshraghian,
3rdEdition,PHI,2008.

2. CMOS VLSI Design – A circuit and systems

perspective, Neil H. Weste and David
Harris, Ayan Banerjee, Pearson, 2009.

13 September 2022 VLSI Design Ch. 1 87

 References
1. CMOS logic circuit design, John P.
Uyemura, Springer, 2007.
2. Modern VLSI Design, Wayne Wolf, Pearson
Education, 3rd edition, 1997.
3. VLSI Design, A. Albert Raj, Latha, PHI, 2008.
4. Introduction to VLSI – Mead and Conway,
BS Publications, 2010.
5. VLSI design, M. Michael Vai, CRC Press,
2009.
13 September 2022 VLSI Design Ch. 1 88
• WEBSITES:
• http://www.vlsihandbook.com
• http://www.bicmosdesign.com
• http://website.informer.com
• http://www.freepatentsonline.com/6927460.
html

13 September 2022 VLSI Design Unit I Session 1 89