VLSI Design

Unit III
Gate-level design

Mrs.T.Sunitha, Asst.Prof
Dept. of Electronics and Telematics Eng.
GNITS, Hyderabad

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 Unit III - Chapters 4, 6
Syllabus
• Architectural Issues, Switch logic
• Logic gates and other complex gates (chapter 6)
• Alternate gate circuits (chapter 6)
• Time delays
• Driving large capacitive loads
• Wiring capacitance
• Fan-in, Fan-out
• Choice of layers

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 Introduction
Objectives
• Discuss about common logic gates and
Logic gates using nMOS, CMOS, BiCMOS

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 Architectural issues
Architectural issues
• Need logical and systematic approach for all
design process
• Design time increases exponentially
with complexity
Example:
• Circuit with 500 transistors
- Takes 2 Engineer-months to design
• Circuit with 500,000 transistors
- Takes 2000 Engineer-months to design
or 170 Engineer-years for designing
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 Architectural issues
Guidelines for VLSI system design
1. Define the requirements
2. Partition overall architecture
into appropriate subsystems
3. Consider communication paths carefully
in order to develop sensible
interrelationships between subsystems
4. Draw a floor plan of how the system is
to map on to the silicon
(repeat 2, 3, and 4, if necessary)

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 Architectural issues
Guidelines for VLSI system design
5. Aim for regular structures to enable
replication
6. Draw suitable (stick or symbolic) diagrams
of the leaf-cells of the subsystems
7. Convert each cell to a layout
8. Carefully and thoroughly carry out
a design rule check on each cell
9. Simulate the performance of
each cell/subsystem

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 Architectural issues
Important steps in design
1. Partitioning of the system into subsystems
with minimum interdependence and
complexity of interconnection.
2. Design simplification within subsystems
to adapt cellular design concept.
This allows the system to be composed of
Few standard cells and replicate to form
highly regular structures.

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 Switch Logic

• Based on pass transistors or transmission gates

• Design is fast for small arrays and draws
no static current from power supply
• Hence Small power dissipation
• Switch (pass transistor) logic Similar to logic
arrays based on relay contacts
• This allows the designer considerable Freedom
to implement architectural features when
compared to bipolar logic-based designs

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 Switch Logic
Switch Logic arrangements

Fig. 6.1 Some switch logic arrangements

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 Switch Logic
Switch Logic arrangements

Fig. 6.1 Some switch logic arrangements

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 Switch Logic
Switch Logic arrangements

Fig. 6.1 Some switch logic arrangements

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 Switch Logic
Switches or switch logic formed by using pass
transistors or transmission gate
Pass Transistors
• Simple nMOS or pMOS transistors
• loss of logic levels (due to undesirable
threshold voltage)
Transmission Gates
• nMOS and pMOS transistors in parallel
• Avoid loss of threshold voltage
• More area, but less On resistance
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 Switch Logic
Pass Transistors and Transmission Gates
Assume Vtp = 1 V
Strong 0
Weak 1

Strong 1
Weak 0

X = control signal
Fig. 6.2 Properties of pass transistors and
transmission gates
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 Switch Logic
Pass Transistors and Transmission Gates

X = control signal

Fig. 6.2 Properties of pass transistors and

transmission gates
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 Switch Logic
Pass Transistors and Transmission Gates

Loss of logic level 1 if the gate of the pass transistor

is driven from another pass transistor
Fig. 6.2 Properties of pass transistors and
transmission gates
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 Switch Logic
For nMOS switch logic
• No pass transistor gate to be driven
through one or more pass transistors
Output vol tage of the first pass transisto r
Vout = VDD − Vtp
Output vol tage of the second pass transisto r
Vout = VDD − 2Vtp

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 Logic Gate and other complex
gates
-The gate of a MOS transistor controls the flow of
current between the source and drain.
-Logic Gates and other complex logic gates can be
implemented by using MOS transistors(like
nMOS, CMOS, BiCMOS)
Basic Logic gates:
• Inverter
• OR
• AND

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 Gate Logic
Gate logic
• Based on inverter circuits
• Nand, Nor, And, Or gates
available
• Inverters :
To complement and restore logic levels
that have been degraded
(due to pass transistors)

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 Gate Logic
Inverters – Circuit diagrams

Fig. 6.3 nMOS, CMOS, and BiCMOS inverters

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 Gate Logic
Inverters – Logic symbols

Fig. 6.3 nMOS, CMOS, and BiCMOS inverters

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 Gate Logic
Inverters – Stick and symbolic
diagrams

Fig. 6.3 nMOS, CMOS, and BiCMOS inverters

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 Gate Logic
For desired p.u to p.d ratio,several possibilities there,two
of which are
(1)

Zpd = Lpd/Wpd = 1
,Assume (VDD)V= 5 V

Fig. 6.4 8:1 nMOS inverter

(min. size pd)
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 Gate Logic
(2)

Zpd = Lpd/Wpd = 1/2

, Assume V = 5 V

Fig. 6.5 An alternative 8:1

nMOS inverter
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 Gate Logic
Gate Logic - Important points from fig(6.4 & 6.5)
• Zpu : Zpd ratio or L:W ratio for each transistor
shown in diagram
• Effect of different approaches on Power
dissipation Pd and area
• Different resistance and capacitance values

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 Two-input NAND gates
Two input NAND gates - nMOS
• nMOS NAND gate - Area increases
p.d transistors added, p.u length increased
to maintain overall ratio
• Delay increased proportional to
the number of inputs  Nand = n  inv
• Rise time dependent on the number of
actual inputs on which 1 → 0 transition takes
place
• NAND gates only when absolutely necessary,
number of inputs limited (to 3)
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 Two-input NAND gates
Two input NAND gates - CMOS
• No restrictions
• Increased fall time due to
number of pull-down transistors
• Adjustment of transistor geometry needed to
keep the transfer characteristic symmetric about
VDD/2
Two input NAND gates - BiCMOS
• Complex geometry used
• Useful for large fan-out or
for driving high Capacitance loads
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 Two-input NAND gates
Two-input NAND gates

Fig. 6.6 (a)-(c) nMOS, CMOS, and BiCMOS

2-input NAND gates
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 Two-input NAND gates
Two-input NAND gates

Fig. 6.6 (a)-(c) nMOS, CMOS, and BiCMOS 2-input NAND gates
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 Two-input NAND gates
BiCMOS Two-input NAND gate

Fig. 6.6(d) A BiCMOS two-input NAND gate

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 Two-input NAND gates
BiCMOS Two-input NAND gate

Symbolic diagram Mask layout

Color Plate 8(a) A BiCMOS two-input NAND gate
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 Two-input NAND gates
nMOS NAND ratio

Fig. 6.7 nMOS NAND ratio determination

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 Two-input NAND gates
To determine L : W ratio for
nMOS NAND gate with n inputs
Output vol tage Vout  Vt = 0.2VDD
VDD  nZ pd
 0.2VDD
nZ pd + Z pu
nZ pd
Boundary condition = 0.2
nZ pd + Z pu
Z pu 4
nMOS NAND ratio = =
nZ pd 1
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 Two-input NOR gates
Two input NOR gates - nMOS
• Two parallel transistors in pull-down
provide path from pull-up transistor to
GND
• Each leg must have the same ratio as inverter
• Area is reasonable as pull-up transistor
is not affected

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 Two-input NOR gates
Two input NOR gates - CMOS
• Pull-down n-transistors in parallel
• Pull-up p-transistors in series
Resistance of pull-up side is increased
• Rise-time, fall-time asymmetry increased
• For > 2 inputs,
adjustment of L:W ratios needed
Two input NOR gates - BiCMOS
• Complex geometry used
• Useful for large fan-out or for driving high C
loads Unit III p1 34
26 October 2022 VLSI Design
 Two-input NOR gates
Two-input NOR gates

Fig. 6.8(a), (b) Two-input NOR gates

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 Two-input NOR gates
Two-input NOR gates

Fig. 6.8(c) Two-input NOR gates

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 Two-input NOR gates
BiCMOS Two-input NOR
gate

Fig. 6.8(d) BiCMOS Two-input NOR gate

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 Two-input NOR gates
BiCMOS Two-input NOR gates

Symbolic diagram Mask layout

Color Plate 8(b) A BiCMOS two-input NOR gate
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 NOR gates
nMOS NOR gate

Stick diagram Mask layout

Color Plate 9(a) nMOS three-input NOR gate
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 NOR gates
CMOS NOR gate

Stick diagram Mask layout

Color Plate 9(b) p-well CMOS two-input NOR gate
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 Alternate gate circuits

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 Alternate gate circuits
1. Pseudo nMOS logic
• In nMOS logic, n-channel depletion mode pull-up
transistor replaced with pMOS, gate connected to VSS.

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 Alternate gate circuits
Pseudo nMOS logic

Depletion mode
nMOS pull-up
is replaced by
pMOS transistor

Fig. Pseudo-nMOS NAND gate

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 Alternate gate circuits
Pseudo-nMOS inverter
•For a pseudo nMOS
inverter driven by another
pseudo nMOS inverter
Zpu : Zpd ratio = 3:1

Fig. 6.10 Pseudo-nMOS inverter

when driven from a similar inverter
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 Pseudo nMOS logic

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 Pseudo nMOS logic

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Dynamic CMOS logic

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 Dynamic CMOS logic

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 Alternate gate circuits
Dynamic CMOS logic
• Actual logic is implemented using nMOS
• pMOS used to charge output capacitance to VDD
during OFF period of clock signal
• Inputs are applied to n-block
• State is evaluated during clock ON period
when bottom n-transistor is ON
• Output value dependent on the input values
If all inputs are 1s, then all nMOS transistors ON
Output Z = 0
If any or all of the inputs are 0, Output =1

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 Alternate gate circuits
Dynamic CMOS logic - 3-input NAND
gate

Clock 

Dynamic CMOS logic - 3-input NAND gate

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 Dynamic CMOS logic

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 Dynamic CMOS logic

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 Alternate gate circuits
Clocked CMOS (C2MOS)
logic
2-input
Clock  Inverter
NOR gate
Clock 
Clock 
Clock 

Fig. 6.12 Clocked CMOS (C2MOS) logic

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 Alternate gate circuits
Clocked CMOS (C2MOS) logic
• Logic is implemented
using both p and n transistors
• Pull-up : p-block
• Pull-down : n-block
• Logic evaluated
only during the ON period of the clock
• Clocked inverter also included
• Slower rise and fall times due to
extra transistors in series.

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 Alternate gate circuits
CMOS domino logic

Clock 

Fig. 6.13 CMOS domino logic

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 Alternate gate circuits
CMOS domino logic
• Extension of dynamic CMOS logic
• Uses single phase clock
• Static CMOS buffer for each gate
• Smaller area than conventional CMOS Logic
• Higher operating speeds
due to smaller parasitic capacitance
• Operation free of glitches as each gate can
make only one 1 to 0 transition
• Non-inverting structures possible
• Charge distribution may be a problem
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 CMOS domino logic

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 CMOS domino logic

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 Alternate gate circuits
n-p CMOS logic
• Logic blocks are alternately n and p
in cascaded structure
• Output of n block precharged to 1 during 
and evaluated during  .
• Output of p-block is precharged to 0 during 
and evaluated during  .
• Precharge and evaluate transistors fed from
clock  and  alternately
• Functions of top and bottom transistors
alternate between precharge and evaluate.
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 Alternate gate circuits
n-p CMOS logic

Clock 
Clock  Clock 

Fig. 6.14 n-p CMOS logic

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 Text Books

1. Essentials of VLSI circuits and

Systems, Kamran Eshraghian, Douglas
A. Pucknell, PHI, 2005 edition
2. VLSI Design, K. Lal Kishore, V.S.V.
Prabhakar, I.K. International, 2009.
3. CMOS VLSI Design – A circuit and
systems perspective, Neil H. Weste
and David Harris, Ayan Banerjee,
Pearson, 2009.

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 References

1. CMOS logic circuit design, John P. Uyemura,

Springer, 2007.
2. Modern VLSI Design, Wayne Wolf, Pearson
Education, 3rd edition, 1997.
3. VLSI Design, A. Albert Raj, Latha, PHI, 2008.
4. Introduction to VLSI – Mead and Conway,
BS Publications, 2010.
5. VLSI design, M. Michael Vai, CRC Press,
2009.

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