Digital Electronics Laboratory Manual (ECE211) : Dr. Pradyut Kumar Sanki

Digital Electronics
Laboratory Manual
(ECE211)
Dr. Pradyut Kumar Sanki
Assistant Professor
Dept. of ECE
SRM University AP, Amaravati.
October 21, 2019

Index
DESIGN OF ARITHMETIC LOGIC UNIT Data Transfer through Multiplexer/De-

(ALU), 29–33 multiplexer, 27–29
Design of programmable ALU, 29– Design & verification of De- Multi-
31 plexer, 26–27
Realization of 4-bit ALU, 31–33 Design & Verification of Multiplexer,
DESIGN OF ASYNCHRONOUS COUNTER, 22–25
45–46 Design of Full Adder/subtractor us-
DESIGN OF CODE CONVERTERS, 12– ing Multiplexer, 26
17 Design of Half Adder/subtractor us-
Design of 4-bit Binary to Gray Code ing Multiplexer, 25
Converter, 12–15 DESIGN OF MAGNITUDE COMPARA-
To design and set up the circuits TOR, 39–42
of a 4-bit Gray to Binary Code Design of magnitude comparator us-
Converter, 15–17 ing IC, 42
DESIGN OF COMBINATIONAL LOGIC Design of Magnitude comparator us-
CIRCUITS, 17–21 ing logic gates, 39–42
Design of Adder, 17–18 DESIGN OF MEMORY, 51–53
DESIGN OF SHIFT REGISTER, 50–51
Design of Subtractor, 18–19
DESIGN SYNCHRONOUS COUNTER,
Parallel Adder/Subtractor, 19–21
47–50
DESIGN OF ENCODER AND DECODER,
Design of MOD16 Synchronous Counter,
33–38
47–48
Design of BCD to SSD, 37–38
Design of MOD8 Synchronous Counter,
To design and set up the circuits of
48–50
Encoder & Decoder, 33–36
To design set up the connections & FAMILIARIZATION OF LOGIC GATES
verify the Encoder & Decoder & DIGITAL ICS, 6–12
ICS, 36–37 FSM BASED DESIGN PROJECT, 53
DESIGN OF LATCHES & FLIP-FLOPS,
43–45
Design & verification of SR, JK, D,
T & Master-Slave JK Flip-flops,
43–45
DESIGN OF LOGIC CIRCUITS USING
MULTIPLEXER & DEMULTIPLEXER,
22–29
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Contents
Contents
Index 3
1 FAMILIARIZATION OF LOGIC GATES & DIGITAL ICS . . . . . . . . . 6
2 DESIGN OF CODE CONVERTERS . . . . . . . . . . . . . . . . . . . . . . 12
2.1 Design of 4-bit Binary to Gray Code Converter . . . . . . . . . . 12
2.2 To design and set up the circuits of a 4-bit Gray to Binary Code
Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3 DESIGN OF COMBINATIONAL LOGIC CIRCUITS . . . . . . . . . . . . 17
3.1 Design of Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 Design of Subtractor . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3 Parallel Adder/Subtractor . . . . . . . . . . . . . . . . . . . . . . . 19
4 DESIGN OF LOGIC CIRCUITS USING MULTIPLEXER & DEMULTI-
PLEXER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1 Design & Verification of Multiplexer . . . . . . . . . . . . . . . . . 22
4.2 Design of Half Adder/subtractor using Multiplexer . . . . . . . 25
4.3 Design of Full Adder/subtractor using Multiplexer . . . . . . . . 26
4.4 Design & verification of De- Multiplexer . . . . . . . . . . . . . . 26
4.5 Data Transfer through Multiplexer/De-multiplexer . . . . . . . . 27
5 DESIGN OF ARITHMETIC LOGIC UNIT (ALU) . . . . . . . . . . . . . . 29
5.1 Design of programmable ALU . . . . . . . . . . . . . . . . . . . . 29
5.2 Realization of 4-bit ALU . . . . . . . . . . . . . . . . . . . . . . . . 31
6 DESIGN OF ENCODER AND DECODER . . . . . . . . . . . . . . . . . . 33
6.1 To design and set up the circuits of Encoder & Decoder . . . . . 33
6.2 To design set up the connections & verify the Encoder & Decoder
ICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.3 Design of BCD to SSD . . . . . . . . . . . . . . . . . . . . . . . . . 37
7 DESIGN OF MAGNITUDE COMPARATOR . . . . . . . . . . . . . . . . 39
7.1 Design of Magnitude comparator using logic gates . . . . . . . . 39
7.2 Design of magnitude comparator using IC . . . . . . . . . . . . . 42
8 DESIGN OF LATCHES & FLIP-FLOPS . . . . . . . . . . . . . . . . . . . 43
8.1 Design & verification of SR, JK, D, T & Master-Slave JK Flip-flops 43
9 DESIGN OF ASYNCHRONOUS COUNTER . . . . . . . . . . . . . . . . 45
10 DESIGN SYNCHRONOUS COUNTER . . . . . . . . . . . . . . . . . . . 47
10.1 Design of MOD16 Synchronous Counter . . . . . . . . . . . . . . 47
10.2 Design of MOD8 Synchronous Counter . . . . . . . . . . . . . . . 48
11 DESIGN OF SHIFT REGISTER . . . . . . . . . . . . . . . . . . . . . . . . 50
12 DESIGN OF MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
13 FSM BASED DESIGN PROJECT . . . . . . . . . . . . . . . . . . . . . . . 53
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Contents
1 FAMILIARIZATION OF LOGIC GATES & DIGITAL ICS
AIM: To familiarize with logic gate IC packages and to verify the truth tables of the
logic gates. Also to familiarize with the Digital Test Kit.
Components Required: Following components in Table 7 are required for perform-

ing the experiment.
Table 1: List of components
SL No. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE IC 7400 1
5. NOR GATE IC 7402 1
6. X-OR GATE IC 7486 1
7. NAND GATE 3 I/P IC 7410 1
8. DIGITAL TEST KIT - 1
9. PATCH CORD - As per Required
Theory:
Digital Test Kit: As digital circuits are required to handle just two levels of voltage
to represent the two possible values of any binary variable, functional testing of simple
digital circuits can be conveniently carried out by applying each input (binary) variable
through a switch and observing each output (binary) variable on a simple LED display.
Note the number of Input Switches and the number of LED Displays provided in the
kit you are using. Each Input Pin is either at LOW (Ground = 0V) level or at a HIGH
(VCC = 5V.) level depending on whether the corresponding switch is OFF or ON. Note
how the LED glows when the corresponding Display Input Pin is at a HIGH level and
when it is at a LOW level.
All circuits we will study in this course will need a 5V DC power supply, and this has
been provided in the Digital Test Kit. The Clock Generator provides different choices
of the frequency of a continuously running clock. The circuit to be studied will have
to be assembled on the breadboard. Figure 1 shows the schematic of the breadboard.
It has 128 vertical strips, 64 on each side of the horizontal divider in the middle, each
strip consisting of 5 spring-loaded tie-points internally connected to one another. Each
connection among the circuit components is made with the help of tie-points connected
together on the same strip. The breadboard also has 8 horizontal strips, four on the
top side and 4 on the bottom side, each having 25 tie-points. These strips are generally
used for making power supply connections.
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Contents
Figure 1: Schematic of Breadboard.
Logic Gates & Logic Families: Logic gates: In digital electronics, a gate is logic
circuits with one output and one or inputs. Logic gates are available as integrated
circuits. AND gate: the AND gate performs logical multiplication, more commonly
known as And operation. The AND gate output will be in high state only when all
the inputs are in high state. 7408 is a Quad 2 input AND gate. OR gate: It performs
logical addition. Its output become high if any of the inputs is in logic high. 7432
is a Quad 2 input OR gate. NOT gate: It performs basic logic function for inversion
or complementation. The purpose of the inverter is to change one logic level to the
opposite level. IC 7404 is a Hex inverter. NAND gate: A NOT gate following an And
gate is called NOT-AND or NAND gate.Its output will be low if all the inputs are in
high state. 7400 IC is Quad two input NAND gate. NOR gate: A NOT gate following
an OR gate is called NOT-OR or NOR gate. Its output will be in low state if any of its
input is in high state. 7402 is a Quad two input NOR gate. EXOR gate: Its output will
be high if and only if one input is in high state. 7486 is a Quad two input EXOR gate.
Two families of digital ICs are commonly used: the TTL 74LSxx series and the CMOS
CD 40xx series. Many of these ICs have 14 pins, and some have 16 or more. Two pins
are used for power supply connections. Thus 12 pins are available in a 14-pin IC for
gate inputs and outputs. A 2-input gate requires three pins per gate (two for inputs and
one output), and so ICs that implement 2-input logic functions generally have 4 gates
per IC. TTL ICs require a fixed DC power supply voltage VCC having the nominal
value of 5V and a tolerance of 5%, i.e. 4.75V ≤ VCC ≤ 5.25V; a voltage outside this
range can damage the IC. Most CMOS ICs can work with 3V ≤ VCC ≤ 15V.
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Contents
Figure 2: Digital Logic Gates
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Figure 3: Pin Connections of TTL 74XX series Quad 2-input Gates
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Contents
Results: All the gates are verified with their truth table.
Conclusions: What is problem faced by the you while performing the lab. How
problems are rectified? Is the execution done by first attempt? If not write reason.
Finally, is the lab successfully executed or the inputs/outputs verified from the truth
table or excitation table?
Table 2: Part Identification
Identification
HD 54 LS 10
SN 74 HCT 2G 04 N
Package Designation
Device Number
Gates Count
Technology Indicator
Specs/Temp Indicator
Manufacturer Prefix
Specs/Temp Indicator: 75 - Interface device

74 - Commercial Grade
64 - Industrial
54 - Military/Airspace Grade
Technology Indicator: Some of more popular ones you’ll encounter are:

None - When no indicator is found, this implies it’s the original TTL Bipolar
S - Schottky logic.
LS - Low-power Schottky. Same as L series but with reduced power consumption and
switching speed.
CMOS: C - CMOS
AC / ACT - Advanced CMOS (T version for TTL-compatible inputs)
HC / HCT - High-speed CMOS, similar to LS (T version for TTL-compatible inputs)
AHC / AHCT - Advanced high-speed CMOS (T version for TTL-compatible inputs)
LV / LVC’ - Low-Voltage CMOS
BiCMOS: BCT - BiCMOS

ABT - Advanced BiCMOS
Gates Count (surface mount ICs only) 1G = 1, 2G = 2, 3G = 3
Device Number:
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Contents
Table 3: Digital IC Series
Digital ICs 1-I/P 2-I/Ps 3-I/Ps 4-I/Ps 8-I/Ps

TTL NOT NAND NOR AND OR XOR NAND AND NOR NAND AND NOR NAND
74 04 00 02 08 32 86 10 11 27 21 25 20 30
Package Designation: D - DIP (Dual Inline Package), DB - SSOP (Shrink Small-

Outline Package), FK - LCCC (Leaded Ceramic Chip Carrier), J - CDIP (Ceramic Dual
Inline Package), N - Plastic DIP, NS - SOP (), PS - SOP (Small-Outline Package), T - Flat
package and W - CFP (Ceramic Flat Package).
Example Chip is labeled DM74LS221N:

DM - prefix - made by Fairchild or National Semiconductor, but given the F logo, we
can determine it’s Fairchild.
74 - series - commercial grade chip
LS - techno - Low-power Schottky.
221 - device - Dual non-retriggerable monostable multivibrator with reset
N - package - standard plastic DIP
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Contents
2 DESIGN OF CODE CONVERTERS
2.1 Design of 4-bit Binary to Gray Code Converter
AIM: To design and set up the circuits of a 4-bit Binary to Gray Code Converter
Components Required: Digital Test Kit, ICs 7486.
THEORY: To convert a binary number to corresponding Gray code, the following

rules are applied.
Step 1: The MSB in the Gray code is the same as the corresponding bit in a binary
number.
Step 2: Going from left to right, add each adjacent pair of binary digits to get the next
Gray code digit. Disregard carries. As the first step to design a binary to Gray
Code Converter, write the truth table ?? with binary numbers B8B4B2B1 and
corresponding gray code numbers G3G2G1G0. Set up a circuit realizing the
simplified logic expressions obtained using K-Maps for G0, G1, G2 and G3 as the
functions of B8, B4, B2 and B1.
Table 4: Truth Table for Binay to Gray Conversion
Decimal Binary Inputs Gray Outputs

Number B8 B4 B2 B1 G3 G2 G1 G0
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 0 1 0
4 0 1 0 0 0 1 1 0
5 0 1 0 1 0 1 1 1
6 0 1 1 0 0 1 0 1
7 0 1 1 1 0 1 0 0
8 1 0 0 0 1 1 0 0
9 1 0 0 1 1 1 0 1
10 1 0 1 0 1 1 1 1
11 1 0 1 1 1 1 1 0
12 1 1 0 0 1 0 1 0
13 1 1 0 1 1 0 1 1
14 1 1 1 0 1 0 0 1
15 1 1 1 1 1 0 0 0
For G3 & G2:
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G3 = B8 G2 = B8 ⊕ B4 (1)
B2 B1 B2 B1
00 01 11 10 00 01 11 10
00 0 0 0 0 00 0 0 0 0
01 0 0 0 0 01 1 1 1 1
B8 B4 B8 B4
11 1 1 1 1 11 0 0 0 0
10 1 1 1 1 10 1 1 1 1
For G1 & G0:
G1 = B4 ⊕ B2 G0 = B2 ⊕ B1 (2)
B2 B1 B2 B1
00 01 11 10 00 01 11 10
00 0 0 1 1 00 0 1 0 1
01 1 1 0 0 01 0 1 0 1
B8 B4 B8 B4
11 1 1 0 0 11 0 1 0 1
10 0 0 1 1 10 0 1 0 1
Circuit diagram:
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(a) Binary to Gray Converter (b) Gray to Binary Converter
Figure 4: Circuit diagram for Binary to Gray and Gray to Binary converter
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Contents
2.2 To design and set up the circuits of a 4-bit Gray to

Binary Code Converter
AIM: Design of 4-bit Gray to Binary Code Converter
Components Required: Digital Test Kit, ICs 7486.
THEORY: To convert from Gray code to binary, the following rules are applied.
Step 1: The most significant digit in the binary number is the same as the corresponding
digit in the Gray code.
Step 2: Add each binary digit generated to the Gray code digit in the next adjacent
position. Disregard carries.
To design the Gray to Binary code converter, write the truth table and get simplified
expressions using K-Maps for each binary bits as a function of Gray code bits. Each
Gray code number differs from the preceding number by a single bit.
Table 5: Truth Table for Gray to Binay Conversion
Decimal Gray Inputs Binary Outputs

Number G3 G2 G1 G0 B8 B4 B2 B1
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
3 0 0 1 1 0 0 1 0
2 0 0 1 0 0 0 1 1
6 0 1 1 0 0 1 0 0
7 0 1 1 1 0 1 0 1
5 0 1 0 1 0 1 1 0
4 0 1 0 0 0 1 1 1
12 1 1 0 0 1 0 0 0
13 1 1 0 1 1 0 0 1
15 1 1 1 1 1 0 1 0
14 1 1 1 0 1 0 1 1
10 1 0 1 0 1 1 0 0
11 1 0 1 1 1 1 0 1
9 1 0 0 1 1 1 1 0
8 1 0 0 0 1 1 1 1
For B8 & B4:
B8 = G3 B4 = G3 ⊕ G2 (3)
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Contents
X1 X0 X1 X0
00 01 11 10 00 01 11 10
00 0 0 0 0 00 0 0 0 0
01 0 0 0 0 01 1 1 1 1
X3 X2 X3 X2
11 1 1 1 1 11 0 0 0 0
10 1 1 1 1 10 1 1 1 1
For B2 & B1:
B2 = G3 ⊕ G2 ⊕ G1 B1 = G3 ⊕ G2 ⊕ G1 ⊕ G0 (4)
X1 X0 X1 X0
00 01 11 10 00 01 11 10
00 0 0 1 1 00 0 1 0 1
01 1 1 0 0 01 1 0 1 0
X3 X2 X3 X2
11 0 0 1 1 11 0 1 0 1
10 1 1 0 0 10 1 0 1 0
Results: Both the circuits have verified with the truth table.
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Contents
3 DESIGN OF COMBINATIONAL LOGIC CIRCUITS
3.1 Design of Adder
AIM: To design and set up the circuits of a Half Adder (HA) & Full Adder (FA).
Components Required: Digital Test Kit, ICs - 7486, 7432, 7408, 7400, Connecting
patch chords.
Theory: A binary Full Adder adds two bits A and B along with a carry in C to
generate sum (Sout) and carry (Cout) bits as output. The first step to achieve this is to
make a binary Half Adder, which adds two binary inputs A and B to give a sum S1
and a carry C1 according to the following Boolean expressions for the outputs S1 and
C1.
S1 = A · B + A · B = A ⊕ B (5)
Another Half Adder is then used to generate the final Sout by adding the third
binary input C to the S1 bit generated by the first Half Adder (HA1).
Sout = S1 ⊕ C (6)
The carry bit generated by this Half Adder is given by
C2 = S1 · C (7)
Write down the complete truth table of a Full Adder, including columns for the
intermediate outputs S1, C1 and C2. Find out the logic for generating the final Cout
output from C1 and C2. As XOR and AND gates are going to be used for the Half
Adders, try to obtain a logic for Cout using the same type of gates, so that the complete
realisation of the Full Adder is possible without necessitating a third IC. Set up the
circuit of a Half Adder using an XOR gate and an AND gate. Apply the inputs A and
B from two input switches and observe the outputs S1 and C1 on two LED displays
for all combinations of the inputs. Tabulate these values and verify the operation of
the Half Adder. Set up another Half Adder using another XOR and another AND
gate out of the same ICs used in step 1, and connect the C input and the S1 output
generated by the first Half Adder as its inputs to generate the final Sout output and
the C2 output. Generate the final Cout from the intermediate carry outputs C1 and
C2, using the unused gates in the XOR and AND ICs deployed so far. Verify the truth
table experimentally by applying the inputs A, B and C through three input switches
and displaying the S1, C1, C2, Sout and Cout outputs.
Circuit diagram:
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Contents
Table 6: Truth Table for Half Adder
Inputs Outputs
Dec
A B S1 C1
0 0 0 0 0
1 0 1 1 0
2 1 0 1 0
3 1 1 0 1
Table 7: Truth Table for Full Adder
Outputs
Inputs
Dec HA1 HA2
Cout
A B Cin S1 C1 Sout C2
0 0 0 0 0 0 0 0 0
1 0 0 1 0 0 1 0 0
2 0 1 0 1 0 1 0 0
3 0 1 1 1 0 0 1 1
4 1 0 0 1 0 1 0 0
5 1 0 1 1 0 0 1 1
6 1 1 0 0 1 0 0 1
7 1 1 1 0 1 1 0 1
3.2 Design of Subtractor
AIM: To design and set up the circuits of a Half Subtractor (HS) & Full Subtractor
(FS).
Components Required: Digital Test Kit, ICs - 7486, 7432, 7408, 7400, Connecting
patch chords.
Theory: A binary Full Subtractor subtracts the Subtrahend bit Y and a Borrow-
in bit Z from the Minuend bit X to generate Borrow (Bout) and Difference (Dout) bits
as output. Obtain the logic for performing subtraction and modify the Full Adder
circuit appropriately for performing subtraction. Verify the truth table experimentally
by applying the inputs X, Y and Z through three input switches and displaying the
Bout and Dout output bits.
Circuit diagram:
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Contents
Figure 5: Circuit diagram of (a) Half Adder & (b) Full Adder
Table 8: Truth Table for Half Subtractor
Inputs Outputs
Dec
A B D1 B1
0 0 0 0 0
1 0 1 1 1
2 1 0 1 0
3 1 1 0 0
3.3 Parallel Adder/Subtractor
AIM: To design and set up the circuit of a 4-bit Binary Adder/Subtractor using
IC 7483
Components Required: Digital Test Kit, IC - 7483, Connecting patch chords.
Theory: 7483 is a TTL IC with 4 full adders in it by which we can add two 4
bit numbers. In a 4 bit adder A3A2A1A0 and B3B2B1B0 are the inputs and Cout and
S3S2S1S0 are the outputs. CARRYIN pin is grounded for 4 bit adder. This is also called
a nibble adder.
4 bit add/subtract circuit:: The circuit is setup as shown in Fig. 9. To add the
nibbles, SUB is to be made 0. To subtract B3B2B1B0 from A3A2A1A0 Sub is to made 1.
XOR gates function as controlled invertors. When SUB=1, B3B2B1B0 is complemented
.Now A3A2A1A0, complemented version of B3B2B1B0 and 1 at Cin pin are added
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Table 9: Truth Table for Full Subtractor
Outputs
Inputs
Dec HS1 HS2
Bout
X Y Z D1 B1 Dout B2
0 0 0 0 0 0 0 0 0
1 0 0 1 0 0 1 1 1
2 0 1 0 1 1 1 0 1
3 0 1 1 1 1 0 0 1
4 1 0 0 1 0 1 0 0
5 1 0 1 1 0 0 0 0
6 1 1 0 0 0 0 0 0
7 1 1 1 0 0 1 1 1
6 1 1 0 0 1 0 0 1
7 1 1 1 0 1 1 0 1
Figure 6: Circuit diagram of (a) Half Subtractor & (b) Full Subtractor
together. Cout is ignored. Thus the 2’s complement of subtractend is added with the
minuend. It minuend is less than subtractend; the obtained output will be the 2’s
complement of difference. In this part, we will study the performance of the Four-bit
Adder 74LS83 capable of adding two 4-bit operands with Carry. This is an IC chip
having a combinational function more complex than simple logic gates integrated on
a single chip at the Medium Scale Integration (MSI) level. The operation of the 4-bit
adder is straightforward: the two 4-bit inputs A4A3A2A1 and B4B3B2B1 (A1, B1 are
the least significant bits and A4, B4 are the most significant bits) are added, along with
the carry input C0 (coming from the lower significant set of bits, if any), according to
binary arithmetic ∑ 1 − ∑ 4 is the 4-bit sum output and C4 is the carry output, if any.
Apply at least 16 different sets of inputs to the 4-bit Adder, using the input switches
for providing the necessary inputs, with a fixed (0/1) input to the carry input CYI by
connecting it to Gnd/VCC, and observe the five outputs on the LED displays. Tabulate
your observations and verify the results by calculating the sum and carry outputs.
Pin Diagram: The pin connections of this IC is given in Fig. 8.
Circuit Diagram:
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(a) Full Adder (b) Full Subtractor
Figure 7: Circuit diagram for Full Adder & Full Subtractor
Figure 8: Pin diagram of IC-7483
Results: Addition & subtraction of two 4-bit numbers are verified.
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Figure 9: Circuit diagram of 4-bit Adder/Subtractor
4 DESIGN OF LOGIC CIRCUITS USING MULTIPLEXER &

DEMULTIPLEXER
4.1 Design & Verification of Multiplexer
AIM: (1) To set up a 4 x 1 multiplexer using gates (2) Verification of 2 x 1, 4 x 1 &

8 x 1 multiplexers using ICs (3) Design Adder/Subtractor using Mux
Components Required: Digital Test Kit, ICs 7400, 7410, 74153, 74151, 74148 &
Connecting patch chords.
Theory: A multiplexer is a combinational circuit that selects binary information

from one of many input lines and directs it to a single output line. The selection of
a particular input line is controlled by a set of selection lines. Normally, there are
2n input lines and n selection lines whose bit combinations determine which input is
selected. A two-to-one-line multiplexer connects one of two 1-bit sources to a common
destination, as shown in Fig.11. The circuit has two data input lines, one output line,
and one selection line S . When S = 0, the upper AND gate is enabled and I0 has a path
to the output. When S = 1, the lower AND gate is enabled and I1 has a path to the
output. The multiplexer acts like an electronic switch that selects one of two sources.
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S1 S1 S0 Y
0 0 0 D0
S1 S0 Y 0 0 1 D1
S Y 0 0 I0 0 1 0 D2
0 I0 0 1 I1 0 1 1 D3
1 I1 1 0 I2 1 0 0 D4
1 1 I3 1 0 1 D5
1 1 0 D6
1 1 1 D7
Table 10: Truth Table for 2:1, 4:1 & 8:1 Muxes
A four-to-one-line multiplexer is shown in Fig. 11. Each of the four inputs,I0 through
I3 , is applied to one input of an AND gate. Selection lines S1 and S0 are decoded to
select a particular AND gate. The outputs of the AND gates are applied to a single OR
gate that provides the one-line output. The function table lists the input that is passed
to the output for each combination of the binary selection values. To demonstrate the
operation of the circuit, consider the case when S1 S0 = 10. The AND gate associated
with input I2 has two of its inputs equal to 1 and the third input connected to I2 . The
other three AND gates have at least one input equal to 0, which makes their outputs
equal to 0. The output of the OR gate is now equal to the value of I2 , providing a path
from the selected input to the output.It is also called Data Selector. Various multiplexer
IC’s are available with 2, 4, & 8 inputs and 1 output. They have control inputs to carry
out this operation. 74148 – It is a 2 line to 1 line multiplexer. It has one select inputs
and an active low strobe input. The data inputs are designated as D0 & D2. One bit
binary number at the data select inputs S select the data input to be directed to the
output. The strobe input is used to activate or deactivate the chip. 74153 – It is a 4
line to 1 line multiplexer. It has 2 select inputs and an active low strobe input. The
data inputs are designated as D0 through D3 .Two bit binary number at the data select
inputs S0 & S1 select the data input to be directed to the output. The strobe input is
used to activate or deactivate the chip. 74151 – It is a 8 line to 1 line multiplexer. It
has 3 select inputs and an active low strobe input. The data inputs are designated as
D0 through D7 .Three bit binary number at the data select inputs S0 , S1 & S2 select
the data input to be directed to the output. The strobe input is used to activate or
deactivate the chip.
Y = S.I0 + S.I1 . (8)
Y = S1 .S0 .I0 + S1 .S0 .I1 + S1 .S0 .I2 + S1 .S0 .I3 . (9)
Y = S2 .S1 .S0 .D0 + S2 .S1 .S0 .D1 + S2 .S1 .S0 .D2 + S2 .S1 .S0 .D3 + S2 .S1 .S0 .D4 +
(10)
S2 .S1 .S0 .D5 + S2 .S1 .S0 .D6 + S2 .S1 .S0 .D7 .
Pin diagram:
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Figure 10: Pin Diagram of Mux/Dmux
(a) (b)
Figure 11: Circuit Diagram of 2:1 & 4:1 Muxes
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Circuit diagram:
Results: Muxes are verified with their truth table.
4.2 Design of Half Adder/subtractor using Multiplexer
AIM: To design and set up the circuits of Half Adder/subtractor using Mux
Components Required: Digital Test Kit, ICs 74153, 7404 & Connecting patch
chords.
Theory:
(a) Halfl Adder (b) Half Subtractor
Figure 12: Circuit diagram for Half Adder & Half Subtractor using 4:1 Mux
Circuit diagram:
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4.3 Design of Full Adder/subtractor using Multiplexer
AIM: To design and set up the circuits of a Full Adder/subtractor using Mux
Components Required: Digital Test Kit, ICs 74153, 7404& Connecting patch
chords.
Theory:
(a) Full Adder (b) Full Subtractor
Figure 13: Circuit diagram for Full Adder & Full Subtractor using 4:1 MUX
Circuit diagram:
4.4 Design & verification of De- Multiplexer
AIM: To design and set up the circuits of an 4:1 De-multiplexer using logic gates
chords.
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Theory: A demultiplexer (or demux) is a device that takes a single input line
and routes it to one of several digital output lines. A demultiplexer of 2n̂ outputs has
n select lines, which are used to select which output line to send the input.
Figure 14: Circuit diagram of Demux using logic gates
Circuit diagram:
4.5 Data Transfer through Multiplexer/De-multiplexer
AIM: To verify serial transfer of data through multiplexed channel
chords.
Theory: Communication between Mux & Dmux is set up to study the serial
transfer of data.
Circuit diagram:
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Figure 15: Circuit diagram of Mux/Demux
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5 DESIGN OF ARITHMETIC LOGIC UNIT (ALU)
5.1 Design of programmable ALU
AIM: To design and set up the circuit of a programmable 1-bit ALU
Components Required: Digital Test Kit, ICs 7860, 7404, 74157, 74151 & Con-
necting patch chords.
Theory: An Arithmetic Logic Unit (ALU) capable of performing 8 Arith-

metic/Logic functions on 1-bit operands, as listed in Table 11, is be set up and tested.
Note that the first 4 functions are Logic functions generating 1-bit output Y0 , while the
last four are arithmetic functions generating 2-bit output Y1 Y0 . The circuit will consist
of two 8-input multiplexers (74LS151), one quad 2-input multiplexer (74LS157) and one
quad 2-input XOR gate (74LS86), all belonging to the TTL family. The pin connections
of these ICs are given in Fig. 16 below. X0 , X1 ,.....denote the data inputs and Q denotes
the data output for each multiplexer. S is the select input for a 2-input multiplexer and
S2, S1, S0 are the select inputs for an 8-input multiplexer. Thus for a 2-input multi-
plexer, Q = X0 if S = 0 and Q = X1 if S =1, while for an 8-input multiplexer, the output
Q = Xn (selected data input) if S2 S1 S0 = n (in binary code). EN is the (negative-logic)
output enable input, i.e. the corresponding multiplexer output is equal to the selected
data input only if EN = 0. Q-outputs of multiplexers are LOW if EN = 1.
Test the three given multiplexer chips one by one by connecting VCC and Gnd
appropriately and applying EN’ and appropriate inputs (X0 , X1 . . . .) from the Input
Switches. Verify the multiplexer function by tabulating the values of the Q output(s)
for all input combinations. Test all gates in the given quad XOR chip as done in
Experiment 1.
Step 1: The final ALU output bits Y0 and Y1 will be generated by the two 8-input multi-
plexers – referred to as MUX0 and MUX1 respectively. The required data, select
and output enable inputs of MUX0 and MUX1 are shown in Fig. 20. Note
that MUX0 is always enabled, while MUX1 is enabled only when F2 = 1, i.e.
for Arithmetic functions only. This is because Y1 is required only to provide
the CARRY/BORROW output for Arithmetic functions. Verify theoretically that
MUX0 and MUX1 do generate the outputs Y0 and Y1 as required by Table 11
Step 2: Note that though the two 8-input multiplexers MUX0 and MUX1 require 16
inputs, they involve only 6 distinct Boolean functions of A, B, C – A · B, A · B,
A + B, A + B, A ⊕ B and A ⊕ B ⊕ C. The first four terms are realised by four
2-input multiplexers as shown in Fig. ??. This implementation requires only
one chip, whereas any implementation using gates would need more, as a single
gate chip contains only one kind of gate (AND/OR/NAND/NOR). Assemble
the circuit given in Fig. ?? and verify its operation by actual tabulation of the
observed outputs for all combinations of values of A and B applied from two
Input Switches.
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Step 3: Connect the same A and B inputs to the inputs of one of the gates in the XOR
chip to generate A ⊕ B. Generate ( A ⊕ B) ⊕ C by applying ( A ⊕ B) and C to a
second XOR gate. Verify the logic of these two outputs for all combinations of
values of A, B and C.
Step 4: Assemble the complete circuit by adding two 74LS151 chips, used as MUX0 and
MUX1, to the circuit assembled so far, making connections to all the inputs of
MUX0 and MUX1 according to Fig. 17. Use a third gate from the XOR chip to
generate F2(= F2 ⊕ 1), providing the Enable input for MUX1.
Step 5: Apply all the combinations of the Function select inputs F2 F1 F0 one by one and
tabulate the observed outputs Y0 and Y1 for as many combinations of the data
inputs A, B, C as possible. Verify that the tabulated results conform to the ALU
functions given in Table 11.
Table 11: ALU Function Table
F2 F1 F0 ALU Function Y1 Y0
000 0 (Zero) - 0
001 A OR B - A+B
010 A AND B - A·B
011 A EXOR B - A⊕B
100 A PLUS B Carry Sum
101 A MINUS B Borrow Difference
110 A PLUS B PLUS C Carry Sum
111 A MINUS B MINUS C Borrow Difference
Truth Table:
Pin diagram:
Circuit diagram:
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Figure 16: Pin diagram of the ICs used
Figure 17: Boolean Functions of A and B using a quad 2-input Multiplexer
5.2 Realization of 4-bit ALU
AIM: To set up & verification of a 4-bit ALU
Components Required: Digital Test Kit, ICs 74181 & Connecting patch chords.
Theory: The Arithmetic Logic Unit (ALU) is the kernel block of a central
processing unit (CPU). The ALU can perform various arithmetic operations such as
parallel addition and subtraction. You have already learned the adder structure in
Experiment 4. The adder introduced in Experiment 4 is a one-bit adder. However, data
to be handled and processed in the ALU are often represented by several bits (usually
the width of a CPU word). Using the adder in Experiment 4 to process one bit at a
time would be too slow. Therefore the ALU is normally required to have the ability to
perform parallel addition and subtraction, so that addition and subtraction of several
bits can be performed simultaneously. Apart from speed, the ALU is also required to
have flexibility. The function of the ALU can be controlled or programmed to carry out
different arithmetic functions.
The ALU device used in this experiment is 74181 and its pin assignment is shown
in Fig.??. 74181 consists of four parallel full adder/subtractor circuits. Data applied
on the inputs Ai’s and Bi’s are processed and the sum or difference is available at the
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Figure 18: Input connections for MUX0 and MUX1
output in a parallel format. Selection of the desired ALU function is controlled by five
control lines, S0–S3, and mode, M in Fig. 19.
ALU Function Table:
Pin diagram:
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Figure 19: ALU function tablePin diagram of ALU
6 DESIGN OF ENCODER AND DECODER
6.1 To design and set up the circuits of Encoder & Decoder
AIM: To design & verify the operation of 8 to 3-line Encoder using logic gates
Components Required: Digital Test Kit, IC 7432, 7404, 7408 & Connecting patch
chords.
Theory:
Encoder: An encoder is a combinational circuit that converts binary information

from 2ninput lines to n number of output lines. The output lines, as an aggregate,
generate the binary code corresponding to the input value. Eight line to three line
or octal-to-binary encoder whose truth table is given in Table 12. It has eight inputs
(one for each of the octal digits) and three outputs that generate the corresponding
binary number. It is assumed that only one input has a value of 1 at any given time.
The encoder can be implemented with OR gates whose inputs are determined directly
from the truth table. Output z is equal to 1 when the input octal digit is 1, 3, 5, or 7.
Output y is 1 for octal digits 2, 3, 6, or 7, and output x is 1 for digits 4, 5, 6, or 7. These
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Figure 20: Pin diagram of ALU
conditions can be expressed by the following Boolean output functions:
z = D1 + D3 + D5 + D7.
y = D2 + D3 + D6 + D7. (11)
x = D4 + D5 + D6 + D7.
The encoder is implemented with three OR gates in 21.
Decoder: A decoder is a digital circuit that performs the inverse operation

of an encoder. Discrete quantities of information are represented in digital systems
by binary codes. A binary code of n bits is capable of representing up to 2n distinct
elements of coded information. A decoder is a combinational circuit that converts
binary information from n input lines to a maximum of 2n unique output lines. If
the n -bit coded information has unused combinations, the decoder may have fewer
than 2n outputs. The decoders presented here are called n -to- m -line decoders,
where m . . . 2n . Their purpose is to generate the 2n (or fewer) minterms of n input
variables. Each combination of inputs will assert a unique output. Consider the
three-to-eight-line decoder circuit of Fig. 22. The three inputs are decoded into eight
outputs, each representing one of the minterms of the three input variables. The three
inverters provide the complement of the inputs, and each one of the eight AND gates
generates one of the minterms. A particular application of this decoder is binary-
to-octal conversion. The input variables represent a binary number, and the outputs
represent the eight digits of a number in the octal number system. However, a three-to-
eight-line decoder can be used for decoding any three-bit code to provide eight outputs,
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Table 12: Truth Table of an Octal-to-Binary Encoder
Inputs Outputs
D0 D1 D2 D3 D4 D5 D6 D7 x y z
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
one for each element of the code. The operation of the decoder may be clarified by the
truth table listed in Table 13.
For each possible input combination, there are seven outputs that are equal to 0
and only one that is equal to 1. The output whose value is equal to 1 represents the
minterm equivalent of the binary number currently available in the input lines.
Figure 21: Circuit diagram of 8:3 Encoder using logic gates
Circuit diagram:
Results: All the inputs are matched with the outputs.
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Table 13: Truth Table of a Three-to-Eight-Line Decoder
Inputs Outputs
x y z D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
6.2 To design set up the connections & verify the Encoder

& Decoder ICS
AIM: To verify the operation of 8 to 3-line Encoder and 3 to 8 Decoder using IC

74138 and 74148
Components Required: Digital Test Kit, IC 74138, 74148, RESISTORs 100Ω,

LEDs, & Connecting patch chords.
Theory: An encoder has 2n̂ input lines and n output lines. The output lines
generate the binary code corresponding to the input value. The IC74148 is the 8:3
encoder which contains 8 inputs and 3 outputs. Decoder is a combinational circuit
which contains n input lines to 2n̂ output lines. The IC74138 is the 3:8 decoder which
contains three inputs and 8 outputs and also three enables out of them two are active
low and one is active high. Here, we are verifying the encoder decoder together using
the circuit diagram in Fig. 23.
Circuit diagram:
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Figure 22: Circuit diagram of 3:8 Decoder using logic gates
Results: All the inputs are matched with the outputs.
6.3 Design of BCD to SSD
AIM: To study the use of a Decoder Chip (IC 7447) to drive a LED Display
Components Required: Digital Test Kit, IC7447, RESISTOR 47Ω, SSD &
Connecting patch chords.
Theory: A seven-segment indicator is used to display any one of the decimal

digits 0 through 9. Usually, the decimal digit is available in BCD. A BCD-to-seven-
segment decoder accepts a decimal digit in BCD and generates the corresponding
seven-segment code. Figure 24 shows the connections necessary between the decoder
and the display. The 7447 IC is a BCD-to-seven-segment decoder/driver that has
four inputs for the BCD digit. Input D is the most significant and input A the least
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Figure 23: Circuit diagram of Encode Decoder
significant. The four-bit BCD digit is converted to a seven-segment code with outputs a
through g . The outputs of the 7447 are applied to the inputs of the 7730 (or equivalent)
seven-segment display. This IC contains the seven light-emitting diode (LED) segments
on top of the package. The input at pin 14 is the common anode ( CA ) for all the LEDs.
A 47Ω resistor toVC C is needed in order to supply the proper current to the selected
LED segments. Other equivalent seven-segment display ICs may have additional anode
terminals and may require different resistor values.
Circuit diagram:
Results: All the decimal values are noted and verified with the truth table.
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Figure 24: BCD-to-seven-segment decoder (7447) and seven-segment display

(7730)
7 DESIGN OF MAGNITUDE COMPARATOR
7.1 Design of Magnitude comparator using logic gates
AIM: Design of 2-bit magnitude comparator
Components Required: IC 7404, 7408, 7432, 7486 & Digital Test Kit.
Theory: Magnitude Comparator is a logical circuit, which compares two signals

A and B and generates three logical outputs, whether A > B, A = B, or A < B . IC 7485
is a high speed 4-bit Magnitude Comparator, which compares two 2-bit words. The A
= B Input must be held high for proper compare operation.
Truth Table:
For f(A<B) & f(A>B):
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Table 14: Truth Table for comparing two 2-bit numbers
Decimal Inputs Outputs

Number A1 A0 B1 B0 f(A< B) f(A=B) f(A> B)
0 0 0 0 0 0 1 0
1 0 0 0 1 1 0 0
2 0 0 1 0 1 0 0
3 0 0 1 1 1 0 0
4 0 1 0 0 0 0 1
5 0 1 0 1 0 1 0
6 0 1 1 0 1 0 0
7 0 1 1 1 1 0 0
8 1 0 0 0 0 0 1
9 1 0 0 1 0 0 1
10 1 0 1 0 0 1 0
11 1 0 1 1 1 0 0
12 1 1 0 0 0 0 1
13 1 1 0 1 0 0 1
14 1 1 1 0 0 0 1
15 1 1 1 1 0 1 0
B1 B0 B1 B0
00 01 11 10 00 01 11 10
00 0 1 1 1 00 0 0 0 0
01 0 0 1 1 01 1 0 0 0
A1 A0 A1 A0
11 0 0 0 0 11 1 1 0 1
10 0 0 1 0 10 1 1 0 0
f ( A < B) = A1 .B1 + A0 .B1 .B0 + A1 .A0 .B0 . f ( A > B) = A1 .B1 + A0 .B1 .B0 + A1 .A0 .B0 .
(12)
For f(A = B):
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B1 B0
00 01 11 10
00 1 0 0 0
01 0 1 0 0
A1 A0
11 0 0 1 0
10 0 0 0 1
f ( A = B) = A1 .A0 .B1 .B0 + A1 .A0 .B1 .B0 + A1 .A0 .B1 .B0 + A1 .A0 .B1 .B0
= A1 .B1 ( A0 .B0 + A0 .B0 ) + A1 .B1 ( A0 .B0 + A0 .B0 )
(13)
= ( A0 .B0 + A0 .B0 )( A1 .B1 + A1 .B1 )
= ( A0 B0 )( A1 B1 ).
Figure 25: Circuit diagram of Magnitude Comparator
Circuit diagram:
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7.2 Design of magnitude comparator using IC
AIM: Design & verification of 4-bit magnitude comparator
Components Required: IC 7485, Digital Test Kit.
Theory: Magnitude Comparator is a logical circuit, which compares two signals

A and B and generates three logical outputs, whether A > B, A = B, or A < B . IC 7485
is a high speed 4-bit Magnitude Comparator, which compares two 4-bit words. The A
= B Input must be held high for proper compare operation.
Figure 26: Circuit diagram of Magnitude Comparator
Pin diagram:
Circuit diagram:
Results: All the outputs are verified with their truth table.
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S R Q(t+1)
0 0 Q(t)
0 1 0
1 0 1
1 1 Invalid
Table 15: Truth Table of SR F/F
Table 16: SR Flip Flop
8 DESIGN OF LATCHES & FLIP-FLOPS
8.1 Design & verification of SR, JK, D, T & Master-Slave JK

Flip-flops
AIM: To set up and test the following flipflops using ICs 7400 and 7410. (1) SR
FF(2) JK FF(3)D FF (4) T FF(5) MS JK FF
Components Required: ICs 7400, 7410, bread board, power supply, connecting
wires, Digital Test Kit.
Theory: Flipflops are synchronous bistable devices. The term synchronous

implies that output changes state only at specified point of a trigger input called the
clock. A flipflop has two stages 0 or1. Set is state 1 and 0 is the reset state. The output
state for any input depends on past input and data inputs present at that instant. The
state may change only when a clock is applied. SR Flipflop: The set reset flipflop is
the most basic variety. The output changes only when clock is high. If S=1, R=0 then
output is Q=1 and Q = 0 and the FF is in set state. If S=0, R=1 the output Q=0 and
Q = 0, then the FF is in reset state. For an input of S=0, R=0, the present output will
be same as past output. An input of S=1, R=1 is not allowed.
JK Flipflop: The functioning is similar to SR FF in set and reset modes. The difference
is that JK FF has no invalid state as in SR FF at S=1 R=1.Here Q and Q are connected
to the input NAND gates. If J=K=1, flipflop changes to opposite state (toggling) with
each successive clock pulse (if race around condition is avoided).
T Flipflop: It is obtained by shorting the J and K inputs of JK FF so that T FF has
only one input and the clock. D Flipflop: This is used for data storage of 1 bit. It has
only one input and a clock. When D is high, operation is in set state and Q=1. When
D is low, it is reset and Q = 0.
Master slave JK flipflop: An MS FF has two separate flipflops. One is the master
and other is the slave. The clock fed to the master is inverted and fed to the slave.
This enables the slave following the master and thus eliminating the problem of race
around condition. Racing is the toggling of output more than once during the positive
clock edge. The first stage of the MS FF is JK FF and the 2nd stage is an SR FF.
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J K Q(t+1)
0 0 Q(t)
0 1 0
1 0 1
1 1 Q(t)
Table 17: Truth Table of JK F/F
Table 18: JK Flip Flop
Table 19: Truth Table of T F/F
T Q(t+1)
0 Q(t)
1 Q(t)
D Q(t+1)
0 0
1 1
Table 20: Truth Table of D F/F
Table 21: D Flip Flop
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Figure 27: Circuit diagram of Master & Slave Flipflop
Circuit diagram:
9 DESIGN OF ASYNCHRONOUS COUNTER
AIM: To set up the following counters using JK FF (1) 4 bit binary up counter (mod16)
(2) 4 bit binary down counter (3) Decade counter. (4) 3 bit up/down counter using
mod control
Components Required: ICs 7476, 7400, Digital Test Kit.
Theory: A counter is a circuit that produces a set of unique output combinations

in relation to the no: of applied input pulses. The no: of unique outputs of a counter
is known as its modulus or mod number. In asynchronous counters, the flip flops are
not given clock simultaneously. Four flip flops must be used in toggle mod to count 16
states. (1) 4 bit up counter: All outputs are clocked by the Q output of the proceeding
FF. JK inputs are connected to a high state. 7476 is a dual JK master slave FF with
preset and clear. A ripple counter comprising of n flip flops can be used to count up
to 2n pulses. A 4 FF circuit gives a maximum count of 24 = 16. With the application
of first clock pulse, Q0 changes from 0 to 1.Q1, Q2, Q3 remains unaffected. With the
2nd clock pulse, Q0 becomes 0 and Q1 becomes 1.At the arrival of the 15th clock pulse
all the Q outputs becomes 1.At the 16th clock pulse all Q outputs become reset and
cycle repeats. (2) 4 bit binary down counter: In this counter, all outputs are clocked by
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CLK Q3 Q2 Q1 Q0 CLK Q3 Q2 Q1 Q0
0 0 0 0 0 0 1 1 1 1
1 0 0 0 1 1 1 1 1 0
2 0 0 1 0 2 1 1 0 1
3 0 0 1 1 3 1 1 0 0
4 0 1 0 0 4 1 0 1 1
5 0 1 0 1 5 1 0 1 0
6 0 1 1 0 6 1 0 0 1
7 0 1 1 1 7 1 0 0 0
8 1 0 0 0 8 0 1 1 1
9 1 0 0 1 9 0 1 1 0
10 1 0 1 0 10 0 1 0 1
11 1 0 1 1 11 0 1 0 0
12 1 1 0 0 12 0 0 1 1
13 1 1 0 1 13 0 0 1 0
14 1 1 1 0 14 0 0 0 1
15 1 1 1 1 15 0 0 0 0
Table 22: 4-bit Binay Up Counter Table 23: 4-bit Binay Down Counter
the Q output of the proceeding FF. The outputs are taken from the Q outputs. Initially
all Q outputs are set. At the 16th clock pulse all Q outputs become reset and cycle
repeats. (3) Decade counter: The circuit of the decade counter is similar to the 4 bit
ripple counter ,but with the aid of a logic circuit the count is limited to 9.As soon as the
count 1010 takes place, a NAND gate clears the flip flops and counting restarts from 0.
(4) 3 bit up/down counter: The direction of counting sequence is made dependant on
a mode control input. A logic circuit connected between the flip flop does a mere job of
connecting either if the Q or Q .When mode control is 1 Q outputs are connected to the
clock inputs of the succeeding flip flops .If mode control is 0, Q outputs are connected
to the clock inputs.
Circuit diagram:
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CLK Q3 Q2 Q1 Q0
0 0 0 0 0 M Q2 Q1 Q0 M Q2 Q1 Q0
1 0 0 0 1 1 0 0 0 0 1 1 1
2 0 0 1 0 1 0 0 1 0 1 1 0
3 0 0 1 1 1 0 1 0 0 1 0 1
4 0 1 0 0 1 0 1 1 0 1 0 0
5 0 1 0 1 1 1 0 0 0 0 1 1
6 0 1 1 0 1 1 0 1 0 0 1 0
7 0 1 1 1 1 1 1 0 0 0 0 1
8 1 0 0 0 1 1 1 1 0 0 0 0
9 1 0 0 1 Table 25: 3-bit Binay Up-Down Counter
Table 24: Decade Counter
Figure 28: Circuit diagram of Up Counter
10 DESIGN SYNCHRONOUS COUNTER
10.1 Design of MOD16 Synchronous Counter
AIM: To design and set up the circuits of a MOD16 Synchronous Counter
Components Required: Digital Test Kit, IC7474, 7486, 7408 & patch chords.
Theory: Synchronous and asynchronous counters provide same outputs. The

difference is that in synchronous counters all flip flops are working in synchronism with
the input clock pulse. The additive propagation delay appears in the asynchronous
counters and it is avoided in synchronous counters, yielding to a tradeoff with the
circuit complexity and comparatively tedious design process. Synchronous counters
for any count sequence and modulus can be designed and set up the following design
procedure:
Step 1: Find the number of flip flops using the relation M = 2 N where M is the modulus
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Figure 29: Circuit diagram of Down Counter
Figure 30: Circuit diagram of Decade Counter
of the counter and N is the minimum number of flip flops required =N = log2 M.
Step 2: Write down the count sequence in a tabular form.
Step 3: Determine the flip-flops inputs which must be present for the desired next state
using excitation table of flip-flops.
Step 4: Prepare Karnaugh maps for each FF input in terms of FF outputs as the input
variables. Obtain the minimized expressions from K-maps.
Step 5: Set up the circuit using FFs and other gates.
Circuit diagram:
10.2 Design of MOD8 Synchronous Counter
AIM: To design and set up the circuits of a MOD8 Synchronous Counter
Components Required: Digital Test Kit, IC7474, 7486, 7408 & patch chords.
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Figure 31: Circuit diagram of Decade Counter
Figure 32: Circuit diagram of 3-bit Up-Down Counter
Theory: Synchronous and asynchronous counters provide same outputs. The

difference is that in synchronous counters all flip flops are working in synchronism with
the input clock pulse. The additive propagation delay appears in the asynchronous
counters and it is avoided in synchronous counters, yielding to a tradeoff with the
circuit complexity and comparatively tedious design process. Synchronous counters
for any count sequence and modulus can be designed and set up the following design
procedure:
Step 1: Find the number of flip flops using the relation M = 2 N where M is the modulus
of the counter and N is the minimum number of flip flops required =N = log2 M.
Step 2: Write down the count sequence in a tabular form.
Step 3: Determine the flip-flops inputs which must be present for the desired next state
using excitation table of flip-flops.
Step 4: Prepare Karnaugh maps for each FF input in terms of FF outputs as the input
variables. Obtain the minimized expressions from K-maps.
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Figure 33: Circuit diagram of MOD16 counter
Step 5: Set up the circuit using FFs and other gates.
Circuit diagram:
Results:
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11 DESIGN OF SHIFT REGISTER
AIM: To set up and verify the performance of a serial in parallel out shift register
and Serial/parallel input shift register using mode control using JK and D flip flops.
Theory: A register is a group of flip flops that can be used to store a binary number.
A shift register is nothing but a register which access a binary number and shifts it. The
data can be entered to the shift register either in serial or parallel. Similarly, the output
can be taken from it either serial or in parallel. Since there are Two ways to shift data
into a register and similarly two ways to shift data out of register, four basic register
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Figure 34: Circuit diagram of MOD8 counter
types can be constructed viz., Serial in Serial out (SISO), serial in parallel out (SIPO),
parallel in serial out(PISO), parallel in parallel out(PIPO). Serial input Shift register:
As its name suggests , serial input shift register allows the data to enter serially. The
output data can be available in parallel or serial. Serial/parallel shift register using
mode control: In this type of shift register data can be fed in serial or parallel using the
mode control pin. Output can be taken serial or in parallel. Serial input is fed through
pin number 2 of 4 × 1 MUX and parallel input I3 I2 I1 I0 is fed through pin number 3 of
4 × 1 MUX. Serial output is taken from A3 and parallel output from A3 A2 A1 A0 .
Circuit diagram:
12 DESIGN OF MEMORY
AIM: To design and set up the circuits of a 64-bits RAM
Components Required: Digital Test Kit, IC7489, 74193 & patch chords.
Theory: IC7489 is a 16×4 RAM. The pin assignments to the inputs and outputs are
shown in Fig.36a. The four address inputs select 1 of 16 words in the memory. The least
significant bit of the address is A and the most significant is A3. The Memory Enable
(ME) input must be equal to 0 to enable the memory. If ME is equal to 1, the memory
is disabled and all four outputs are in a high-impedance state. The write enable (
WE ) input determines the type of operation, as indicated in the function table. The
write operation is performed when WE = 0. This operation is a transfer of the binary
number from the data inputs into the selected word in memory. The read operation is
51 | 55
Contents
Figure 35: Circuit diagram of Universal Shift Register
Table 26: Function Table for RAM
Function Table
ME WE Operation Data outputs
0 0 Write High impedance
0 1 Read Complement of selected word
1 X Disable High impedance
performed when WE = 1. This operation transfers the complemented value stored in

the selected word into the output data lines. The memory has three-state outputs to
facilitate memory expansion.
Circuit diagram:
Results: Tabulate the value you have written & read while doing the write & read
operations.
52 | 55
Contents
(a) Pin diagram of IC 7489 (b) Circuit diagram for Read & Write operation of RAM
table or excitation table.
13 FSM BASED DESIGN PROJECT
53 | 55
Bibliography
Bibliography
[1] Digital Design: With an Introduction to the Verilog HDL by M. Moris Mano,
Michael D. Ciletti, 5th Edition, Pearson, 2013.
55 | 55

Digital Electronics Laboratory Manual (ECE211) : Dr. Pradyut Kumar Sanki

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Digital Electronics

October 21, 2019

DESIGN OF ARITHMETIC LOGIC UNIT Data Transfer through Multiplexer/De-

1 FAMILIARIZATION OF LOGIC GATES & DIGITAL ICS

Components Required: Following components in Table 7 are required for perform-

Table 1: List of components

SL No. COMPONENT SPECIFICATION QTY

Figure 1: Schematic of Breadboard.

Figure 2: Digital Logic Gates

Figure 3: Pin Connections of TTL 74XX series Quad 2-input Gates

Table 2: Part Identification

Specs/Temp Indicator: 75 - Interface device

Technology Indicator: Some of more popular ones you’ll encounter are:

BiCMOS: BCT - BiCMOS

Table 3: Digital IC Series

Digital ICs 1-I/P 2-I/Ps 3-I/Ps 4-I/Ps 8-I/Ps

Package Designation: D - DIP (Dual Inline Package), DB - SSOP (Shrink Small-

Example Chip is labeled DM74LS221N:

2 DESIGN OF CODE CONVERTERS

2.1 Design of 4-bit Binary to Gray Code Converter

Components Required: Digital Test Kit, ICs 7486.

THEORY: To convert a binary number to corresponding Gray code, the following

Table 4: Truth Table for Binay to Gray Conversion

Decimal Binary Inputs Gray Outputs

For G3 & G2:

For G1 & G0:

(a) Binary to Gray Converter (b) Gray to Binary Converter

2.2 To design and set up the circuits of a 4-bit Gray to

AIM: Design of 4-bit Gray to Binary Code Converter

Components Required: Digital Test Kit, ICs 7486.

Table 5: Truth Table for Gray to Binay Conversion

Decimal Gray Inputs Binary Outputs

For B8 & B4:

For B2 & B1:

3 DESIGN OF COMBINATIONAL LOGIC CIRCUITS

3.1 Design of Adder

The carry bit generated by this Half Adder is given by

Table 6: Truth Table for Half Adder

Table 7: Truth Table for Full Adder

3.2 Design of Subtractor

Table 8: Truth Table for Half Subtractor

3.3 Parallel Adder/Subtractor

Components Required: Digital Test Kit, IC - 7483, Connecting patch chords.

Table 9: Truth Table for Full Subtractor

Pin Diagram: The pin connections of this IC is given in Fig. 8.

(a) Full Adder (b) Full Subtractor

Figure 7: Circuit diagram for Full Adder & Full Subtractor

Figure 8: Pin diagram of IC-7483

Results: Addition & subtraction of two 4-bit numbers are verified.

Figure 9: Circuit diagram of 4-bit Adder/Subtractor

4 DESIGN OF LOGIC CIRCUITS USING MULTIPLEXER &

4.1 Design & Verification of Multiplexer

AIM: (1) To set up a 4 x 1 multiplexer using gates (2) Verification of 2 x 1, 4 x 1 &

Theory: A multiplexer is a combinational circuit that selects binary information

Y = S.I0 + S.I1 . (8)

Y = S1 .S0 .I0 + S1 .S0 .I1 + S1 .S0 .I2 + S1 .S0 .I3 . (9)

Figure 10: Pin Diagram of Mux/Dmux

Figure 11: Circuit Diagram of 2:1 & 4:1 Muxes

Results: Muxes are verified with their truth table.

4.2 Design of Half Adder/subtractor using Multiplexer

(a) Halfl Adder (b) Half Subtractor

4.3 Design of Full Adder/subtractor using Multiplexer

(a) Full Adder (b) Full Subtractor