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Designing a 1-bit Comparator Cell and Cascading It to Form a Comparator for

Two 4-bit Numbers Using Cadence and Verilog

Technical Report · April 2019

DOI: 10.13140/RG.2.2.35201.58723/1

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 Chittagong University of Engineering & Technology

Department of Electrical and Electronic Engineering

EEE 490: VLSI Technology Sessional

Project Name: Designing a Cascadable

Comparator Cell and Cascading It to Form a
Comparator for Two 4-bit Numbers

Prepared By

Students Name: Arpita Das,Sudeshna Das

Student IDs of Group Members: 1402054,1402061
Group No.: 13
Section: A
Date of Submission: April 07, 2019
Arpita Das Sudeshna Das 1402054 1402061

ABSTRACT

In this project, a 4 bit comparator cell has been designed in Cadence Vir-
tuoso. For design purpose, nmos and pmos widths are specified to 240nm
and 120nm respectively. A gate level schematic design along with layout
diagram of 4-bit comparator including each of the gates or sub-block used
in this project have been developed. Our design has been verified through
DRC(Design Rule Check) and LVS(Layout versus Schematic) checking. Post
layout simulation of each sub-block of our system and of the full design have
been performed to verify its functionality. After that, full chip layout has
been completed with I/O pad placement and this full chip design is also veri-
fied through DRC,LVS checking. Finally, a GDS(Graphic Database System)
file of the layout has been generated that is normally sent to the foundry
for fabrication. Besides, the functionality of 4-bit comparator using Inci-
sive Unified Simulator(IUS) is also verified by Verilog and Testbench code in
Cadence NCSim Software which has also ensured our simulation output.

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KEYWORDS

1. Cadence Virtuoso Software

2. DRC Rules Check(DRC)

3. Layout versus Schematic Check(LVS)

4. 4 bit Comparator Cell

5. GDS (Graphic Database System) file of layout

6. Incisive Unified Simulator(IUS)

7. Cadence NCSim Software

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Table of Contents
1 INTRODUCTION 7

2 THEORY 7
2.1 4-Bit Magnitude Comparator . . . . . . . . . . . . . . . . . . 8

3 PRE-WORK DATA AND RESULTS 8

4 TASKS 9
4.1 Specification, Architectural Design and Functional Verification 9
4.1.1 Specification . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1.2 Behavioural Verilog Code of a Comparator for Two
4-bit Numbers in Cadence NCSim Software Using In-
cisive Unified Simulator (IUS) . . . . . . . . . . . . . . 9
4.1.3 Functional Verification of 4-bit Comparator Circuit Us-
ing Incisive Unified Simulator (IUS) . . . . . . . . . . . 12
4.2 Gate Level Design,Layout Simulation,DRC and LVS check of
Each Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2.1 Gate Level Design and Layout Simulation of Inverter . 13
4.2.2 Gate Level Design and Layout Simulation of Two Input
Nor Gate . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2.3 Gate Level Design and Layout Simulation of Three In-
put Nor . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3 Gate Level Design and Layout Simulation of Each Sub-block . 22
4.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.5 Gate Level Schematic Design,Top Level Layout Placement,
Routing of 4 bit Comparator, Layout Simulation and DRC,LVS
Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.5.1 Gate Level Schematic Design . . . . . . . . . . . . . . 26
4.5.2 Top Level Layout Placement and Routing . . . . . . . 27
4.5.3 Layout Simulation and DRC,LVS Check . . . . . . . . 29
4.6 Complete Chip Layout with I/O Pad Placement, Clearing All
DRC Errors and Tape Out . . . . . . . . . . . . . . . . . . . . 31
4.6.1 Complete Chip Layout with I/O Pad Placement . . . . 31
4.6.2 DRC and LVS Check . . . . . . . . . . . . . . . . . . . 31

5 TOOLS USED 32

6 CONCLUSION 32

7 FUTURE IMPROVEMENTS 32

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8 REFERENCES 32

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List of Figures
1 Output Waveforms of 4-bit Comparator . . . . . . . . . . . . . 12
2 Schematic Design of Inverter . . . . . . . . . . . . . . . . . . . 13
3 Symbol of Inverter . . . . . . . . . . . . . . . . . . . . . . . . 13
4 Layout Diagram of Inverter . . . . . . . . . . . . . . . . . . . 14
5 DRC and LVS Check of the layout of Inverter . . . . . . . . . 14
6 Output Waveform of Inverter . . . . . . . . . . . . . . . . . . 15
7 Schematic Design of Two Input Nor Gate . . . . . . . . . . . . 16
8 Symbol of Two Input Nor Gate . . . . . . . . . . . . . . . . . 16
9 Layout Diagram of Two Input Nor Gate . . . . . . . . . . . . 17
10 DRC and LVS Check of the layout of Two Input Nor Gate . . 17
11 Output Waveform of Two Input Nor Gate . . . . . . . . . . . 18
12 Schematic Design of Three Input Nor Gate . . . . . . . . . . . 19
13 Symbol of Three Input Nor Gate . . . . . . . . . . . . . . . . 19
14 Layout Diagram of Three Input Nor Gate . . . . . . . . . . . 20
15 DRC and LVS Check of the layout of Three Input Nor Gate . 20
16 Output Waveform of Three Input Nor Gate . . . . . . . . . . 21
17 Schematic Design of 1-bit Comparator . . . . . . . . . . . . . 22
18 Layout Diagram of 1-bit Comparator . . . . . . . . . . . . . . 23
19 DRC and LVS Check of the layout of 1-bit Comparator . . . . 23
20 Output Waveforms of 1-bit Comparator . . . . . . . . . . . . . 24
21 Block Diagram of 4-bit Comparator . . . . . . . . . . . . . . . 25
22 Schematic Design of 4-bit Comparator . . . . . . . . . . . . . 26
23 Layout Diagram of 4-bit Comparator before Routing . . . . . 27
24 Layout Diagram of 4-bit Comparator after Routing . . . . . . 28
25 DRC and LVS Check of the layout of 4-bit Comparator . . . . 29
26 AV extracted view of 4-bit Comparator showing parasitic ca-
pacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
27 Output Waveforms of 4-bit Comparator . . . . . . . . . . . . . 30
28 Complete Chip Layout with I/O Pad Placement . . . . . . . . 31
29 DRC and LVS Check of Complete Chip Layout . . . . . . . . 31

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1 INTRODUCTION
In electronics, the comparator is used to compare two voltages or currents
which are given at the two inputs of the comparator. That means it takes two
input voltages, then compares them and gives a differential output voltage
either high or low-level signal. A digital comparator or magnitude com-
parator is a hardware electronic device that takes two numbers as inputs in
binary form and determines whether one number is greater than, less than or
equal to the other number. Comparators are used in central processing units
(CPUs) and microcontrollers (MCUs). In metrology, measuring instruments
and comparators play significant role. Measuring instruments are used to
measure the actual dimension of the work piece, whereas the comparators
are used for comparison of the actual dimension with the working standard.
In our 4-bit comparator project, we will use Cadence Virtuoso and Cadence
NCSim Software for design purpose and to verify its functionality. We will
also design complete chip layout with I/O pad placement and create a GDS
file from the layout which is normally sent to the foundry for fabrication.

2 THEORY
A magnitude digital comparator is a combinational circuit that compares two
digital or binary numbers in order to find out whether one binary number
is equal, less than or greater than the other binary number. We logically
design a circuit for which we will have two inputs one for A and other for
B and have two output terminals, one for A>B condition and one for A<B
condition. For circuit requirements, we have considered only greater and
smaller outputs. The truth table for a binary 1-bit comparator bit-slice is
given in table 01.

Table 1: Truth Table of Comparator

Inputs Outputs
Ai Bi Gi+1 Si+1 Gi Si
x x 1 0 1 0
x x 0 1 0 1
0 0 0 0 0 0
0 1 0 0 0 1
1 0 0 0 1 0
1 1 0 0 0 0

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2.1 4-Bit Magnitude Comparator

A comparator is used to compare two binary numbers each of four bits is
called a 4-bit magnitude comparator. It consists of eight inputs each for two
four bit numbers and three outputs to generate less than, equal to and greater
than between two binary numbers. In a 4-bit comparator the condition of
A>B can be possible in the following four cases:

1. If A3 = 1 and B3 = 0

2. f A3 = B3 and A2 = 1 and B2 = 0

3. If A3 = B3, A2 = B2 and A1 = 1 and B1 = 0

4. If A3 = B3, A2 = B2, A1 = B1 and A0 = 1 and B0 = 0

Similarly the condition for A<B can be possible in the following four cases

1. If A3 = 0 and B3 = 1

2. f A3 = B3 and A2 = 0 and B2 = 1

3. If A3 = B3, A2 = B2 and A1 = 0 and B1 = 1

4. If A3 = B3, A2 = B2, A1 = B1 and A0 = 0 and B0 = 1

For our project purpose and according to the given suggestions, we have con-
sidered only outputs for A>B and A<B. The logic expressions for the two
output signals in terms of the four input signals are as follows:-

Greater = Gi+1 + Si+1 + Ai + Bi

Smaller = Si+1 + Gi+1 + Bi + Ai

3 PRE-WORK DATA AND RESULTS

There is no pre-work data and results associated with this project.

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4 TASKS
4.1 Specification, Architectural Design and Functional
Verification
4.1.1 Specification
For design purpose, the width of nmos is specified to 240nm and pmos is
specified to 120nm.

4.1.2 Behavioural Verilog Code of a Comparator for Two 4-bit

Numbers in Cadence NCSim Software Using Incisive Uni-
fied Simulator (IUS)
The Verilog code for 4 bit comparator is given as follows:-

//The V e r i l o g module−
//The i n p u t s and o u t p u t s i g n a l s are d e c l a r e d

module comparator (
intA , // i n p u t A
intB , // i n p u t B
smaller , // h i g h when A i s l e s s than B
greater // h i g h when A i s g r e a t e r than B
);

parameter n=4;

// what are t h e i n p u t p o r t s .
input [ n − 1 : 0 ] intA , intB ;

//What are t h e o u t p u t p o r t s .
output reg s m a l l e r , g r e a t e r ;

//When t h e i n p u t s and A or B are changed ,

// t h i s b l o c k i s e x e c u t e d

always @( intA or intB )

begin
i f ( intA > intB )
begin

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Arpita Das Sudeshna Das 1402054 1402061

// c h e c k i f A i s b i g g e r than B.
{ s m a l l e r , g r e a t e r }=2 ’ b01 ;
end
e l s e i f ( intA == intB )
begin
// Check i f A i s e q u a l t o B
{ s m a l l e r , g r e a t e r }=2 ’ b00 ;
end
e l s e i f ( intA < intB )
begin
// O t h e r w i s e − c h e c k f o r A l e s s than B.
{ s m a l l e r , g r e a t e r }=2 ’ b10 ;
end
end

endmodule

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The testbench code for Comparator is given as follows :-

module c o m p t s t ;

parameter n=4;

// what are t h e i n p u t p o r t s .
reg [ n − 1 : 0 ] intA , intB ;

//What are t h e o u t p u t p o r t s .
wire s m a l l e r , g r e a t e r ;

// I n s t a n t i a t e t h e Unit Under Test (UUT)

comparator uut (
. intA ( intA ) ,
. intB ( intB ) ,
. smaller ( smaller ) ,
. greater ( greater )
);

i n i t i a l begin
// Apply i n p u t s
intA = 2 ;
intB = 3 ;
#100;
intA = 9 ;
intB = 8 ;
#100;
intA = 1 1 ;
intB = 1 2 ;
#100;
intA = 1 3 ;
intB = 1 3 ;
#100;
intA = 1 5 ;
intB = 1 4 ;
#100;
intA = 1 1 ;
intB = 2 ;
#100;

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Arpita Das Sudeshna Das 1402054 1402061

intA = 4 ;
intB = 6 ;
#100;
end

initial begin
$shm open ( ”shm . db” , 1 ) ; // Opens a waveform d a t a b a s e
$shm probe ( ”AS” ) ; // Saves a l l s i g n a l s t o d a t a b a s e
#700 $finish ;
#750 $ s h m c l o s e ( ) ; // C l o s e s t h e waveform d a t a b a s e
end

endmodule

4.1.3 Functional Verification of 4-bit Comparator Circuit Using

Incisive Unified Simulator (IUS)

Figure 1: Output Waveforms of 4-bit Comparator

From figure 1 we see that, the inputs A and B are taken after every
100ns.The simulation is stopped at 700ns which is evident from the figure.The
waveform database is closed at 750ns. We can observe two observations ,
one of which is between 0 to 100ns at which A<B and for this Smaller=1.
Another one is between 300ns and 400ns at which both inputs are same and
the generated outputs are both zero. So we see the co-ordination of Table 1
with the output from Figure 1. We have verified the functionality of 4-bit
comparator with the truth table and the result is positive.

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4.2 Gate Level Design,Layout Simulation,DRC and LVS

check of Each Gate
4.2.1 Gate Level Design and Layout Simulation of Inverter
Inverters or NOT gates are single input devices which have an output level
that is normally at logic level 1 and goes LOW to a logic level 0 when its
single input is at logic level 1, in other words it invertes (complements) its
input signal. The output from a NOT gate only returns HIGH again when
its input is at logic level 0 which is also evident from Figure 5.

Figure 2: Schematic Design of Inverter

Figure 3: Symbol of Inverter

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Figure 4: Layout Diagram of Inverter

(a) DRC Check (b) LVS Check

Figure 5: DRC and LVS Check of the layout of Inverter

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Figure 6: Output Waveform of Inverter

From Figure 5, we see that when the gate receives a HIGH signal, it
makes it LOW signal by inverting it and similar is the case for LOW signal
when the gate receives it. The output is plotted for 20ns transient response.

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4.2.2 Gate Level Design and Layout Simulation of Two Input Nor
Gate
The inclusive NOR (Not-OR) gate has an output that is normally at logic
level 1 and only goes LOW to logic level 0 when any of its inputs are at logic
level 1. The NOR gate is implemented by connecting two p-mos in series
and two n-mos in parallel. The output is taken from the common terminal
of drain of n-mos and drain of one p-mos that is immediately connected to
the common drain terminal of two n-mos.

Figure 7: Schematic Design of Two Input Nor Gate

Figure 8: Symbol of Two Input Nor Gate

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Figure 9: Layout Diagram of Two Input Nor Gate

(a) DRC Check (b) LVS Check

Figure 10: DRC and LVS Check of the layout of Two Input Nor Gate

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Figure 11: Output Waveform of Two Input Nor Gate

From Figure 11, it is seen that when the gate receives HIGH signal at
any of input terminals, it immediately makes it output LOW. When the gate
receives two LOW signals at its both input terminals at the same time, the
output becomes HIGH. The output is plotted for 25ns transient response.

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4.2.3 Gate Level Design and Layout Simulation of Three Input

Nor
The three input nor gate is a digital logic gate that implements logical
NOR.The operation is similar to the two input nor gate. A HIGH output (1)
results if all inputs to the gate are low (0); if only one input is HIGH (1), a
low output (0) results. It shares this property with the NAND gate. Likewise
two input nor gate, it is implemented by connecting three p-mos in series and
three n-mos in parallel. The output is taken from the common terminal of
drain of n-mos and drain of one p-mos that is immediately connected to the
common drain terminal of three n-mos which is evident in figure 12.

Figure 12: Schematic Design of Three Input Nor Gate

Figure 13: Symbol of Three Input Nor Gate

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Arpita Das Sudeshna Das 1402054 1402061

Figure 14: Layout Diagram of Three Input Nor Gate

(a) DRC Check (b) LVS Check

Figure 15: DRC and LVS Check of the layout of Three Input Nor Gate

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Arpita Das Sudeshna Das 1402054 1402061

Figure 16: Output Waveform of Three Input Nor Gate

From Figure 16, likewise the operation of two input nor gate, it is seen
that when the gate receives HIGH signal at any of three input terminals,
it immediately makes it output LOW. When the gate receives LOW signals
at all its input terminals at the same time, the output becomes HIGH. The
output is plotted for 25ns transient response.

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4.3 Gate Level Design and Layout Simulation of Each

Sub-block
The operation of the complete schematic circuit shown in figure 17 is as
follows:

1. The two numbers are compared starting with the most significant bits.
The outputs from this comparison are connected to the next most sig-
nificant bit stage inputs etc. The two output signals Gi and Si remain
at zero as long as the two bits being compared are the same.

2. As soon as a difference is detected, the two outputs are set to one of

two possible states. If Ai > Bi then Gi = 1 and Si = 0 if Ai < Bi then
Gi = 0 and Si = 1.

3. All the remaining pairs of less significant bits then have no further
effect on the state of subsequent outputs Gi and Si .

4. If all pairs of bits of the two numbers being compared are equal, then
the outputs stay at zero signifying equality.

Figure 17: Schematic Design of 1-bit Comparator

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Arpita Das Sudeshna Das 1402054 1402061

Figure 18: Layout Diagram of 1-bit Comparator

(a) DRC Check (b) LVS Check

Figure 19: DRC and LVS Check of the layout of 1-bit Comparator

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Figure 20: Output Waveforms of 1-bit Comparator

From figure 20, we can see that whenever A3>B3 output greater is high
and when B3>A3 output smaller is high. The output is plotted for 20ns
transient response.

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4.4 Block Diagram

In the previous section,the schematic design of one bit comparator was shown.
To make a 4-bit comparator with one bit comparator circuit,four 1-bit com-
parator circuit has been cascaded which has been shown by block diagram
below in the figure 21.

In the cascaded circuit,we have assigned the inputs from the outputs of pre-
vious stage by Gi1 and Si1 for the 1st block. Outputs of the 1st block( G3 ,
S3 ) are inputs to the 2nd block and so likewise for other two blocks. The two
numbers A and B consist of four bits. In the comparison process if outputs
of previous stages are different from each other(e.g. G3 =1, S3 =0), resultant
greater will be high and smaller will be low and the circuit will not respond
to the values of inputs. Similar is the case when G3 =0, S3 =1. But if the
previous stages output bits are both zero,only then the output will respond
to the inputs.

Thus,comparing two bits per block along with outputs of previous stage we
get the resultant as ’Greater’ and ’Smaller’. The normalized block diagram
is as follows :-

Figure 21: Block Diagram of 4-bit Comparator

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4.5 Gate Level Schematic Design,Top Level Layout Place-

ment, Routing of 4 bit Comparator, Layout Simu-
lation and DRC,LVS Check
4.5.1 Gate Level Schematic Design
In this section we have shown the schematic design of cascaded 4-bit com-
parator which is the detailed version of the block diagram(figure 21)

Gi1 , Si1 , Ai , Bi are the inputs. For different values of Gi1 and Si1 , states of
Ai and Bi will be neglected otherwise states of Ai and Bi will be compared.
So we will get the comparator result on the basis of Gi1 , Si1 ,Ai , Bi for
three different cases.

For the whole cascaded circuit, 16 inverters, 8 two input nor and 8 three
input gates are used.

Figure 22: Schematic Design of 4-bit Comparator

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4.5.2 Top Level Layout Placement and Routing

In this section we have shown a figure without routing among the gates.
From the cascaded design, we have automatically generated from all sources
as shown in figure 23.

Figure 23: Layout Diagram of 4-bit Comparator before Routing

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Figure 24: Layout Diagram of 4-bit Comparator after Routing

Figure 24 is the complete layout connection of cascaded 4-bit comparator

after interconnecting all gates,each vdd and gnd with the vdd rail and gnd
rail.

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4.5.3 Layout Simulation and DRC,LVS Check

(a) DRC Check (b) LVS Check

Figure 25: DRC and LVS Check of the layout of 4-bit Comparator

Figure 26: AV extracted view of 4-bit Comparator showing parasitic capac-

itance

Figure 26 is the av extracted view of 4-bit comparator showing parasitic

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Arpita Das Sudeshna Das 1402054 1402061

capacitances, parasitic resistances which is created after post layout simula-

tion. Parasitic extraction is the calculation of the parasitic effects in both
the designed devices and the required wiring interconnects of an electronic
circuit. In order to get an idea of how the design would work from layout,a
post-layout simulation from the extracted view have been performed.

Figure 27: Output Waveforms of 4-bit Comparator

From figure 27, we can study a few observations. One of which is between
0 to 5ns in which B>A, both Gi1 and Si1 both are 0. The resultant smaller
output is 1 and greater is 0.
Another one is between 20 to 25ns in which A>B, both Gi1 and Si1 both are
0. The resultant greater output is 1 and smaller is 0.
Another one is between 15 to 20ns in which A=B, both Gi1 and Si1 both are
0. The both outputs are 0.
Another one is between 25 to 30ns in which A>B, Gi1 is 0 and Si1 is 1. The
resultant greater output is 0 and smaller is 1. So in this time duration, we
see that outputs do not respond to the states of the inputs. Similar is the
case with 30 to 35ns.
Hence, the functionality of 4-bit comparator is verified.

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4.6 Complete Chip Layout with I/O Pad Placement,

Clearing All DRC Errors and Tape Out
4.6.1 Complete Chip Layout with I/O Pad Placement

Figure 28: Complete Chip Layout with I/O Pad Placement

4.6.2 DRC and LVS Check

(a) DRC Check (b) LVS Check

Figure 29: DRC and LVS Check of Complete Chip Layout

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5 TOOLS USED
In this experiment we used:

• Cadence Virtuoso

• Cadence NCSim Software

• Cadence’s ASUURA

6 CONCLUSION
Using Cadence Virtuoso and Cadence NCSim Software,a system design with
functional architectural analysis of 4-bit comparator have been performed.
At the end of this project, design of a complete chip and a GDS file of the
layout have been created after clearing all design rule errors and layout to
schematic verification.

7 FUTURE IMPROVEMENTS
The critical delay in this circuit is the propagation delay of the two outputs
through all the stages. The gates passing both outputs should be sized appro-
priately. The delay is only one gate per stage and should not be the limiting
factor on a system’s scale. In our design,there are some ripples occured in
both input and output signals. This is due to the signals passing through all
gates which causes propagation delay. As a future improvement,we can look
forward to minimizing this delay to reduce ripples.

8 REFERENCES
1. Lab Manual

2. http://www.google.com

3. Basic VLSI Design: Douglas A.Pucknell & Kamran Eshraghian

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