Cadence IC Design Manual

For EE5518

ZHENG Huan Qun

Lin Long Yang

Revised on
May 2017

Department of Electrical & Computer Engineering

National University of Singapore

1 | P a g e  
 
Contents 
1  INTRODUCTION ..................................................................................................................................... 4 
1.1  Overview of Design Flow ............................................................................................................... 4 
1.2  Getting Started with Cadence ....................................................................................................... 6 
1.3  Using Online Help .......................................................................................................................... 8 
1.4  Exit Cadence .................................................................................................................................. 8 
2  SCHEMATIC ENTRY ................................................................................................................................ 9 
2.1  Creating a New Design Library ...................................................................................................... 9 
2.2  Creating a Schematic Cellview .................................................................................................... 10 
2.3  Adding Components to Schematic .............................................................................................. 11 
2.4  Adding Pins to Schematic ............................................................................................................ 12 
2.5  Adding Wires to Schematic ......................................................................................................... 13 
2.6  Saving Your Design ...................................................................................................................... 14 
3  SYMBOL AND TEST CIRCUIT CREATION ............................................................................................... 15 
3.1  Creating Symbol .......................................................................................................................... 15 
3.2  Editing Symbol ............................................................................................................................ 16 
3.3  Building Test Bench ..................................................................................................................... 18 
4  SIMULATING YOUR CIRCUIT ................................................................................................................ 21 
4.1  Start the Simulation Environment .............................................................................................. 21 
4.2  Selecting Project Directory.......................................................................................................... 21 
4.3  Setup Model Library .................................................................................................................... 22 
4.4  Choosing the Desired Analysis .................................................................................................... 22 
4.5  Setup Variables ........................................................................................................................... 23 
4.6  Saving Simulation Data ............................................................................................................... 24 
4.7  Saving Output for Plotting .......................................................................................................... 24 
4.8  Viewing the Netlists .................................................................................................................... 25 
4.9  Running the Simulation ............................................................................................................... 25 
5  PHYSICAL LAYOUT ............................................................................................................................... 28 
5.1  Layout vs Symbol of CMOS Devices ............................................................................................ 28 
5.2  Starting Layout Editor ................................................................................................................. 29 
5.3  Vias .............................................................................................................................................. 31 
5.4  Changing the Grid ....................................................................................................................... 33 
5.5  Inserting and Editing Instances ................................................................................................... 34 

2 | P a g e  
 
 5.6  Drawing Shapes / Paths .............................................................................................................. 35 
5.7  Creating Pins ............................................................................................................................... 36 
6  DESIGN VERIFICATION: DRC AND LVS ................................................................................................. 38 
6.1  Performing DRC ........................................................................................................................... 38 
6.2  Performing LVS ............................................................................................................................ 40 
6.3  Performing PEX ........................................................................................................................... 41 
7  POST‐LAYOUT SIMULATION ................................................................................................................ 45 
7.1  Simulation the Extracted Cell View ............................................................................................. 45 
8  CONCLUSION ....................................................................................................................................... 46 
 

3 | P a g e  
 
1 INTRODUCTION  
This manual describes how to use Cadence IC design tools. It covers the whole design
cycle, from the front-end to the back-end, i.e., from the pre-layout design to the post-layout
design.

The manual aims to provide a guide for fresh users. Following the manual, users can start
doing analog IC design even though the users don’t have any knowledge of the tools.

An inverter is used to illustrate the whole cycle of analog IC design, and Cadence
Generic 45nm (cg45nm) kit is the technology library used for implementing the inverter. The
method stated in the manual can be applied to other type of analog circuit design.

1.1 Overview of Design Flow 
 
Figure 1 shows a typical analog IC design flow.
The design flow starts from schematic entry with the Cadence schematic capture tool –
Schematic Editor. Devices or cells from the cg45nm or other libraries are used to build your
circuit. Your design is hierarchical; therefore higher level schematics also incorporate cells
which you have already developed. The schematics which you enter at this stage therefore
typically consist of a number of base library cells and also lower level cells designed yourself.
These are described in Sections 2 and 3 of the manual.
When you have finished designing a particular circuit, you need to simulate it to ensure
that it works as expected. It would be unlikely that your circuit works as expected at the first
time so you have to repeat the cycle to improve the circuit, as shown in Figure 1, until the
circuit works satisfactorily. This must be done for each sub-circuit of your design and then for
the top level design. How to simulate and view the performance of simulation results are
presented in Sections 4 of the manual.
When the performance of the circuit is satisfactory, it is ready to start the physical design
or layout of the circuit. The layout starts with the cell or device placement. Once the cells have
been placed, routing can be carried out. Routing connects the cells/device of the design.
After finishing placement and routing, the layout has to go through the Design Rule Check
(DRC) with rule decks provided by PDK provider, to ensure that there is no design rule
violation in the layout. The layout has to be rectified accordingly to the rules’ requirement till
it passes DRC.
Upon a successful DRC, it is Layout-versus-Schematic (LVS) check, to assure that all
connections in the layout are correct. The layout has to be amended accordingly to the
schematic If LVS doesn’t pass. DRC has to be done whenever layout is changed. The process
is repeated until the LVS passes.

4 | P a g e  
 
 Figure 1. Analog IC Design Flow

5 | P a g e  
 
 The next step is parasitic extraction (PEX) to get the extracted view of the circuit, which is
used for post–layout simulation. The extracted view includes the parasitic effects in both the
instances/devices and the required wiring interconnects of the circuit.
Following DRC, LVS and PEX, it is post-layout simulation. The post-layout simulation is
essential to make sure that the circuit with the extra parasitic parameters functions well and
still meet the design specifications. If the performance of the post-layout simulation is not
acceptable, back to the stage of schematic entry to check the circuit. Basically, re-design the
circuit is necessary. Repeat the whole flow until the results of the post-layout simulation meet
the design specifications.
If everything is satisfactory, the next stage is GDSII Generation. It generates a file which
depicts the low level geometry of layout. GDSII format is industry standard format suitable for
a semiconductor company to fabricate and manufacture the chip of layout. This is briefed in
the last section of the manual.

1.2 Getting Started with Cadence 
 
Upon logging into your account, you will be brought to the Linux Desktop Environment.
Right click on the desktop and click Open Terminal to open a “window” on the desktop. This
window is the Linux command line prompt at which you can run Linux commands. After
running a Linux command, this window also shows the output of the command.
The following steps show how to start Cadence with cg45nm kit.
A. Create a working directory - project (it can be any name as you like) with the
command:
mkdir project
where mkdir is Linux command and the project is the directory name;
B. Enter the working directory with the command:
cd project
where the cd is the Linux command;
C. Type the followings commands to do the environment setup for using Cadence Generic
45nm PDK.
cp /app11/cg45nm/USERS/cds.lib .
cp /app11/cg45nm/USERS/assura_tech.lib .
cp /app11/cg45nm/USERS/pvtech.lib .
D. Start cadence in the working directory – project with the following command:
virtuoso &
where virtuoso is the command to start Cadence IC design tool.
Now, Cadence tools are successfully started. Keeps only the Command Input Window
(CIW) which is shown in Figure 2.

6 | P a g e  
 
 Figure 2. CIW Window
Do not close this CIW and try to keep it in view whenever you are using Cadence. Error
messages and output from some of the tools are always sent to the CIW. If something doesn't
appear to be working, always check the CIW for error messages. In addition, the CIW allows
the user great control over Cadence by interpreting skill commands which are typed into it.
E. In the CIW, select ToolsLibrary Manager. The Library Manager pop up as in
Figure 3. The Library Manager is where you create, add, copy, delete and organize
your libraries and cell views.

Figure 3. Library Manager Window

7 | P a g e  
 
 You can see that the library gpdk045 appears in the Library column of the library
manager.
Now, you have started Cadence tool and loaded the cg45nm kit successfully. There are some
documents in /app11/cg45nm/ gpdk045_v4_0/docs, and you can always refer to these
documents for the information such as devices, device models, DRC rules and others related
to cg45nm kit.
Next time, you need only to repeat the steps B and D, for launching Cadence virtuoso and
doing your project.

1.3 Using Online Help 
 
Cadence provides a comprehensive online manuals for all Cadence tools. You can launch
the online help by typing the following command at the Linux prompt.
cdnshelp
This invokes the online software manuals. Alternately, there is a help menu on each Cadence
window. Manual which is related to that window related will pop-up once clicking on the help
button.

1.4 Exit Cadence 

To exit Cadence, just click on the cross sign X or FileExit in CIW. It is necessary to exit
Cadence when it is not in use. Your library file would be locked or cannot edited next time if
Cadence was not exited properly.

8 | P a g e  
 
2 SCHEMATIC ENTRY 
Now that Cadence is running, you are almost ready to start entering schematics. However,
you must first create a library which will be used to store all the parts of your design. Then,
schematic can be created in the library.
2.1 Creating a New Design Library 
A. In the Library Manager window, select FileNewLibrary. New Library form
pops up as shown in Figure 4.
B. In the New Library form referring to Figure 4, key in your design library name
(example: test) in the field of Name, and then click Ok.
C. Click Ok in the pop-up window - the Technology File for New Library, referring to
Figure 5.
D. Choose gpdk045 in the Attach Library to Technology Library form, referring to
Figure 6, and then click Ok.

Figure 4. New Library Form

Figure 5. Technology File for New Library Form

9 | P a g e  
 
 Figure 6. Attach Library to Technology File Form
A new library, named test, should appear in your Library Manager window.

2.2  Creating a Schematic Cellview  
 
A. In Library Manager, select the Library where you would like to create a schematic. Then,
select FileNewCell View.
B. Set up the New File form as Figure 7

Figure 7. Create CellView

C. Click OK when done. A blank schematic window for the "inv" (your cell name)
schematic appears.
Explore the functions available by putting your mouse over the toolbar and fixed menu icons.

10 | P a g e  
 
 In addition, note that some of the menu selections have alphabets listed to the right of
them. These are bind-key or shortcut-key definitions which are very useful in the long run.
Test them out during the schematic drawing in subsequent steps.

2.3 Adding Components to Schematic 
 
Figure 8 shows the schematic which you are going to patch, and the property of each
component is listed in Table 1.

Figure 8. Inverter Circuit

Tabel 1. Component Properties of Figure 8: Inverter Circuit

Components  Library Name  Cell Name  Properties 
PMOS   gpdk045  pmos1v  l:45nm w:120nm (default size)   
NMOS   gpdk045  nmos1v  l:45nm w:120nm (default size) 

Here is the example on how to add component instances by placing cell views from
libraries. Type “i” bind-key or select CreateInstance in the schematic window or click
on the menu bar to display Add Instance form. Then in the Add Instance window, select
gpdk045 as Library, choose the NMOS transistor by selecting nmos1v in Cell and also
choose symbol as View, as shown in Figure 9.

11 | P a g e  
 
 Figure 9. Add Instance Form
Similarly, add the pmos1v into the schematic. As an example, here we just keep all the
parameters as default.
If you place a component with the wrong parameter values, select the component and type
“q” bindkey or use the EditPropertiesObjects command to change the parameters. Use
the EditMove command or type “m” if you place components in the wrong location.

2.4 Adding Pins to Schematic 
 
You must place I/O pins in your schematic to identify the inputs and the outputs. A pin can
be an input, output or an input-output (bi-directional) pin.
12 | P a g e  
 
 Type “p” or select Add Pin from inv Schematic Window or click the Pin fixed menu
icon in the schematic window. The Add Pin form appears as Figure 10.

Figure 10. Add Pin Form

Click Hide and move you cursor to the Schematic Window. Place pins at the correct places and
click right mouse key to rotate the pin if necessary.
Add pins according to Table 2, paying attention to the direction.
Table 2. Pin Names and Direction of inv

Pin Names Direction

Vin Input
Vout Output
VDD, GND Input-Output

Caution: Do not use the add component form to place schematic pins.

2.5  Adding Wires to Schematic 
 
Add wires to connect the components and pins in the design.
A. Type “w” or select Add Wire (narrow) in Schematic Window or click (narrow)
fixed menu icon.
B. In the schematic window, click on a pin of one of your components as the first point
for your wiring. A diamond shape appears over the starting point of this wire.

13 | P a g e  
 
 C. Follow the prompts at the bottom of the design window and click left mouse key on
the destination point for your wire.
D. Continue wiring the schematic. When done wiring, press Esc with your cursor in the
schematic window to cancel wiring.

2.6 Saving Your Design 
 
Check the design to ensure that it is correct and save the design.
A. Click the Check and Save icon in the schematic window.
B. Observe the CIW output area, for the information of the check and save action.

14 | P a g e  
 
3 SYMBOL AND TEST CIRCUIT CREATION 
Symbols are useful when creating designs as it is impractical to show every transistor on the
top level schematic. Instead, the symbols of cells are created in order to instantiate them in the
higher level schematics and make them more readable (i.e. hierarchical designs). Create a symbol
for your design so you can place it in a test circuit for simulation.

3.1 Creating Symbol 

A. In the inv schematic window, select Create  Cellview  From Cellview. Cellview
From Cellview pops up as shown in Figure 11.

Figure 11. Cellview From Cellview Form

B. Click OK in the Cellview From Cellview form. The Symbol Generation Options form
appears as Figure 12. Enter the information listed in Table 3 for the symbol.

Table 3: Pin Spectifications

Left Pins : Vin
Right Pins : Vout
Top Pins: VDD
Bottom Pins: GND
 

15 | P a g e  
 
  
 
Figure 12. Symbol Generation Options Form

C. Click OK in the Symbol Generation Options form. A window with a symbol created
automatically by the tools pops up, referring to Figure 13.

 
Figure 13.  Symbol Generated Automatically 
 
D. Observe the CIW output pane and note the messages stating Adding ‘CDF
information ...’.

3.2 Editing Symbol 

You can modify the symbol to have a more meaningful shape for easy recognition.

16 | P a g e  
 
 A. Move your cursor over the symbol, until the entire green rectangle is highlighted. Click
left to select it.
B. Click Delete icon in the symbol window to delete the green rectangle.
C. Select CreateShapePolygon. Follow the prompts at the bottom of the symbol, and
draw the triangle shown in Figure 14.
D. Type “m” or click Move icon in the symbol window, move the pins to the final
destination.
E. Select [@partName], and use EditPropertiesObject to change it to inverter as
shown in Figure 14.

Figure 14. Edit Object Properties Form

F. Save your edited symbol view. The final symbol is shown in Figure 15.

Figure 15. Symbol of inv

17 | P a g e  
 
3.3 Building Test Bench 

To test the inverter that you have just built, you need to create a test bench. This test bench
will also be used during the post-layout simulation.

Creating an inv_test schematic cellview with the below information, following the steps
listed in Section 2 – SCHEMATIC ENTRY. The test bench is as shown in Figure 17.
Library Name : test
Cell Name : inv_test
View Name : schematic

Library Name  Cell Name Properties

test  inv_test 
analogLib  Vdc  VDD 
analogLib  vpulse  Referring to Figure 16         
analogLib  gnd GND
analogLib  cap  1f F

18 | P a g e  
 
 Figure 16. Vpulse Form

19 | P a g e  
 
 Figure 17. Test Bench – inv_test for inv Circuit

Note:
There are wire names Vin and Vout in Figure 17. These can be created by clicking on
CreateWire Name on the inv_test schematic window. Key in Vin Vout in the Names field of
the Add Wire Name form, and then click Hide. Moving your mouse to the schematic window,
click the wire where you want it to be named in the same sequence as typing the names in the
Names field.

20 | P a g e  
 
4 SIMULATING YOUR CIRCUIT 
Before starting the simulation, make sure that the schematic (inv_test) is open, then perform
the following steps.
4.1 Start the Simulation Environment 
In your schematic window, select Launch ADE L. The Analog Design Environment
(ADE) window appears as shown in Figure 18.

Figure 18. ADE Window

4.2 Selecting Project Directory 

In the ADE window, select SetupSimulator/ Directory/ Host. A Choosing Simulator

form appears as Figure 19. In the Project Directory blank, type in /var/tmp/(desired folder
name) to save your simulation files in the /var/tmp directory on the local server. Click OK to
confirm.

Figure 19. Choosing Simulator/Directory/Host Form

21 | P a g e  
 
 As each user account has a limited quota, this helps to conserve memory space in your account
and prevents you from exceeding your account quota. However, note that contents in this folder is
deleted periodically every 30 days automatically.

4.3 Setup Model Library  

In the ADE window, select SetupModel Libraries. The Model Library setup form
appears. Double click the column of section, and then click the down arrow to choose tt which is
typical N and P model parameters. The model library setup for the inv_test circuit is shown in
Figure 20. Click ok on the setup form to finish the settings.
The information of models can be found in
/app11/cg45nm/gpdk045_v4_0/docs/gpdk045_pdk_referenceManual.pdf.

Figure 20. Model Library Setup for inv_test

4.4 Choosing the Desired Analysis 
In the ADE window, click the Choose Analyses icon . The Choosing Analyses form
appears. Cadence ADE is able to run several types of simulations consecutively. You are then able
to view the signals from different simulations at the same time. In this example, we will do
transient analysis, so we shall setup transient analyses through the ADE as Figure 21.

22 | P a g e  
 
 Figure 21. Setup for Transient Analyses

4.5 Setup Variables 
There is a variable, VDD, in the inv_test circuit. We need to set a value to it before starting
simulation.
In the ADE window, click Variables. Enter the name as the variable name VDD, then set the value
as 1.1, and finally click Ok. Please take note that 1.1v is the nominal voltage for this technology.

Figure 22. Editing Design Variables

23 | P a g e  
 
4.6 Saving Simulation Data 

The simulation environment is configured to save all node voltages in the design by default.
In larger designs, where saving all of the data requires too much disk space, you can select a
specific set of node to save. Following steps show you how to select terminals to save.
A. In the ADE window, select OutputsSave All.
B. The Keep Options form appears. Do not modify the form at this time. However, if you
need to save less data, under the first option “Select signals to output”, Click “selected”.

4.7 Saving Output for Plotting 

Select the signals that you would like to observe.

A. Select OutputsTo Be PlottedSelect On Design.
B. Note that if you click on wires / nets, voltage signals are selected. If you click on
connection nodes, currents flowing through that note and into the component are saved.
C. Follow the prompts at the bottom of the schematic window. Click on the output wires
labeled with Vout and Vin (select the wire that you want to monitor).
D. Press Esc with your cursor in the schematic window when finished.
Now you have set up the simulation environment which as shown in Figure 23. You can save
the simulation state. This saves all the information such as the Model Path, outputs, analyses,
environment options, and variables so that you do not need to set these parameters the next time
again.

Figure 23. ADE window with completed settings

24 | P a g e  
 
 In the ADE window, select SessionSave State. Tick Cellview and then click OK. You can
recall your settings by selecting SessionLoad State.

4.8 Viewing the Netlists 
 
Sometimes, you need to view the netlist of your circuit or design. You can do so through
the ADE, select SimulationNetlistCreate / Display / Recreate.
If there are any errors encountered during this step, check the messages in the CIW and retrace
your steps to see that all data was entered properly.

4.9 Running the Simulation 
 
Select SimulationNetlist and Run to start the simulation or click on the Run
Simulation icon in the Simulation Window. After the simulation is done, a waveform window
will pop up showing the simulation results as Figure 24.

Click on the waveform window to separate Vin and Vout.

You can create a horizontal or vertical marker by clicking Marker on the waveform window.
For example, creating a horizontal marker on Figure 24 with put Y Postion at 0.5*VDD=550mV,
and then zoom in. The waveform window will look like Figure 25. Delays of the inverter could be
found from the reading on the marker.

25 | P a g e  
 
 Figure 24. Output of Simulation

26 | P a g e  
 
 Figure 25. Waveform with Marker.
Explore the icons on the toolbar as well as the various items on the menu. Try to add markers
as that is something that will be used often during your simulations. You can also update the
titles and labels on your plot to make them easy to read or more meaningful, if necessary.
*Quick Tip : Shortcuts “a” and “b” to place a delta marker where you observe the difference
between two points. What does shortcuts “v” and “h” do? 

There are many other functions available in the calculator tool, explore and play around with
them.
By now, you have finished pre-layout simulation (schematic level simulation). Next, you need
to draw the layout of the inverter circuit and then do post-layout simulation to check your circuit
performance.

27 | P a g e  
 
5 PHYSICAL LAYOUT 
 
By now, you should know how to create and simulate your circuit. Once the performance of
your design is satisfactory, the next step in the process of making an integrated circuit chip is to
create a layout. What is a layout? A layout is basically a drawing of the masks from which your
design will be fabricated. Therefore, layout is just as critical as specifying the parameters of your
devices.
Before we get into the layout, first you need to understand the design rules for layout. Design
rules give guidelines for generating layouts. They dictate spaces between wells, sizes of contacts,
minimum spacing between a poly and a metal, and many other similar rules.
Design rules are essential to any successful layout design, since they account for the various
allowances that need to be given during actual fabrication and to account for the sizes and the steps
involved in generating masks for the final layout. Note that the layout is very much process
dependent, since every process has a certain fixed number of available masks for layout and
fabrication.
You may find more details on the Design Rules Manual (DRM):  
/app11/cg45nm/gpdk045_v_4_0/docs/gpdk045_drc.pdf 
5.1 Layout vs Symbol of CMOS Devices 
 
In this section, we look at only three devices: nmos1v and pmos1v. Check the process
document, you can find the information for other devices.
Figure 26 shows the nmos1v device. From layout view, you can see that the terminal B is the
black background of the layout window.

D S

G
B 
Figure 26. Layout vs Symbol of NMOS

Figure 27 shows the pmos1v device, which looks similar to NMOS device but with P type
implant (orange-stripe layer) and N-well (purple surrounding layer).

28 | P a g e  
 
 Figure 27. Layout vs Symbol of PMOS  

5.2 Starting Layout Editor 
 
Now we are going to create a new layout in the cell “inv” in “test” library.
A. In Library Manager, select FileNewCellview ... A Create New File form pops up.
B. Select "test" as Library Name; enter "inv" as Cell Name, "layout" as View Name.
C. Choose Open with Layout XL, and then click OK.

Figure 28. Create Cellview – Layout

29 | P a g e  
 
 Useful layer 
selection 
feature

Figure 29. Layout Window

Cell "inv" with "layout" view in library "test" will be created. It is opened up automatically,
followed by inv schematic window, as shown in Figure 29. The layout editor contains two main
sub-windows, namely the Layers sub-window on the left and Layout Editing window on the right.
Notice the Layers sub-window on the left side of the layout view. This sub-window displays
the fabrication layers defined in the technology. You can find the cross sectional profile in the
process documents.
Each layer is represented by a different color and pattern for easier differentiation. The black
background on the right can be interpreted as the p-substrate of the wafer.
To hide a layer, use the middle scroll button to click on a layer. To disable a layer from use,
use the right mouse button.
You might notice that some layer names appear more than once in the Layers sub-window.
For example, Metal1 appears two times: one as Metal1 drawing, the other as Metal1 pin. Metal1
drawing is a layer with drawing purpose, and such layers with drawing purposes will be
fabricated in the mask. The pin layers are symbolic layers and serve to indicate position of I/O
pins and define net names. Such layers are not part of the mask layout and will not be fabricated.

30 | P a g e  
 
5.3 Vias 
 
Vias are used to connect between layers, much like those used in PCB design.
There are different types of vias for different layer pairs. Normally a via is only for connecting
two successive layers, e.g., Metal 1 and Metal 2. In case there is a metal jump between more than
two layers, via stacking is required.
In the layout window, click CreateVia or type “o” to bring up the via menu. Place the vias
on the layout editing window, you can observe the layers that are involved in each type of via.
Experiment with the different modes and configurations in the via menu to create arrays and
stacks of vias as well. For example,
A. Click on CreateVia, the Create Via window pops up as figure 30 shows.
B. Choose M1_PO under Via Definition, and click on the layout window to place it and
then press Esc button to stop the placing. You can change the number of Rows and
Columns on the Create Via form.
C. To view the layers of M1_PO, click to select it first and then press Shift + f key. Observe
the via appears different.
D. To check the layers used in via M1_PO, select it and then click Edit
HierarchyFlatten as shown in figure 31. Click OK on the pop-up form shown in
Figure 32.
E. Now, you can separate the layers and check layers’ property to find out the layers’ name.
Via M1_PO connects layers Metal 1 and Poly as shown in Figure 33.
Try to explore different options (Rows, Columns, Stack, etc.) under via menu by yourself, this
will be very helpful for layout drawing.

Figure 30. Create Via windows

31 | P a g e  
 
 Figure 31. Edit Via

Figure 32. Flatten Form

32 | P a g e  
 
 Figure 33. Via M1_PO
The M1_PSUB and M1_NWELL contacts are substrate and n-well contacts that are used to
connect the bulks of the NMOS and PMOS respectively. For the inverter circuit used in this
manual, the bulks of the NMOS and PMOS need to be connected to ground (GND) and VDD
respectively.

5.4 Changing the Grid 
 
In Figure 29, the black window on the right is the layout editing window. The position of the
cursor in layout editing window is indicated by the coordinate showed on the top right corner of
the window after X: and Y:. The unit here is "µm". Move your cursor around the editing window
and see the X: Y: values change with step size 0.1. Change the step size to 0.005 as that is the
minimum step size for this technology.

From Layout Editing window pull down menu, select Options  Display... change "X Snap
Spacing" and "Y Snap Spacing" to 0.005 then click on "OK". Now move the cursor around the
editing window again, you will see the X: Y: values change with step size 0.005.

There are raw grid and fine grid (as small dots) on the window background. If you cannot
clearly see the raw grids, from pull down menu select Window  Zoom out by 2

In addition to pull down menu and bind key "z", "Zoom Out" is also listed in the picture tool
bar to the left of the window. Find it and try it out.

Also you may use up, down, left, and right arrows to move around the design window. You
will need to use "Zoom in" and "Zoom out" and those arrows many times throughout your design
process. So it's not a bad idea to practice them a little bit now.

To save and close the cell view, from Virtuoso Editing window, Select Design  Save.
 
33 | P a g e  
 
5.5 Inserting and Editing Instances 
 
Now, we can begin drawing the layout. Open your schematic so you may refer to it at all
times, if it is not opened.
A. Select Create  Instance or type “i” to insert the layout of instances. They can be
found in the same library and cell name as the schematic symbol.
B. Figure 34 is an example of inserting the layout of nmos4. Edit the width and length so
they correspond to the schematic design. Note that the view is layout, not symbol.

Figure 34. Add NMOS Device with View – Layout

C. Place them and type Shift+F to reveal all the layers.

D. To change the location of instances, go to Edit  Move or type the “m” bind key and
click on the component. If you need to rotate or flip the layout, hit F3 and the Move
Menu will appear as Figure 35. You can rotate and flip the layouts through this
convenient side menu.

34 | P a g e  
 
  
Figure 35. Move Form
Figure 36 shows the layout after inserting all the instances of the inverter Circuit. Note that
there are two more instances compared to the inv Schematic in Figure 10. They are M1_NWELL
and M1_PSUB (NOTE: you can ignore the PWdummy layer), for connecting the nwell to VDD
and the p-substrate to GND respectively. The nwell is drawn with the NWELL layer, while the
p-substrate is the black background of the layout window.

 
Figure 36. Inverter Layout before Routing

5.6 Drawing Shapes / Paths 

To connect two points together, we need to draw shapes or paths. The most common shape
in a layout is rectangle. To draw rectangles

A. From the layer window select a layer by clicking left on it. You will see the selected layer
surrounded by a border.

35 | P a g e  
 
 B . From Virtuoso Editing window pull down menu, click left to select Create
Rectangle or type bind key “r”.
C. In the layout design window click left on the first corner of the rectangle, then click left
on the second corner. A rectangle is formed.
D. If this is not the rectangle you want, type “u” or select Edit Undo to undo the action.
E. If you want to draw rectangle on another layer, in LSW click left on the layer to change
the drawing layer then repeat step C.
F. If you have finished drawing rectangles, hit <Esc> on the key board to exit from "Create
Rectangle" command.

You can use Create  Polygon to create other shapes. The procedures are the same
as creating rectangle.

Similar steps can be used for Create Path, type the “P” bind key to try it out.

Connect all the points in the layout according to the schematic. Remember to
connect the bulks of the NMOS and PMOS to GND and VDD respectively.

5.7 Creating Pins 

The final part of the layout is to create the corresponding pins.

A. Select Metal1 pin in the Layers sub-window on the left side of the layout view,
first.
B. To create the pins, go to Create Pin bring up the form as shown in Figure 37.
C. Type the pin name in the Terminal Names field and choose input in the I/O
Type option which must be exactly the same as that in the schematic.
D. Place the pin on the corresponding part of the layout. Check the schematic to ensure you
put at the right place.
E. Repeat the above steps, steps A-D, to finish creating all the pins drawn on the schematic,
referring to Table 2 for the I/O Type option.

36 | P a g e  
 
 Figure 37. Create Label Form
Your completed layout may look like the one shown in Figure 38.

Figure 38. Inverter Layout after Routing

37 | P a g e  
 
6 DESIGN VERIFICATION: DRC AND LVS 
You have completed your layout of the inverter. The created mask layout must conform to
a complex set of design rules, in order to ensure a low probability of fabrication defects.

A tool built into the Layout Editor, called Design Rule Check, is used to detect any design
rule violations during and after the mask layout design. The detected errors are displayed on the
layout editor window as error markers, and the corresponding rule is also displayed in a separate
window.
The designer must perform DRC (in a large design, DRC is usually performed frequently - before
the entire design is completed), and make sure that all layout errors are eventually removed from
the mask layout, before the final design is suitable for fabrication.

After completing DRC, the layout should be checked against the schematic circuit
description created earlier. This Layout-versus-Schematic (LVS) Check will compare the
original netlist with the one from the layout and prove that the two networks are indeed
equivalent.

The LVS step provides an additional level of confidence for the integrity of the design, and
ensures that the mask layout is a correct realization of the intended circuit topology. Note that
the LVS check only guarantees topological match: A successful LVS will not guarantee that the
extracted circuit will actually satisfy the performance requirements. Any errors that may show
up during LVS (such as unintended connections between transistors, or missing
connections/devices, etc.) should be corrected in the mask layout.

Finally, after passing these two checks, we run the PEX or Parasitic Extraction. By extracting
all the parasitic capacitors and resistors, we obtain a netlist corresponding to the layout. To test
the performance of the circuit now, we run a post-layout simulation with the extracted netlist.
Note that the PEX step must be repeated every time you modify the mask layout.

6.1 Performing DRC 
 
A. From the main menu, select Assura Run DRC. This brings out a DRC form as shown
in Figure 39.

38 | P a g e  
 
 Figure 39. DRC Form

B. Change the Technology to gpdk045_av.

C. Click OK and the following window will pop up if there are no DRC errors after finishing.

Figure 40. DRC Windows

39 | P a g e  
 
 D. In case there are DRC errors, Error Layer Window as shown in Figure 40 will pop up. By
clicking on the error, you get more details on the description and the location of the error
in your layout.
E. By clicking on the highlighted arrows in Figure 40, the layout window will automatically
zoom to the error location, allowing you to edit the layout accordingly.
Density errors can be ignored in the initial stage of design.

6.2 Performing LVS 
 
A. From the main menu, select Assura  Run LVS. This brings out a LVS form as shown
in Figure 41.

Figure 41. LVS form

40 | P a g e  
 
 B. Change the Technology according to Figure 41, then click OK.
C. If the layout indeed corresponds to the schematic, you get a similar window as shown in
Figure 42 to indicate that you have passed the LVS.

Figure 42. Pass LVS

D. If not, edit the layout, run DRC and LVS again. Whenever layout is changed, DRC must
be done before running LVS.

6.3  Performing PEX 
 
A. From the main menu of layout window, select QRC  Run Assura - Quantus QRC.
This brings out QRC (Assura) Parasitic Extraction Run Form.
B. Choose gpdk045_av under Technology, rcx_typical under RuleSet, Extracted View for
Output, and av_extracted for View, referring to Figure 43.

41 | P a g e  
 
 Figure 43. QRC (Assura) Parasitic Extraction Run Form

C. Click on Extraction tab on the Parasitic Extraction Run Form. Set it exactly as the one
shown in Figure 44.

42 | P a g e  
 
 Figure 44. Extraction option

D. Click on Netlisting tab on the Parasitic Extraction Run Form. Ensure the first three lines
are set to Do Not Include, referring to Figure 45.

43 | P a g e  
 
 Figure 45. Netlisting Options

E. Click OK on the QRC (Assura) Parasitic Extraction Run Form after finishing the settings
following Figures 43, 44 and 45. Parasitic extraction is started.

F. Go to the library manager and you will observe that there is now an additional cellview in
your “inv” cell named “av_extracted”.

44 | P a g e  
 
7 POST‐LAYOUT SIMULATION 
 
The electrical performance of a full-custom design can be best analyzed by performing a post-
layout simulation on the extracted circuit netlist. At this point, the designer should have a complete
mask layout of the intended circuit/system, and should have passed the DRC and LVS steps with
no violations. The detailed (transistor-level) simulation performed using the extracted net-list will
provide a clear assessment of the circuit speed, the influence of circuit parasitics (such as parasitic
capacitances and resistances), and any glitches that may occur due to signal delay mismatches.
If the results of post-layout simulation are not satisfactory, the designer should modify some
of the transistor dimensions and/or the circuit topology, in order to achieve the desired circuit
performance under "realistic" conditions, i.e., taking into account all of the circuit parasitics. This
may require multiple iterations on the design, until the post-layout simulation results satisfy the
original design requirements.
Finally, note that a satisfactory result in post-layout simulation is still no guarantee for a
completely successful product; the actual performance of the chip can only be verified by testing
the fabricated prototype. Even though the parasitic extraction step is used to identify the realistic
circuit conditions to a large degree from the actual mask layout, most of the extraction routines
and the simulation models used in modern design tools have inevitable numerical limitations. This
should always be one of the main design considerations, from the very beginning.

7.1 Simulation the Extracted Cell View 
 
After a successful LVS, you will have two main cell views for the same circuit. The first one
is the schematic, which is your initial (ideal) design, the second is the extracted view, that is based
on the layout and in addition to the basic circuit includes all the layout associated parasitic effects.
In this chapter, you are going to re-run the simulation for "inv", but we will make the simulator
use the extracted view instead of the schematic cell view. Open your test bench schematic that you
used to simulate the inverter design earlier.
A. Start the Analog Design Environment. Load the state that you saved in the earlier
simulation.
B. Go to Setup Environment. Insert av_extracted in Switch View List as the first entry.

45 | P a g e  
 
 Figure 46. Environment Options Form
C. The Switch View List is an ordered list of cell views that contain information that can be
simulated. The simulator (or in fact the netlister) will search until it finds one of these
cellviews. The default entry does not contain an extracted cellview. You need to add an
entry for extracted cellview – av_extracted (name of the cell view) in front of the spectre
cellview.
D. As a result of this modification, the simulator will use the av_extracted view of the cell, if
one is available. The final form is like Figure 46.
From this point, the simulation will continue just as it has been described in Sections 4.8 and
4.9 of this manual, except for the fact that the results will now include parasitic effects from the
actual layout.
Following the flow of Figure 1, your design would be completed if it satisfies the design
specifications.

8    CONCLUSION 
Analog IC design method with Cadence IC 6 – Virtuoso is presented in this manual. The flow
as shown in Figure 1 is iterative and stops only when the design is satisfactory. The details of each
stage is described. I wish that the manual is helpful for users who want to start learning analog IC
design. You are welcome to feedback to at any time, to improve the manual so that more users
would be benefited.

46 | P a g e