Professional Documents
Culture Documents
Unit II
Mrs. T.Sunitha, Asst.Prof
Dept. of Electronics and Telematics Eng.
GNITS, Hyderabad
These rules usually specify the minimum allowable line widths for
physical objects on-chip
• Objective:
To achieve a high overall yield and reliability
while using the smallest possible silicon area.
Ref [1]
3 October 2020 VLSI Design Ch. 3 Part 2 5
Design Rules
2. Micron rules:
In which the layout constraints such as minimum
feature sizes and minimum allowable spacing, are stated in
terms of absolute dimensions (in micrometers).
Ref [R6]
diff-poly spacing l
Fig. 3.6
Design rules
for wires
nMOS and CMOS
Ref [1]
Ref [1]
Contact Cuts :
Electrical connection can be established between
layers by special structures called contact cuts.
Ref [1]
Ref [1]
3 October 2020 VLSI Design Ch. 3 Part 2 22
Butting Contact
• The gate and diffusion of NMOS device can be
connected by a butting contact.
Ref [1]
Butting Contacts
• 2λx2λ cut is made to each of the layers to be connected
• The layers are butted together so that the two contacts are
contiguous
• Contact is made through metal deposition
Metal 2 Via
Metal 1 Contact
n-diffusion
Ref [1]
3 October 2020 VLSI Design Ch. 3 Part 2 29
Design Rules and Layout
Ref [1]
3 October 2020 VLSI Design Ch. 3 Part 2 30
Design Rules and Layout
Ref [1]
Fig. 3.11. particular rules for p-well CMOS process
3 October 2020 VLSI Design Ch. 3 Part 2 33
Design Rules and Layout
Design Rules for Contacts/Vias
Ref [1]
Ref [1]
3 October 2020 VLSI Design Ch. 3 Part 2 36