Analog and Digital VLSI Design

EEE F313/INSTR F313

Lecture 7: Design Rules and Packaging

 CMOS inverter

P Diffusion Region N Diffusion Region

p well

Layout
 CMOS Latch Up
When it is in the state of latch up, it draws a
large current from VDD, but does not function
in response to input
Heat dissipation destroys the die permanently
This happens due to the formation of thyristor
like structure as a result of parasitic BJTs
 Design Rules
Interface between the circuit designer and process
engineer

Circuit Designer: Compact designs leading to higher performance and

high circuit density

Process Engineer: Reproducible and high yield process

Design rules attempts to satisfy both

 Design Rules

Guidelines for constructing process masks

 Design Rules

Unit dimension: minimum line width

Minimum mask dimension that can be safely

transferred to the semiconductor material
(minimum resolution)

scalable design rules: lambda parameter

(compatibility)
micron rules: absolute dimensions
 Design Rules

A complete set of rules include

set of layers
intra-layer: relations between objects in the same layer
inter-layer: relations between objects on different
layers
 Layer Representation
Substrates and Wells

Diffusion Regions
Also called active areas

Polysilicon layers
Contact and via layers for
interlayer connections
Metal Interconnect layers
 Intra layer design rules
Minimum dimensions (e.g., widths) of objects on each
layer to maintain that object after fab
minimum line width is set by the resolution of the patterning
process (photolithography)

0.3 micron
 Intra layer design rules
Minimum spaces between objects (that are not
related) on the same layer to ensure they will not short
after fab

0.3 micron
0.15
0.3 micron
0.15
Intra layer design rules
 Inter layer design rules
More Complex since multiple layers are
involved

Clear understanding of 2D layout to 3D reality

of actual device required
 Inter layer design rules
Transistor Rules
Transistor formed by overlap of active and the
Polysilicon layers

3
2

5
 Inter layer design rules
Well and substrate contacts
Well and substrate should be adequately connected to supply

Why is this so Important ????

Numerous substrate/well contacts spread over complete region

To establish ohmic contact between supply rail and a p

material(n material), p+ (n+) diffusion layer provided
 Design Rule Checker
Ensuring that none of the design rules are violated is
fundamental requirement

Automation required

Computer aided Design-Rule Checking (DRC) is integral

part of design cycle

Some tools even perform on-line DRC

 Packaging ICs
IC pakaging plays fundamental role

Increasing complexity of chip also contributes to

increase in number of I/O pins

Rents rule
P = K x G
P is number if I/O pins to the chip

K is avg number of I/Os per gate

G is number of gates
is rents exponent and varies between 0.1-0.7
 Good Package
Electrical Requirements Low parasitic

Mechanical Requirements Reliable and robust

Thermal Requirements Efficient Heat removal

Economical Requirements Cheap

 Reading Assignments
Interconnect levels (2.4.2)

Thermal considerations in packaging (2.4.3)

Perspective-Trends in process technology (2.5)

Thank You