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Topic 1 PIC 18

Comparison of PIC Family

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0% found this document useful (0 votes)
33 views3 pages

Topic 1 PIC 18

Comparison of PIC Family

Uploaded by

Sagar Shende
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd

 Comparison of PIC12XX, PIC16XX, PIC18XX, PIC24XX and PIC32XX PIC

families
PIC12CXXX: 8-Pin, Family
The PIC12CXXX family packs Microchip’s powerful RISC-based PICmicro architecture into
8-pin DIP(Dual In-line Package) and SOIC (small outline integrated circuit) packages. These
PIC12CXXX products are available with either a 12-bit or 14-bit wide instruction set, a low
operating voltage of 2.5V, small package footprints, interrupt handling, a deeper hardware
stack, multiple channels and EEPROM data memory. All of these features provide an
intelligence level not previously available in applications because of cost or size
considerations

PIC16CXXX: 14-Bit Architecture Family


With the introduction of new PIC16CXXX family members, Microchip now provides the
industry’s highest performance Analog-to-Digital Converter capability at 12-bits for an
MCU. The PIC16CXXX family offers a wide-range of options, from 18- to 68-pin packages
as well as low to high levels of peripheral integration. This family has a 14-bit wide
instruction set, interrupt handling capability and a deep, 8-level hardware stack. The
PIC16CXXX family provides the performance and versatility to meet the more demanding
requirements of today’s cost-sensitive marketplace for mid-range applications.

PIC18CXXX: 16-Bit Enhanced Architecture Family


The PIC18CXXX is a family of high performance, CMOS, fully static, 16-bit MCUs with
integrated analog-to-digital (A/D) converter. All PIC18CXXX MCUs incorporate an
advanced RISC architecture.
The PIC18CXXX has enhanced core features, 32 level-deep stack, and multiple internal and
external interrupts sources. The separate instruction and data busses of the Harvard
architecture allow a 16-bit wide instruction word with the separate 8-bit wide data. The two-
stage instruction pipeline allows all instructions to execute in a single cycle, except for
program branches, which require two cycles. A total of 77 instructions (reduced instruction
set) are available. Additionally, a large register set gives some of the architectural innovations
used to achieve a very high performance of 10 MIPS for an MCU. The PIC18CXXX family
has special features to reduce external components, thus reducing cost, enhancing system
reliability and reducing power consumption. These include programmable Low Voltage
Detect (LVD) and programmable Brown-Out Detect (BOD).

PIC24CXXX: 16-Bit Flash Architecture Family


(a)High-Performance CPU:
• Modified Harvard Architecture
• Up to 16 MIPS Operation @ 32 MHz
• 8 MHz Internal Oscillator with 4x PLL Option and
 Multiple Divide Options
• 17-Bit by 17-Bit Single-Cycle Hardware Multiplier
• 32-Bit by 16-Bit Hardware Divider
• 16-Bit x 16-Bit Working Register Array
(b) Analog Features
• 10-Bit, up to 13-Channel Analog-to-Digital Converter:
- 500 ksps conversion rate
- Conversion available during Sleep and Idle
• Dual Analog Comparators with Programmable
• Input/Output Configuration
(c) Peripheral Features
• Peripheral Pin Select (PPS):
- Allows independent I/O mapping of many peripherals
- Up to 26 available pins (44-pin devices)
• Continuous hardware integrity checking and safety interlocks prevent unintentional
configuration changes
• 8-Bit Parallel Master/Slave Port (PMP/PSP):
- Up to 16-bit multiplexed addressing, with up to
• 11 dedicated address pins on 44-pin devices
- Programmable polarity on control lines
• Hardware Real-Time Clock/Calendar (RTCC):
PIC32CXXX:
(a) Operating Conditions
• 2.3V to 3.6V, -40ºC to +105ºC, DC to 40 MHz
• 2.3V to 3.6V, -40ºC to +85ºC, DC to 50 MHz
(b) Core: 50 MHz/83 DMIPS MIPS32® M4K®
• MIPS16e® mode for up to 40% smaller code size
• Code-efficient (C and Assembly) architecture
• Single-cycle (MAC) 32x16 and two-cycle 32x32 multiply

(c) Clock Management


• 0.9% internal oscillator
• Programmable PLLs and oscillator clock sources
• Fail-Safe Clock Monitor (FSCM)
• Independent Watchdog Timer
• Fast wake-up and start-up

(d) Power Management


• Low-power management modes (Sleep and Idle)
• Integrated Power-on Reset and Brown-out Reset
• 0.5 mA/MHz dynamic current (typical)
• 44 μA IPD current (typical)
(e) Advanced Analog Features
• ADC Module:
- 10-bit 1.1 Msps rate with one S&H
- Up to 10 analog inputs on 28-pin devices and 13
• analog inputs on 44-pin devices
• Flexible and independent ADC trigger sources

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