PHD Gillon

Modelling and Characterisation
of the SOI MOSFET for MMIC Applications

Renaud GILLON
Jury
Prof. P. Sobieski (President)
Prof. D. Vanhoenacker (Promoteur)
Prof. A. Vander Vorst
Prof. J.-P. Colinge
Prof. P. Jespers
Dr Ch. Raynaud
Thèse presentee en vue de
lobtention du grade de
docteur en Sciences Appliquees
Juin 1998
UNIVERSIT
E CATHOLIQUE DE LOUVAIN
LABORATOIRE DHYPERFR
EQUENCES
Louvain-la-Neuve
Ce doctorat naurait pu exister sans letroite collaboration entre les Lab-
oratoires dHyperfrequences et de Microelectronique, mise sur pied par les
professeurs Danielle Vanhoenacker et Jean-Pierre Colinge. Je leur suis pro-
fondement reconnaissant davoir cree cet environnement de recherche riche et
stimulant. Merci, egalement, au professeur Andre Vander Vorst, responsable de
lunite, pour la qualite du cadre de travail au Laboratoire dHyperfrequences.
La trame de cette thèse est tissee de nombreux avis et conseils recueil-
lis auprès des professeurs Danielle Vanhoenacker, Jean-Pierre Colinge, Andre
Vander Vorst, Paul Jespers et Fernand Van de Wiele. Je tiens ` a leur temoigner
ici ma gratitude et à rendre hommage à leur savoir-faire. Plusieurs resultats
presentes dans cet ouvrage sont issus de discussions fructueuses avec des col-
lègues. En particulier, avec Jean-Pierre Raskin pour la modelisation et les ex-
tractions, avec Jian Chen pour les aspects technologiques, avec Isabelle Huynen
pour les lignes et les etalonnages, avec Jean-Paul Eggermont pour les ampli-
cateurs operationnels, et avec Denis Flandre, Luis Ferreira et Benjamin I n`guez
pour le modèle charge-sheet. Je les remercie tous chaleureuseme nt pour leur
disponibilite et leur aide.
Aux membres du Jury, qui ont consacre leur temps à la lecture des manu-
scrits et ont contribue à en ameliorer la qualite par leur remarques, je souhaite
exprimer ma reconnaissance.
`
A Danielle Vanhoenacker tout specialement, qui
en tant que promoteur, ma judicieusement guide et abondamment encourage.
Les travaux de recherche associes à cette thèse ont necessites de nombreuses
realisations techniques. Merci ` a Andre Crahay et à toute lequipe de fabrica-
tion de circuits integres ; à Pierrot Loumaye pour lencapsulation des puces ; ` a
Robert Platterborze pour les fabrications de circuits imprimes et pour toutes les
ameliorations apportees aux stations de caracterisation; à Hubert Sablain pour
son aide minutieuse lors des mesures sur tranche ; ` a Fran cois-Michel Plennevaux
et Christian Renaux qui ont repris le fardeau de la caracterisation. Merci, enn,
à tous les ingenieurs, techniciens et informaticiens qui ont apporte le soutien
indispensable ` a mes travaux.
Ce travail a benecie du soutien nancier de la Region Wallonne, de la
Communaute Fran caise par son programme dActions Concertees et de la
Communaute Europeenne gr ace au programme ESPRIT.
Je remercie aectueusement mon epouse pour sa patience et son courage
lors des diciles periodes dintense redaction.
Je dedie cet ouvrage ` a ceux qui mont transmis leur go ut de la technique.
Renaud
Preface
Silicon-on-insulator technology has been under development for more than
three decades. Interest in thin-lm SOI for high performance applications
dates back from the late 70s, when several commercial companies undertook
research eorts in this area. SOI remained an exotic technology, conned in
niche applications for some time, until recently, when the quest for low-voltage
performance driven by the boom in portable electronics and mobile communi-
cations brought it under the spotlight. Thin-lm SOI MOSFETs oer indeed
interesting low-voltage performances, higher speed and increased integration
density, all with simpler processing than bulk silicon MOSFETs of compa-
rable size, [1]. Many recent realisations of logic circuits, memories, and RF
circuits, [2], have conrmed both the advantages and the viability of thin-lm
SOI circuits, even in the case of very large systems.
To support the development of thin-lm SOI circuits, adequate device mod-
els must be made available concurrently with the maturation of fabrication
processes. Several models have already been proposed for thin-lm SOI MOS-
FETs, [3, 4, 5, 6, 7]. Very few of them have however been tailored to the design
of analogue microwave circuits. The majority of these models is indeed targeted
at the prediction of quasi-static characteristics, failing to account properly for
channel propagation delays which become signicant at microwave frequencies.
Some of these models do not meet the strict continuity requirements necessary
for the non-linear simulation of analogue circuits. None of the existing mod-
els deals properly with substrate coupling eects and particularly with their
inuence on the back gate at high frequencies.
This thesis concerns the development and the validation of a comprehensive
model of the thin-lm SOI n-MOSFET intended for the simulation of analogue
circuits in the microwave domain. To enable model validation at microwave
frequencies, new characterisation techniques and parameter extraction proce-
dures are proposed, which will be shown to be accurate and reliable. Finally,
the model is used to evaluate the feasibility of microwave SOI MOSFET mixers.
v
Preface
The text is structured as follows :
Chapter I : Introduction The global context of this work is presented.
The evolution of technology under the impulse of the recent boom in mobile
telecommunications is briey analysed. Silicon-on-insulator and bulk silicon
technologies are compared in the perspective of this evolution, and the specic
advantages of SOI CMOS technology for low-voltage applications are illus-
trated. The main-stream fabrication processes of SOI material are described.
Finally, several aspects of characterisation and modelling are discussed.
Chapter II : On-wafer characterisation at microwave frequencies
The scattering parameters measurement techniques developed in this work are
described. The chapter starts with an introduction to the rigorous framework
which forms the foundation of scattering parameters measurements. The cal-
ibration procedures of interest to on-wafer characterisation are reviewed, and
new reference impedance determination methods are proposed, which enable
to use powerful scattering parameters calibrations directly for the complete de-
embedding of devices integrated on any kind of wafer. The new de-embedding
strategy is shown to be more reliable than the conventional immittance correc-
tion approach.
Chapter III : Modelling fully depleted SOI MOSFETs Several mod-
els are developed with the specic needs of analogue microwave circuit design
in mind. Such issues as short-channel eects, channel propagation delays, dis-
persive behaviour of the interface states and continuity of all characteristics are
addressed. For the intrinsic device, a large-signal current and charge model,
a small-signal equivalent circuit model, and a distributed channel model at
V
DS
= 0 are proposed. The picture is completed with a small-signal equivalent
circuit accounting for device parasitics : series resistances, gate-diusion ca-
pacitances, substrate capacitances, etc. Finally, model limitations concerning
device dimensions, biasing conditions and maximum frequency are discussed.
Chapter IV : Extraction of the SOI MOSFET model parameters A
progressive extraction strategy is demonstrated which leads to the identica-
tion of the majority of model parameters. All extractions can be formulated
as optimisation problems, which are solved by selective optimisation on the
most inuencing parameters in order to minimise uncertainty. Original direct
extraction schemes are proposed as advantageous alternatives, being inherently
robust and ecient. The chapter includes numerous comparisons of predicted
and measured characteristics, providing condence in the validity of the newly
introduced models.
Chapter V : Microwave MOSFET down-conversion mixers The an-
alytical current and charge model is used to evaluate the performance of mi-
crowave mixer designs based on SOI MOSFETs. The feasibility of resistive
SOI MOSFET mixers at 2.0 GHz is established by simulations and conrmed
vi
REFERENCES
by measurements performed on basic mixing cells. The implementation of a
single-chip down-conversion stage with image rejection is presented.
References
[1] J.-P. Colinge, Silicon-on-Insulator Technology : Materials to VLSI. Boston
Dordrecht London: Kluwer Academic Publ., 2nd ed., 1997.
[2] S. R. Wilson et al., TFSOI circuit applications, in Proc. of the 8th Intl
Symp. on SOI technology and devices (S. Cristoloveanu, ed.), vol. 97-23,
pp. 359372, The Electrochemical Society, 1997.
[3] Dept of Electrical Engineering and Computer Sciences, University of Cal-
ifornia, Berkeley, BSIM3SOI v1.0 Manual, 1997.
[4] E. Arnold, Double-charge-sheet model for thin silicon-on-insulator lms,
IEEE Trans. on Electron Devices, vol. 43, pp. 21532163, Dec. 1996.
[5] B. I n`guez, L. F. Ferreira, B. Gentinne, and D. Flandre, A physically-
based C
-continuous fully-depleted SOI MOSFET model for analog ap-

plications, IEEE Trans. on Electron Devices, vol. 43, pp. 568575, Apr.
1996.
[6] C. Mallikarjun and K. N. Bhat, Numerical and charge sheet models for
thin-lm SOI MOSFETs, IEEE Trans. on Electron Devices, vol. 37,
pp. 20392051, Sept. 1990.
[7] S. Veeraraghavan and J. G. Fossum, A physical short-channel model for
the thin-lm SOI MOSFET applicable to device and circuit CAD, IEEE
Trans. on Electron Devices, vol. 35, pp. 18661875, Nov. 1988.
vii
Contents
Preface v
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
Main scientic publications xiii
List of abbreviations xvii
I Introduction I-1
I.1 RF and microwave monolithic ICs . . . . . . . . . . . . . . . . I-1
I.1.1 New driving forces . . . . . . . . . . . . . . . . . . . . . I-2
I.1.2 Technology directions . . . . . . . . . . . . . . . . . . . I-4
I.2 Competing technologies for emerging RF applications . . . . . I-8
I.2.1 Bulk MOSFETs . . . . . . . . . . . . . . . . . . . . . . I-9
I.2.2 Thin-lm SOI MOSFETs . . . . . . . . . . . . . . . . . I-13
I.2.3 Bulk bipolar transistors . . . . . . . . . . . . . . . . . . I-14
I.2.4 Thin-lm lateral bipolar SOI transistors . . . . . . . . I-14
I.2.5 Low-voltage systems-on-a-chip, the future of SOI . . . . I-16
I.3 Silicon-on-Insulator substrate technology . . . . . . . . . . . . . I-16
I.3.1 Silicon-on-sapphire . . . . . . . . . . . . . . . . . . . . . I-16
I.3.2 Separation by Implantation of Oxygen . . . . . . . . . . I-17
I.3.3 Wafer-bonding . . . . . . . . . . . . . . . . . . . . . . . I-18
I.3.4 The blooming of a SOI era ? . . . . . . . . . . . . . . . . I-19
I.4 Characterisation and modelling of MMICs . . . . . . . . . . . I-20
I.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-22
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-23
II On-wafer characterisation at microwave frequencies II-1
II.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-1
II.2 Uniform waveguides . . . . . . . . . . . . . . . . . . . . . . . . II-2
II.2.1 Modal electro-magnetic elds . . . . . . . . . . . . . . . II-2
II.2.2 Waveguide voltage and current . . . . . . . . . . . . . . II-3
ix
CONTENTS
II.2.3 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-4
II.2.4 Characteristic impedance . . . . . . . . . . . . . . . . . II-4
II.2.5 Normalisation of waveguide voltage and current . . . . . II-5
II.2.6 Transmission line equivalent circuit . . . . . . . . . . . . II-6
II.3 General waveguide circuit theory . . . . . . . . . . . . . . . . . II-7
II.3.1 Travelling wave intensities . . . . . . . . . . . . . . . . . II-7
II.3.2 Pseudo-waves . . . . . . . . . . . . . . . . . . . . . . . . II-8
II.3.3 Power-waves . . . . . . . . . . . . . . . . . . . . . . . . II-9
II.3.4 Load impedance . . . . . . . . . . . . . . . . . . . . . . II-10
II.3.5 Scattering matrix for pseudo-waves . . . . . . . . . . . . II-11
II.3.6 Transfer matrix . . . . . . . . . . . . . . . . . . . . . . . II-12
II.3.7 Immittance matrices . . . . . . . . . . . . . . . . . . . . II-13
II.3.8 Change of reference impedance . . . . . . . . . . . . . . II-14
II.4 Measurement set-up . . . . . . . . . . . . . . . . . . . . . . . . II-15
II.5 Calibration methods . . . . . . . . . . . . . . . . . . . . . . . . II-17
II.5.1 The transfer-matrix formalism . . . . . . . . . . . . . . II-18
II.5.2 SOLT procedure . . . . . . . . . . . . . . . . . . . . . . II-20
II.5.3 TAN self-calibration procedures . . . . . . . . . . . . . . II-21
II.6 Reference impedance determination . . . . . . . . . . . . . . . . II-27
II.6.1 Propagation constant measurement . . . . . . . . . . . . II-27
II.6.2 Load measurement . . . . . . . . . . . . . . . . . . . . . II-28
II.6.3 Calibration comparison . . . . . . . . . . . . . . . . . . II-31
II.7 De-embedding strategies . . . . . . . . . . . . . . . . . . . . . . II-34
II.7.1 Immittance corrections . . . . . . . . . . . . . . . . . . . II-35
II.7.2 In-situ calibration . . . . . . . . . . . . . . . . . . . . . II-36
II.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-37
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-37
IIIModelling fully depleted SOI MOSFETs III-1
III.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-1
III.1.1 The SOI MOSFET structure . . . . . . . . . . . . . . . III-3
III.1.2 Operating modes of the generic SOI MOSFET structure III-3
III.1.3 Thin-lm SOI MOSFETs . . . . . . . . . . . . . . . . . III-4
III.1.4 Splitting the device in intrinsic and extrinsic regions . . III-5
III.1.5 Requirements for a good MOSFET model for analogue circuit designIII-5
III.2 Charge-sheet models for the intrinsic device . . . . . . . . . . . III-7
III.2.1 Surface potential and charge density equations . . . . . III-8
III.2.2 A numerical charge-sheet model . . . . . . . . . . . . . III-12
III.2.3 An analytical approximate charge-sheet model . . . . . III-13
III.2.4 A dynamic model for the interface traps . . . . . . . . . III-16
III.2.5 Short channel eects . . . . . . . . . . . . . . . . . . . . III-17
III.3 Static conduction current . . . . . . . . . . . . . . . . . . . . . III-20
III.3.1 Carrier velocity . . . . . . . . . . . . . . . . . . . . . . . III-20
III.3.2 Triode operation . . . . . . . . . . . . . . . . . . . . . . III-21
III.3.3 Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . III-23
III.3.4 Unied model . . . . . . . . . . . . . . . . . . . . . . . . III-28
III.4 Dynamic currents . . . . . . . . . . . . . . . . . . . . . . . . . . III-30
x
CONTENTS
III.4.1 Surface potential prole . . . . . . . . . . . . . . . . . . III-31
III.4.2 Front-gate charge . . . . . . . . . . . . . . . . . . . . . . III-32
III.4.3 Back-gate charge . . . . . . . . . . . . . . . . . . . . . . III-34
III.4.4 Wards channel-charge partitioning scheme . . . . . . . III-34
III.4.5 Drain and source charges . . . . . . . . . . . . . . . . . III-35
III.4.6 Alternative formulation of the charge model . . . . . . . III-36
III.5 Operation at microwave frequencies . . . . . . . . . . . . . . . . III-38
III.5.1 The non-quasi-static small-signal model topology . . . . III-39
III.5.2 The distributed channel model at V
DS
= 0 . . . . . . . . III-41
III.5.3 A non-quasi-static large-signal channel model . . . . . . III-44
III.6 Small-signal model for the extrinsic device . . . . . . . . . . . . III-46
III.6.1 Diusion and contact resistances . . . . . . . . . . . . . III-46
III.6.2 Parasitic capacitances . . . . . . . . . . . . . . . . . . . III-47
III.6.3 Lateral signal distribution in the basic MOSFET cell . . III-50
III.6.4 Dedicated model for the common-source conguration . III-53
III.7 Model limitations . . . . . . . . . . . . . . . . . . . . . . . . . . III-55
III.7.1 Channel length . . . . . . . . . . . . . . . . . . . . . . . III-55
III.7.2 Biasing conditions . . . . . . . . . . . . . . . . . . . . . III-56
III.7.3 Scaling rules . . . . . . . . . . . . . . . . . . . . . . . . III-57
III.7.4 Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . III-57
III.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-58
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-59
IVExtraction of SOI MOSFET model parameters IV-1
IV.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-1
IV.2 Substrate resistivity . . . . . . . . . . . . . . . . . . . . . . . . IV-3
IV.3 Three-terminal MOSFET model . . . . . . . . . . . . . . . . . IV-3
IV.3.1 Shunt parasitic elements . . . . . . . . . . . . . . . . . . IV-7
IV.3.2 Channel length . . . . . . . . . . . . . . . . . . . . . . . IV-12
IV.3.3 Series parasitic elements . . . . . . . . . . . . . . . . . IV-16
IV.4 Four-terminal MOSFET model . . . . . . . . . . . . . . . . . . IV-25
IV.4.1 Corrections to the shunt parasitic elements . . . . . . . IV-25
IV.4.2 Corrections to the series parasitic elements . . . . . . . IV-29
IV.5 Intrinsic MOSFET in the linear operating regime . . . . . . . . IV-32
IV.5.1 Determination of the C-V curve from broadband measurementsIV-32
IV.5.2 Threshold voltage . . . . . . . . . . . . . . . . . . . . . IV-35
IV.5.3 Mobility . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-36
IV.5.4 Unied analytical model from depletion to inversion . . IV-38
IV.6 Intrinsic MOSFET in saturation . . . . . . . . . . . . . . . . . IV-40
IV.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-44
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-44
V Microwave MOSFET downconversion mixers V-1
V.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-1
V.2 Single FET mixers . . . . . . . . . . . . . . . . . . . . . . . . . V-2
V.2.1 Active mixers . . . . . . . . . . . . . . . . . . . . . . . . V-3
V.2.2 Passive mixers . . . . . . . . . . . . . . . . . . . . . . . V-6
xi
CONTENTS
V.2.3 The MOSFET switch . . . . . . . . . . . . . . . . . . . V-7
V.3 Balanced mixers . . . . . . . . . . . . . . . . . . . . . . . . . . V-8
V.3.1 The Gilbert cell . . . . . . . . . . . . . . . . . . . . . . . V-9
V.3.2 The resistive ring . . . . . . . . . . . . . . . . . . . . . . V-11
V.4 A low-IF down-conversion architecture . . . . . . . . . . . . . . V-13
V.4.1 Basic IF cell . . . . . . . . . . . . . . . . . . . . . . . . V-15
V.4.2 Quadrature generation . . . . . . . . . . . . . . . . . . . V-15
V.4.3 Evaluation chip . . . . . . . . . . . . . . . . . . . . . . . V-17
V.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-17
xii
Main scientic publications
Published
1. J.-P. Raskin, R. Gillon, J. Chen, D. Vanhoenacker, and J.-P. Colinge,
Accurate SOI MOSFET characterization at microwave frequencies for
device performance optimisation and analogue modelling, IEEE Trans.
on Electron Devices, May 1998.
2. R. Gillon, J.-P. Colinge, D. Flandre, J.-P. Raskin, and D. Vanhoenacker,
Silicon-on-insulator for RF and microwave low-power applications, in
Workshop on New Technologies for RF devices, (London Heathrow, U.K.),
Microwave Engineering Europe, Miller Freeman, PLC, May 21 1998.
3. J.-P. Raskin, R. Gillon, and G. Dambrine, Direct extraction of the se-
ries equivalent circuit parameters for the small-signal model of SOI MOS-
FETs, IEEE Microwave and Guided Waves Letters, vol. 7, pp. 408410,
Dec. 1997.
4. I. Huynen, J.-P. Raskin, R. Gillon, D. Vanhoenacker, and J.-P. Colinge,
Integrated microwave inductors on silicon-on-insulator substrate, in
27th European Microwave Conference Digest, (Jerusalem, Israel), pp. 1008
1013, Sep. 812 1997.
5. R. Gillon, J.-P. Raskin, D. Vanhoenacker, J.-P. Colinge, and G. Dambrine,
Characterisation of soi mosfets at microwave frequencies, in Proceedings
of the 8th Int. Symp. on SOI Technology and Devices (S. Cristoloveanu,
ed.), vol. 97-23, (Paris), pp. 149154, Electrochemical Society, Inc., Aug.
31 Sep. 5 1997.
6. J. Chen, J.-P. Colinge, D. Flandre, R. Gillon, J.-P. Raskin, and D. Van-
hoenacker, Investigation of SALICIDE processes for thin-lm SOI mi-
crowave applications, in Proceedings of the 8th Int. Symp. on SOI Tech-
nology and Devices (S. Cristoloveanu, ed.), vol. 97-23, (Paris), pp. 98103,
Electrochemical Society, Inc., Aug. 31 Sep. 5 1997.
xiii
7. J. Chen et al., Comparison of TiSi
2
, CoSi
2
and NiSi for thin-lm silicon-
on-insulator applications, J. Electrochem. Soc., vol. 144, pp. 24372442,
July 1997.
8. R. Gillon, Modelisation et caracterisation du transistor MOS SOI aux
hyperfrequences en vue de la conception dune tete de reception pour
communications mobiles, in Forum URSI 1996 (P. M. Blondel, ed.),
(Faculte Polytechnique de Mons), pp. 4042, Comite URSI (Belge), Dec.
11 1996.
9. J.-P. Colinge, J. Chen, D. Flandre, J.-P. Raskin, R. Gillon, and D. Van-
hoenacker, A low-votlage, low-power microwave SOI MOSFET, in Proc.
IEEE Intl SOI Conf., (Sanibel Island - Fort Myers, Florida), pp. 128129,
Oct. 1-3 1996.
10. I. Huynen, J.-P. Raskin, R. Gillon, D. Vanhoenacker, and J.-P. Col-
inge, Modelling and measurement of inductive elements on SIMOX sub-
strates, in Proc. IEEE Intl SOI Conf., (Sanibel Island - Fort Myers,
Florida), Oct. 1-3 1996.
11. J.-P. Raskin, I. Huynen, R. Gillon, D. Vanhoenacker, and J.-P. Colinge,
An ecient design tool for transmission line on SIMOX substrates,
in Proc. IEEE Intl SOI Conf., (Sanibel Island - Fort Myers, Florida),
pp. 2829, Oct. 1-3 1996.
12. R. Gillon, J.-P. Raskin, D. Vanhoenacker, and J.-P. Colinge, Determin-
ing the reference impedance of on-wafer TLR calibrations on lossy sub-
strates, in 26th European Microwave Conference Digest, (Prague, Czech
Republic), pp. 170173, Sep. 912 1996.
13. J.-P. Raskin, R. Gillon, D. Vanhoenacker, and J.-P. Colinge, Direct
extraction method of SOI MOSFET transistors parameters, in Proc.
of the 7th Intl Symp on SOI Technology and Devices, vol. 96-3, (Los
Angeles), pp. 225229, Electrochemical Society, Inc., May 510 1996.
14. J.-P. Raskin, R. Gillon, D. Vanhoenacker, and J.-P. Colinge, Direct
extraction method of SOI MOSFET transistors parameters, in ICMTS
Conf. Proc., (Trento, Italy), pp. 191194, Mar. 2628 1996.
15. J.-P. Eggermont et al., A 1.0 GHz operational transconductance ampli-
er in SOI technology, in Proc. IEEE Int. SOI Conference, (Tucson
(Arizona)), pp. 127128, Oct. 35 1995.
16. R. Gillon, J.-P. Raskin, D. Vanhoenacker, and J.-P. Colinge, Modelling
and optimizing the SOI MOSFET in view of MMIC applications, in
25th European Microwave Conference Digest, (Bologna, Italy), pp. 543
547, Sep. 47 1995.
17. R. Gillon, J.-P. Raskin, J.-P. Colinge, J. Chen, and D. Vanhoenacker,
Modelling and optimization of the SOI MOSFET in view of MMIC
applications, in Workshop on Si-Processing and High Frequency Devices,
(Kista, Sweden), N.U.T.E.K. Consortia, June 1516 1995.
xiv
18. Z. Zhu, R. Gillon, and A. Vander Vorst, A new approach to broadband
matching for p-i-n photodiodes, Microwave and Optical Technology Let-
ters, vol. 8, pp. 813, Jan. 1995.
19. A. Vander Vorst, D. Vanhoenacker, R. Gillon, Z. Zhu, B. Stockbroeckx,
J. F. Michotte, and J. Singh, Laser diode matching, in Colloque PAI no
24, (Brussels, Belgium), Technologies de linformation optoelectroniques,
May 1994.
M. Serres, and J. Singh, Design and fabrication of a PIN diode, together
with RUG-INTEC, for its transmission line parameters measurement, in
Colloque PAI no 24, (Brussels, Belgium), Technologies de linformation
optoelectroniques, May 1994.
and P. Delisse, S-matrix theory applied to optical systems and com-
ponents, in Colloque PAI no 24, (Ghent, Belgium), Technologies de
linformation optoelectroniques, Nov. 1993.
Accepted
1. J.-P. Raskin, R. Gillon, D. Vanhoenacker, and J.-P. Colinge, Direct Ex-
traction of the non-quasi-static small-signal Model of MOSFETs, in
28th European Microwave Conference Digest, (Amsterdam, The Nether-
lands), pp. 170173, Oct. 59 1998.
2. D. Flandre, J.-P. Colinge, D. De Ceuster, J.-P. Eggermont, L. F. Ferreira,
B. Gentinne, P. Jespers, A. Viviani, R. Gillon, J.-P. Raskin, A. Van-
der Vorst and D. Vanhoenacker, Fully-depleted SOI CMOS technology
for low-voltage, low-power mixed digital / analog / microwave circuits,
Analog Integrated Circuits and Signal Processing, 1997.
Submitted
1. C. Raynaud, O. Faynot, J.-L. Pelloie, S. Deleonibus, D. Vanhoenacker,
R. Gillon, J. Sevenhans, and E. Mackoviak, Fully-depleted 0.25 m SOI
devices for low power RF mixed analog-digital circuits, in IEEE Intl SOI
Conf., 1998.
In preparation
1. R. Gillon, I. Huynen, J.-P. Raskin, D. Vanhoenacker, and J.-P. Colinge,
Macroscopic modelling of CPWs on silicon substrates, IEEE Trans.
on Microwave Theory and Techniques, 1998.
xv
2. R. Gillon, D. Vanhoenacker, and J.-P. Colinge, Modelling non-quasi-
static eects in the SOI MOSFET at microwave frequencies, Analog
Integrated Circuits and Signal Processing, 1998.
xvi
List of abbreviations
AC Alternating Current
A/D Analog to Digital
BJT Bipolar Junction Transistor
BiCMOS Bipolar / Complementary MOS Transistor technology
CMOS Complementary MOS Transistor technology
CPW Coplanar Waveguide
DC Direct Current
DIBL Drain-induced Barrier Lowering
DuT Device under Test
FET Generic Field Eect Transistor
GSM Global System Mobile
(formerly : Groupe Speciale Mobile)
HBT Hetero-junction Bipolar Transistor
HEMT High Electron Mobility Transistor
IC Integrated Circuit
IF Intermediate Frequency
IIP3 Third-order Intermodulation Intercept Point
LDD Lightly Doped Drain
LETI Laboratoire d
Electronique, de Technologie et dInstrumentation

(CENG, Grenoble)
LO Local Oscillator (frequency)
MESFET Metal Semiconductor Field Eect Transistor
MMIC Monolithic Microwave Integrated Circuits
MOS Metal-Oxide-Semiconductor
MOSFET Metal-Oxide-Semiconductor Field Eect Transistor
MS Microstrip line
NQS Non-quasi-static
OTA Operational Transconductance Amplier
PCB Printed Circuit Board
PTFE Poly-Tetrauoro-ethylene
xvii
List of abbreviations
QS Quasi-static
RC Resistance-capacitance
RF Radio Frequency
SIMOX Separation by Implantation of oxygen
SOI Silicon-On-Insulator
SOLT Short-Open-Load-Through calibration
SOS Silicon-On-Sapphire
TAN Through-Attenuator-Network calibration
TE Transverse electric eld mode
TEM Transverse electric and magnetic elds mode
TM Transverse magnetic eld mode
TRL Through reect line calibration
TRM Through-Match-Reect calibration
UCL Universite catholique de Louvain
UniBond UniBond SOI material from SOITEC
VNA Vector network analyser
xviii
Chapter I
Introduction
I.1 RF and microwave monolithic ICs
Analogue circuits functioning in the microwave frequency range use passive
components extensively. At high frequencies, transistor and amplier gain
is limited so that passive impedance matching becomes an important means
of optimising circuit performance. Passive components are typically used to
eliminate unwanted reections at the circuit ports, to maximise the power
transfer or to enhance the noise performance. They are also useful as resonators
in lters or oscillators.
For years, microwave systems have been realised by mounting discrete tran-
sistors together with lumped-element or distributed components on printed cir-
cuit boards. The advantages of the hybrid design approach are the following :
It is simple to combine devices fabricated with very dierent materials so
that optimum performance can be achieved for each component.
Devices can be individually selected in function of their measured char-
acteristics.
Post-assembly trimming is feasible thanks to the large size of the resulting
printed circuit board.
Microwave systems realised on PCBs tend however to be rather bulky and
costly to manufacture. Together with the need for systems of ever increasing
complexity, these drawbacks fostered the development of fabrication processes
allowing the monolithic integration of all passive components and active devices
on a single chip. The principal benets of monolithic integration are :
I-1
Introduction
The length of interconnections is reduced and the package parasitics are
minimised, so that signals are less attenuated and power savings can be
realised.
Device and component uniformity is enhanced and a higher yield is achieved
as the number of packaging and mounting operations is reduced.
Smaller size and light weight can be achieved.
In contrast to the hybrid approach, monolithic integration necessitates a trade-
o in the performance of individual devices, as only compatible fabrication steps
can be merged into a single process.
Figure I.1: A typical MMIC amplier. The spiral inductors are used as RF-
chokes in the DC-biasing circuit. The two comb-like structures are MESFETs.
The input and output pads on the left and right are metal-insulator-metal DC-
blocking capacitors.
Monolithic microwave integrated circuits were rst used for radio com-
munications, radar and guidance in military, naval and aero-space applica-
tions. MMICs eventually found their way into commercial applications via
high-frequency instrumentation, broad-band networks, and mobile communi-
cations, [I.1].
I.1.1 New driving forces
The boom of mobile communications and the advent of high-speed data net-
works have upset the dominant position traditionally held by military appli-
cations in the MMIC market. Military and aero-space systems were typically
high-quality products manufactured in limited quantities, while the markets
for mobile communications and high-speed data networks are calling for mass-
production of low-cost products. For example, the number of mobile communi-
cation terminals sold annually already overtook the number of annual car sales
I-2
during the year 1995, and it is even expected to rise above the number per-
sonal computers sold during the year 1998, [I.2]. This shift of the MMIC market
towards large volume production has fostered the development of alternative
MMIC technologies based on silicon rather than on compound semiconductors
which used to dominate previously.
The mobile terminals themselves also experienced an important evolution.
From the heavy car-phone at the beginning of the 80s to the ergonomically
designed hand-sets of the 90s, the range of available services has been consid-
erably extended from simple voice communications to a complete communica-
tor with electronic mail, fac-simile and internet access. The miniaturisation
of mobile terminals opened up the possibility of integrating communication
capabilities into such systems as palm-top notebooks, as the one featured in
gure I.2. In the future, mobile communication terminals are expected to be-
come capable of multi-mode operation, that is to say, capable to access various
communications services using dierent signalling protocols and modulation
schemes, [I.3].
Figure I.2: The Communicator 9000i from Nokia, [I.4]. A GSM handset and
palm-top PC : based on an Intel-386 processor with 8 Mb of memory. When
the screen is folded down onto the keyboard, the unit looks like any standard
hand-set.
The major technical challenges encountered in the development phase of
such advanced terminals stem from four key parameters : volume, weight,
power consumption and components count. Volume and weight have been de-
I-3
Introduction
creasing steadily since the introduction of the rst portable mobile communi-
cation appliances and are now reaching a level of comfortable use, as indicated
by Neuvo in [I.2]. Power consumption and components count remain as critical
issues where improved solutions are being sought.
Power consumption is critical because mobile terminals must operate on
batteries which have a limited capacity due to weight restrictions. Battery ca-
pacity improvements are slow and major breakthroughs are still to be awaited,
so that the most straightforward solution is presently the reduction of the power
consumption of ICs.
The number of components involved in the assembly of a mobile commu-
nication appliance inuences the reliability, the quality and the manufacturing
costs. Mobile phones still contain an important amount of discrete devices,
especially in the RF sections where 80 % of the parts count is due to discrete
passive devices. Monolithic integration of these devices would not only allow
to enhance manufacturing yield and product reliability, but would also con-
tribute to reduce the power consumption and allow to evolve towards software-
recongurable multi-mode transceivers.
I.1.2 Technology directions
The new challenges resulting from the trend towards low-cost, monolithically
integrated, low-power microwave appliances have triggered an important re-
search eort aiming at the development of adequate MMIC technologies.
Fabrication processes for mass-production
Silicon-based technologies have proven more suitable for mass-production aimed
at consumer markets than compound-semiconductor materials such as gallium-
arsenide. 300 mm-wide silicon wafers of very high quality are presently available
allowing to drive fabrication costs to very low levels by simultaneous processing
of a large number of devices. The largest GaAs wafers available today have a
diameter of only 150 mm.
Handling of GaAs wafers is complicated by the fact that the GaAs material
is brittle. GaAs material is therefore produced by epitaxial growth on a silicon
wafer to facilitate handling. Epitaxial growth is a low-throughput fabrication
step which drives the manufacturing costs up, as investments pay-o must be
spread on a limited number of wafers.
The defect density on GaAs wafers is higher than on Si wafers, so that
circuit manufacturing yield is bound to be lower. Furthermore, isolation tech-
niques available in Si -based technologies allow a much higher integration den-
sity than the isolation processes used in GaAs. The compound semiconductor
material does indeed not possess a stable insulating oxide comparable to silicon-
dioxide. A high integration density is of primary importance for the fabrication
of complex systems as more devices and hence more functions can be integrated
on a single chip.
Together with the fact that Si technologies have had more time to mature,
the larger wafer size, the good material quality and the high integration level are
I-4
denite advantages favouring the development of silicon MMICs for consumer
applications in mobile communications.
Systems on a chip
The demand for increasing functionality of mobile communication terminals has
forced the integration of all base-band parts on to a single chip : the necessary
microprocessors, memories, digital logic circuits and digital signal processors
are now implemented on a single silicon dice using CMOS technology.
Figure I.3: The super-heterodyne architecture proposed by Motorola for digital
cellular phones, [I.5]. It consists of bipolar chips for the receiver and transmitter
ICs, together with one CMOS chip for the base-band processing and one for
the micro-controller. Five ceramic lters are used.
The RF part, on the other hand, is still a mix of discrete components,
together with bipolar or GaAs chips. The low integration level of the RF part
is a direct consequence of the super-heterodyne architecture used presently for
commercial transceivers. Super-heterodyne receivers rely on lters to select the
adequate RF-channel and to reject the image frequency at IF. The constraints
on the lters are relatively tight and can only be met using ceramic lters which
are mounted in separate packages on the motherboard. Figure I.3 illustrates
the architecture proposed by Motorola using the companys products.
As outlined in subsection I.1.1, there exist several economical and tech-
nical incentives pushing towards the monolithic integration of the complete
transceiver on a single chip. Briey, these are : Lower assembling costs, higher
I-5
Introduction
yield and reliability because of the reduced number of components; Power sav-
ings as the interconnection lengths and the number of package pins driven
by high-frequency signals are reduced; Smaller occupied surface on the moth-
erboard allowing for an increased complexity e.g., software recongurable
front-ends. However, single chip integration can not be achieved unless some
alternative architectures are introduced which do away with the need for high-
performance lters.
Candidate architectures for the single-chip integration of the transceiver
have been identied. They use quadrature down-conversion schemes to discrim-
inate between the wanted signal and its image and rely on low-frequency on-chip
ltering to isolate the wanted signal from neighbouring channels, [I.6, I.7]. The
low-frequency ltering can be performed either using analogue or digital signal
processing techniques. The most promising solution is the low-IF architecture
demonstrated by Crols in his thesis, [I.8].
The technology of choice for the single chip integration of the transceiver is
of course CMOS, which is the mass-market technology which already allowed
to integrate all the base-band and control functions monolithically at low-cost
and with a very low power-consumption. Several microwave CMOS technology
options are presently being actively developed. One of them is thin-lm silicon-
on-insulator to which the other chapters of this work are entirely devoted.
Low-power operation
To ensure a sucient autonomy for battery-powered mobile communication
terminals, power consumption must be kept low. In digital CMOS circuitry,
the dynamic power consumption per gate is known to be proportional to
C
load
V
2
swg
f
clk
, where C
load
is the load capacitance, V
swg
is the voltage swing
and f
clk
is the clock frequency. Lowering the biasing voltage and hence the
voltage swing is thus the most eective way to reduce the power consumption
of digital MOS circuits, [I.9]. In order to maintain the current drive capability
and the switching speed of the devices, the threshold voltage is lowered and the
channel length is scaled down. If the threshold voltage is too low, then the o-
state leakage current will become too important, causing a noticeable increase
of the static power consumption. The optimum threshold voltage must hence
be chosen in function of the acceptable level of leakage current. In conventional
bulk MOS technology the optimum lies around 450 mV, while for thin-lm SOI
MOSFET it lies about 10 mV lower, [I.10].
For low-frequency designs, the analogue performance of MOSFETs is most
suitably characterised by the open-loop voltage gain of a single device A
V
=
G
m
/G
DS
where G
D
is the output conductance. The output conductance can be
approximated over a wide bias range by I
D
/V
A
, where V
A
is the early voltage.
Finally :
A
V
=
G
m
I
D
V
A
(I.1)
The G
m
/I
D
ratio is a measure of the eciency to translate current hence
power into transconductance, [I.10]. In low-power applications, G
m
/I
D
can
I-6
be maximised by operating the transistors in weak inversion, with a low gate
voltage overdrive above the threshold, [I.9]. In conventional bulk MOS transis-
tors the peak G
m
/I
D
ratio attains about 25 V
1
in weak inversion. For SOI
MOSFET this peak value lies around 35 V
1
.
0 0.5 1 1.5 2 2.5 3
f
T
GHz
Bias Voltage
0.5 m Bulk MOSFET

0.65 m Bulk Bipolar
0.75 m SOI MOSFET
0
5
10
15
20
25
0.5 m SOI MOSFET
Figure I.4: Evolution of the transition frequency f
T
in function of the bias
voltage for various technologies and their particular minimum feature width.
The bulk MOS and bipolar transistor data comes from a BiCMOS technology,
[I.11]. The 0.75 m channel-length SOI MOSFET data was obtained at the
UCL, [I.12]. The 0.5 m SOI MOSFET data is an extrapolation based on the
eective channel length and a linear scaling of f
T
.
In high-frequency applications, capacitive loading becomes the determining
factor and the analogue device performance is best analysed using the current
gain, A
I
= G
m
/( C
G
), where C
G
is the total gate capacitance of the MOS-
FET. The current gain can be evaluated for any type of device, either bipolar,
MOSFET or MESFET, and its transition frequency, f
T
, is a direct measure
of the high-frequency performance which allows to compare dierent technolo-
gies. The evolution of f
T
versus biasing voltage presented in gure I.4 allows to
compare the low-voltage performance of various technologies at microwave fre-
quencies. The bipolar transistor is already within 20 % of its peak performance
at 0.6 V, the SOI MOSFET at 0.8 V and the bulk MOSFET at 1.2 V.
Thin-lm SOI MOS technology thus appears to be a very good candidate for
the implementation of mixed-mode low-power systems comprising digital and
high-frequency analogue components, the latter being capable of operation at
microwave frequencies. A detailed comparison of MOS and bipolar technologies
for microwave applications is proposed in the next section.
I-7
Introduction
I.2 Competing technologies for emerging RF ap-
plications
The competing device technologies for the emerging mass-market applications
are bipolar, CMOS, and mixed bipolar-MOS (BiCMOS). Bulk-silicon and silicon-
on-insulator options are available for all three. Bipolar-only processes, and
SiGe bipolar in particular, are high-performance technologies which are prob-
ably shooting to high with respect to the needs of the mobile communication
market in the near future, [I.13]. Bipolar-only processes target high-speed ap-
plications and are in particular not well suited for the implementation of the
low-power digital base-band part of portable communication terminals. CMOS
and BiCMOS are thus the best candidates for the single chip integration of mo-
bile communication transceivers.
High performance sub-micrometre-channel MOSFETs are capable of ana-
logue operation at microwave frequencies, [I.13]. The record transition fre-
quencies of 150 GHz recently attained with experimental nanometre MOS-
FETs show that present-day MOS technology still has potential for improve-
ment, [I.14]. Using a silicon-on-insulator substrate, circuit speed can be sub-
stantially improved, but the ultimate advantage of SOI CMOS circuits is to
be expected in low-power applications when using thin-lm, fully depleted SOI
MOSFETs, [I.10].
The use of MOSFETs in microwave circuits does however cause a few
problems which bipolar transistors can remedy, so that BiCMOS technologies
are very appealing.
1. Optimal tuning of the MOSFET noise performance is more dicult than
for bipolar devices. Indeed, the input load resulting in the minimum
noise gure is for MOSFETs a large inductance with a high quality
factor, which can not be practically be implemented on-chip. Worse even,
the sensitivity of the noise gure to the input load is high, so that the
noise gure degrades rapidly when the input load departs for its optimal
value, [I.15]. One solution to this is to increase the device size at the
expense of larger drain current and power dissipation. In such a case, a
circuit with BJTs requires lower bias current and dissipates less power
for comparable noise gures, [I.11].
2. Short-channel MOSFETs, and fully depleted SOI MOSFETs in partic-
ular, have a rather high output conductance in saturation which may
aect amplier gain. Typical values for the Early voltage of MOSFETs,
V
A
= G
DS
I
D
, lye around 30 V, while for BJTs V
A
= G
CE
I
C
lies around
50 V.
3. MOSFETs are less ecient to handle large signals than BJTs, as they
require a considerably larger biasing current to attain high power-levels,
[I.13].
Being more complex than CMOS technology, BiCMOS is of course more costly,
and must be targeted at high-end products which can absorb the extra cost.
I-8
I.2 Competing technologies for emerging RF applications
Plain CMOS can however be expected to prevail in low-cost and less demanding
applications.
I.2.1 Bulk MOSFETs
Silicide
Silicide
n
+
diusion
n
di. (LDD)
Pocket implants
p well
Channel-stop implants
Source Gate Drain
Poly-silicon
Oxide
Silicide
Depletion limit
n
+
diusion
n
di. (LDD)
p
substrate
Field oxide Field oxide
Channel region
Figure I.5: Cross-section of a short-channel bulk-silicon MOSFET.
Characteristic of bulk technologies is that the transistors are fabricated di-
rectly on monocristalline silicon wafers and are thus all in contact with the
substrate material. Bulk has been the main-stream technology for years, but
silicon-on-insulator has now evolved into a mature contender, [I.16]. A specic
advantage of bulk technology is that the substrate acts as an ecient heat-sink,
thanks to the high thermal conductivity of silicon. Bulk technology is however
confronted with isolation problems. Bulk MOS transistors suer from high par-
asitic capacitances diusion capacitances, body eect and require special
techniques for submicrometer scaling. Figure I.5 shows the cross-section of a
high-performance bulk MOSFET.
Isolation
The standard isolation technique in bulk technology is the use of reverse-biased
junctions. This technique is only ecient at low frequencies and at moder-
ate operating temperatures : Indeed, high-frequency signals may easily cross
reverse-biased junctions because of the nite capacitance, while leakage cur-
rents increase rapidly with temperature up to a point were reverse biased
junctions have little blocking eect. Junction isolation may even fail catas-
trophically when neighbouring p- and n-wells combine to form a thyristor-like
structure which can be triggered by a transient injecting a sucient amount of
I-9
Introduction
current in any of the wells. These issues can be partly resolved by increasing
the inter-well spacing, at the cost of a lower integration density, or by using
advanced techniques such as trench isolation.
Parasitic capacitances
At low frequencies, when the substrate is essentially conductive, bulk MOS-
FETs are loaded by large capacitances due to the depletion region associated
with the source and drain diusions as well as with the inversion channel. The
lower limit of the depletion region is represented in gure I.5 by the dashed
line. The presence of a large depletion region underneath the gate oxide has
a detrimental eect on the characteristics of the MOSFET. The inuence of
the gate voltage, V
G
, on the surface potential,
s
, which controls the inversion
charge density in the channel, is diminished :
d
s
dV
G
ox
C
ox
+ C
d
< 1 (I.2)
For an ideal device, the derivative should approach unity. This body eect
which reduces the eective control of the gate on the channel, is responsible
for the low rate at which the transition frequency f
T
of the bulk MOSFET
increases as a function of bias voltage on gure I.4. The o-state performance
of bulk MOSFETs is also aected, as the gate voltage must be driven lower
below threshold to restrain the leakage current below a specied level. Bulk
MOSFETs must therefore be designed with higher threshold voltages see
gure I.4.
Substrate
Gate-oxide capacitance
Depletion capacitance
Gate
s
Substrate capacitance
Wafer back-plane
Gate
s
V
G
V
G
Low-frequency High-frequency
Figure I.6: The body-eect for a bulk MOSFET at low-frequencies. (Interface
states have been negelected)
Paradoxally, the body eect has a less dramatic inuence on high-frequency
I-10
signals. The reason is that, for signals located in a band above the dielectric
relaxation frequencies of the silicon material, the substrate behaves rather as
a lossy dielectric, which adds a small capacitance in series with the depletion
capacitance so that the body eect is attenuated.
Short-channel eects
The large depletion zones associated with the source and drain diusions of
bulk MOSFETs are also an obstacle to the submicrometer scaling of the chan-
nel length. Indeed, the nite width of these depletion zones set a lower bound
on the channel length. Below this limit, the source and drain depletion zones
overlap, creating a region where a strong electric eld can sweep electrons di-
rectly from source to drain independently of the gate voltage. Even, at channel
lengths above this punch-through limit, the source and drain depletion zones
have a detrimental impact on scaling, as they contribute to lower the threshold
voltage, [I.10].
Present-day submicrometer MOSFET technologies compensate the punch-
through and threshold voltage roll-o eects using special pocket implants,
which are designed to locally divert the electric eld, [I.17]. These pockets
must be very precisely located at the lower tip of the diusions. To achieve
the proper doping prole, a tilted implantation technique is used where the
wafer is tilted at an angle with respect to the ion-beam. Four of these implants
are required to provide pockets at the drain and source of MOSFETs aligned
in two orthogonal directions. Specic masks are also required to select the
implantation regions.
Partially depleted SOI MOSFETs
Silicon-on-insulator technology can be used to enhance the performance of bulk
MOSFETs, particularly speed and packing density. The latter is increased on
SOI essentially thanks to the very ecient isolation of individual devices by the
eld and buried oxides. This all-round isolation alleviates the need for diused
wells which require specic contacts and careful spacing and are limiting the
integration density in bulk technology.
The buried oxide layer, with its low dielectric constant, contributes to sig-
nicantly reduce the parasitic capacitances loading the source and drain dif-
fusions, allowing SOI designs to book speed gains with respect to their bulk
counter-parts, [I.16, I.18].
The partially depleted device shown in gure I.7 is a rather conservative SOI
MOSFET design : it is merely a bulk MOSFET transposed onto a SOI sub-
strate. In particular, the existence of a quasi-neutral region below the depletion
zone associated with the transistor ensures that the body eect in the partially
depleted SOI MOSFET is identical to that of the bulk MOSFET, so that the
SOI device shows no improvement in the subthreshold characteristics, [I.10],
which are essential for low-voltage applications.
Partially depleted SOI MOSFETs have a also a problem of their own :
oating body eects. It is mainly a lowering of the threshold voltage due to the
accumulation holes generated by hot carriers in the drain region. The result is
I-11
Introduction
an ugly kink in the current characteristics occuring at moderately high drain
voltage. The eect can be suppressed by using special body contacts which tie
the neutral region of the lm to the source potential.
Silicide
Silicide
n
+
diusion
n
di. (LDD)
Pocket implants
p lm
Source Gate Drain
Poly-silicon
Oxide
Silicide
Depletion limit
n
+
diusion
n
di. (LDD)
p
substrate
Pocket implants
Channel region
Buried oxide
Figure I.7: Cross-section of a short-channel partially-depleted SOI MOSFET.
Silicide
Silicide
n
+
diusion
p lm
Source Gate Drain
Poly-silicon
Oxide
Silicide
n
+
diusion
p
substrate
Channel region
Buried oxide
Figure I.8: Cross-section of a short-channel fully-depleted SOI MOSFET.
I-12
I.2.2 Thin-lm SOI MOSFETs
It has been shown in the last subsection that silicon-on-insulator technology
remedies elegantly to the isolation problems of conventional bulk technologies
and even contributes to circuit speed improvements. The use of fully depleted
SOI MOSFETs extends the advantages of SOI even further to easier down-
scaling and nearly optimal low-voltage performances. Fully depleted SOI de-
vices are obtained by using silicon lm thicknesses thinner than the depth of
the depletion zone, typically below 100 nm.
Low-voltage operation
Figure I.9 reveals that in all cases the body eect in fully depleted SOI MOS-
FETs is less pronounced, because the series connection of the lm capacitance,
C
b
, and the buried oxide capacitance, C
ob
, is smaller than the depletion ca-
pacitance of a bulk transistor. The control of the gate voltage on the surface
potential,
sf
, and hence the channel, is even almost optimal as the buried
oxide capacitance is very small :
d
sf
dV
Gf
1/C
b
+ 1/C
ob
1/C
of
+ 1/C
b
+ 1/C
ob
1 (I.3)
where C
of
is the gate oxide capacitance, the interface states have been ne-
glected. For high-frequency operation, the situation is even more favorable,
thanks to the substrate capacitance.
sf
sb
Gate-oxide capacitance
Si lm capacitance
Gate
Buried oxide capacitance
Wafer back-plane
Gate
V
Gf
V
Gf
Low-frequency High-frequency
Substrate
sf
sb
Substrate capacitance
Figure I.9: The body-eect for a fully-depleted SOI MOSFET.
I-13
Introduction
The very small body eect of fully depleted SOI MOSFETs is the key
to their outstanding low-voltage performances and their good high-frequency
performance. Interestingly, the fabrication of these devices is less complicated
than that of bulk MOSFETs of comparable channel lengths, notwithstanding
their better performances. The comparison of gures I.5 and I.8 shows indeed
that the SOI MOSFET structure is inherently simpler than that of the bulk
device.
Short-channel eects
In fully depleted SOI MOSFETs, the small thickness of the silicon lm strongly
limits the extent of the depletion zones associated with source and drain, so
that the risk of punch-through and the threshold-voltage roll-o are strongly
attenuated. This feature alleviates the need for complex pocket implants, al-
lowing to reach smaller channel lengths with a simpler fabrication process,
comparatively to bulk technology. Even other short-channel eects such as
channel-length modulation and drain-induced barrier lowering have been shown
to be less severe in fully depleted SOI MOSFETs.
I.2.3 Bulk bipolar transistors
As already stated at the beginning of section I.2, bipolar junction transis-
tors can help to optimise the overall circuit performance, particularly in RF
analogue circuits, where the dicult noise tuning, the larger output conduc-
tance and the limited power handling capability of MOSFETs may have a
detrimental impact, [I.13, I.19]. Bulk BiCMOS technology, because of the 30 %
cost-overhead due to the higher process complexity, targets essentially high-tier
products in the mobile communications equipment market.
Figure I.10 presents the cross-section of a npn-BJT in a typical bulk BiC-
MOS process, [I.20]. Additional processing steps with respect to CMOS tech-
nology are :
Epitaxial crystal growth, necessary to stack the collector n-well on top of
the n
+
region.
Second poly-siclicon layer for the emitter contact.
Vertical BJT structures such as the one displayed in gure I.10 have been
implemented on SOI. This kind of structure requires a minimum lm thickness
of about 1 m, so that vertical BJTs are not compatible with fully depleted
MOSFETs.
I.2.4 Thin-lm lateral bipolar SOI transistors
The lateral bipolar structure shown in gure I.11 can be used to implement a
BiCMOS process in thin-lm SOI technology, [I.21]. Current-gain transition
frequencies around 15 GHz have been attained for such devices integrated to-
gether with 0.5 m fully-depleted MOSFETs, demonstrating the viability of a
I-14
Collector
Base
Emitter
Base
Poly-silicon (E.)
Oxide
Polysilicon (B.)
Field oxide
p
+
extrinsic B. di.
n
+
emitter
p intrinsic B. di.
Polysilicon (B.)
Oxide
Oxide
n
+
C. diusion
n
C. well
p
substrate
Figure I.10: Cross-section of a bipolar junction transistor in a bulk-silicon
BiCMOS process.
Collector Emitter Base
Polysilicon (B.)
Field oxide
n
+
E. diusion
p B. diusion
Oxide
n
+
C. diusion
n
collector
p
substrate
Metal (E.)
Oxide
Metal (C.)
Buried oxide
Field oxide
Figure I.11: Cross-section of a lateral bipolar junction transistor in a thin-lm
SOI BiCMOS process.
I-15
Introduction
microwave, thin-lm SOI BiCMOS technology, [I.22]. Interestingly, the fabrica-
tion of the lateral BJT structure is fairly simple, involving exclusively standard
CMOS processing and requiring the addition of only two extra lithography
steps.
I.2.5 Low-voltage systems-on-a-chip, the future of SOI
The comparison of technologies and their basic building blocks in the previous
subsections has shown that thin-lm SOI has a strong potential for large-scale
integrated systems where integration density and power savings are a premium.
Thin lm SOI MOS and bipolar devices oer excellent microwave performances
in low-voltage biasing conditions at a reasonable cost, because of their inher-
ently simple device structure. Thin-lm SOI hence appears as a technology of
choice for the single-chip integration of advanced mobile communication ter-
minals.
I.3 Silicon-on-Insulator substrate technology
SOI substrate technology has been under development for more than two
decades. Many options have been investigated, but, presently, three solutions
seem to dominate : silicon-on-sapphire, oxygen implantation and wafer bond-
ing. Silicon-on-sapphire was the rst to reach maturity, but it is not suited for
mass-production and will probably survive in niche applications. The remain-
ing SOI wafer technologies have both evolved to meet the the constraints of
high-volume production, but it seems that wafer-bonding may gain the lead.
I.3.1 Silicon-on-sapphire
Silicon-on-sapphire substrates are obtained by growing a silicon substrate on
top of a monocristalline sapphire substrate. This process is called hetero-epitaxy
as silicon and sapphire are dierent materials with slightly dierent cristal
structures. The dierences in lattice dimensions generate stress in the silicon
layer, which is absorbed by the formation of cristal defects. Such defects reduce
the carrier mobility and can induce leakage currents.
In order to achieve reasonable transistor performances on SOS, the density
of cristal defects is reduced using specic processing techniques, [I.23]. These
allow to heal the cristal structure in most of the silicon lm, except for a thin
buer-layer in the vicinity of the sapphire, where cristal defects compensate the
lattice mismatch. This residual defect concentration at the bottom of the lm
makes SOS substrates unsuitable to integrate thin-lm fully depleted MOS-
FETs. Cristal defects would indeed be activated by variations of the surface
potential
sb
at the bottom of the lm, modifying the device characteristics in
an unpredictable manner and generating noise. In partially depleted devices
on the other hand, the quasi-neutral region is tied to the source, so that the
potential
sb
is xed, and that defects are not activated.
Sapphire is a very attractive substrate, having a very high resistivity, a
low dielectric constant and a high thermal conductivity. The hetero-epitaxial
I-16
(a) (b)
Silicon lm Cristal defects
Sapphire substrate
Figure I.12: Silicon-on-sapphire substrate fabrication : (a) Hetero-epitaxy of
silicon on a sapphire substrate; (b) Successive amorphisation and recrystallisa-
tion steps.
growth and the recrystallisation steps are however costly and low through-
put processing steps, which disqualify SOS in the competition for mass-market
applications.
I.3.2 Separation by Implantation of Oxygen
(a) (b)
O
Buried oxyde
Silicon lm
Figure I.13: The SIMOX fabrication process : (a) Oxygen implantation, for-
mation of oxide precipitates; (b) Annealing. Steps (a) and (b) are repeated
until the buried oxide attains the desired thickness.
SIMOX is a trade-mark of Ibis Corp. which developed the process and
commercialises SOI wafers. In this process, oxygen is implanted inside a sil-
icon wafer in order to form a buried Si O
2
layer underneath a thin cristalline
I-17
Introduction
lm. Compared to implantation doses usually required in transistor fabrica-
tion, where the implanted impurities form a small fraction of the total number
of atoms in the material, in the SIMOX process the implanted O
dose in
enormous, as the number oxygen ions must be twice the number of Si atoms
necessary to form the buried oxide layer. In order to avoid damaging the cristal
structure of the top silicon lm irreversibly, the implantation is performed pro-
gressively, alternating implantation and annealing steps. The technique pro-
duces high-quality lms, with a defect density comparable to that of bulk-silicon
wafers, so that giga-bit memories have been successfully integrated on SIMOX
wafers.
High-capacity implanters have been developped specically for mass-produc-
tion in the SIMOX process, however the fabrication cost is high, and will prob-
ably remain higher than that of bulk-silicon wafers, [I.10].
I.3.3 Wafer-bonding
(c) (d)
(a) (b)
H
+
Wafer A Wafer A
W a f e r A
Wafer B
R
ecycled
as
new
wafer
B
Smart-Cut layer
SiO
2
Figure I.14: The UniBond fabrication process.
Wafer-bonding relies on the attraction of two hydrophilic surfaces for each
other. Once brought in contact these surfaces attract each other so strongly,
that hydrogen bonds can form spontaneously. The bonding can then be further
strengthened by a proper annealing. Wafer bonding is used to form SOI wafers,
I-18
but can eventually be used to transfer a silicon-lm containing processed cir-
cuits onto a dierent substrate, for example alumina, chosen for its outstanding
dielectric properties.
UNIBOND material
UniBond is a trade-mark of SOITEC which commercialises SOI wafers pro-
duced using the patented Smart-Cut process. SOI wafer fabrication starts
with the growth of a high-quality oxide on a bulk silicon wafer, gure I.14(a).
Then hydrogen atoms are implanted in the silicon below the oxyde, at a depth
corresponding to the wanted lm thickness, gure I.14(b). The wafer A and
a second wafer B are prepared for bonding by a cleaning step. Wafer A is
then turned over and brought into contact with B for bonding, gure I.14(c).
The bonded wafers are heated to 500
C, at which temperature the implanted

hydrogen activates and creates a cleavage plane cutting wafer A in two and
leaving a thin cristalline silicon lm on top of a buried oxide layer on wafer B
the Smart-Cut process, gure I.14(c). The new SOI wafer is then annealed,
and the surface roughness is adjusted on both wafers by a touch polishing step.
Wafer A is nally recycled as a new wafer B.
All of the fabrication steps involved in the production of UniBond wafers
have been tailored for high-volume production. On the basis of the production
capacity being installed, some projections even dare to predict lower prices for
8 inch UniBond wafers than for equivalent bulk silicon wafers.
Silicon-on-anything
Bonding or even glueing can be used to transfer thin silicon lms containing
fully operational circuits onto various substrates. Applications of such tech-
niques are typically : the creation of three-dimensional structures as memory
capacitors, [I.16], the substitution of high-quality substrates (instead of the na-
tive silicon) for microwave operation, [I.24], or the transfer onto adhesive tapes,
etc.
I.3.4 The blooming of a SOI era ?
Silicon-on-insulator has evolved into a mature technology, oering not only
higher performance and simpler device processing, but also opening up a wealth
of new design possibilities, such as the vertical stacking of structures, the lift-o
and transfer of circuits and the integration of sensors, micro-mechanical ele-
ments, optical waveguides, etc. The break-through of SOI into large volume
applications will be driven by the demand for highly integrated low-voltage
systems, such as portable and personal communications equipment. The range
of applications of SOI will then rapidly spread to computer memories, automo-
tive, aircraft and spaceborne electronics, where in addition to their low-voltage
performance, the exceptional isolation, the high-temperature stability and the
radiation hardness of SOI circuits will be appreciated.
I-19
Introduction
I.4 Characterisation and modelling of MMICs
The availability of adequate device models is essential for the design of high-
performance integrated systems. Design methods rely heavily on computer
simulations of circuits to investigate alternative solutions using virtual proto-
typing, which is both more exible, faster and less expensive than the eective
fabrication of a prototype. During a simulation, information about the be-
haviour of individual devices is extracted from their models and combined to
evaluate global circuit responses. The accuracy and the reliability of circuit
simulations is thus conditionned by the quality of available models. To en-
sure a sucient level of accuracy, model predictions must be systematically
confronted with measured device characteristics in order to tune parameters
values to obtain a good agreement. In the case of microwave devices, charac-
teristics used for model validation and for parameter extraction are basically
the evolution of scattering parameters versus frequency and biasing conditions.
Figure I.15: A close-up view of the probing setup on a Karl Suss PM-8-HF
station, showing the coaxial cables feeding the microwave on-wafer probes. The
probes are 40 GHz PicoProbes from GGB Industries. (Photograph courtesy of
Karl Suss, [I.25])
On-wafer characterisation is the measurement of device characteristics di-
rectly on the silicon die, immediately after fabrication, before slicing and encap-
sulation. It is both an important productivity tool and a powerful modelling
tool. Indeed, on-wafer characterisation allows to test individual circuits in a
highly automated way, so that the whole production can be scanned and faulty
chips eliminated prior to packaging and assembly. On-wafer characterisation
also allows to access transistors, passive devices or any circuit building block
directly with minimal interfering parasitics, facilitating model development and
validation.
I-20
I.4 Characterisation and modelling of MMICs
Figure I.16: ACP 40 GHz on-wafer probes from Cascade. The inset shows a
microscope view of the probe tips.
Using adequate probes, the test-signals can be transferred from the coaxial
cables connected to the measuring equipment onto the integrated transmission
lines feeding the test-devices. To ensure optimal measurement conditions, mi-
crowave probes must provide a seamless transition between the millimetre-scale
connectors of the coaxial cables and the micrometre-scale integrated coplanar
waveguide structures. As is usually the case in microwave hardware, high-
performance translates in tight mechanical tolerances which explain the high
cost of such probes.
The quality of the transition realised by the probes depends on the ability
to obtain simultaneous contacts with the three probe-tips on the aluminum
metallisation of the test-structures. Planarity of the probe with respect to the
substrate is therefore critical and careful adjustments of the rolling angle are
required. The quality of the contacts further depends on the pressure of the
probe tips onto the aluminum contact pads. This pressure is controlled by the
amount of overtravel, the vertical distance by which the probe body is lowered
after the initial touch-down of the probe tips, typically around 100 m.
In order to perform accurate and reliable measurements on small-size inte-
grated devices, a high horizontal positionning accuracy must be achieved with
a good repeatability. Micro-metric screws used for positionning typically have
a resolution on the order of 5 m which can be fully exploited if adequate refer-
ence marks are provided on the test-wafer. Figure I.4 shows a probing structure
with its sets of alignment marks designed reduce the positionning uncertainty
below 5 m. Other important features of this design are that :
the ground-to-ground spacing of the coplanar waveguide sections is di-
mensioned so as to closely t the average transistor size, allowing to
reduce the inductance of ground connections.
the structure implements a smooth transition between the geometry of the
I-21
Introduction
Signal
Ground
Ground
Probe-tips
Contact pads
Passivated metal
Alignment marks
150 m
150 m
Figure I.17: Artists view showing microwave on-wafer probes contacting a
MOSFET test structure.
probe-pads dictated by layout rules and the feeding waveguide sections
naturally associated with the transistor geometry.
the spacing between opposing sets of probe-pads is large in order to reduce
the risk of direct coupling between the probes.
To achieve the required control on the probes motion and attitude, each
probe is mounted on a positionner equiped with three orthogonal micrometric
translation stages and one tilting stage. The positionners themselves are bolted
down on a single rigid platen, which rests on an antivibration table. Vibration
isolation is further enhanced by feeding the probes with exible cables disposed
in an ample meander curve.
Such an on-wafer probing station was used intensively in the framework of
this thesis. All scattering parameters measurements shown in the text were per-
formed on the probing station installed at the Laboratoire dHyperfrequences.
The characterisation procedure is described in more detail in chapter II.
I.5 Conclusion
The global context of the thesis has been reviewed. SOI and bulk technologies
were compared in the perspective of the evolution towards portable, multi-
functional personal (communication) appliances. The specic advantages of the
fully depleted SOI CMOS technology for low-voltage, low-power applications
were illustrated. The major types of SOI material were presented. Important
aspects of characterisation and modelling were discussed and the microwave
on-wafer probing station has been described.
I-22
REFERENCES
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[I.2] Y. Neuvo, Future directions in mobile communications, in Proceedings
of the 22nd European Solid-State Circuits Conference (H. Gr unbacher,
ed.), pp. 3539, Sept. 1996.
[I.3] Y. Neuvo, Rf mobile communications circuits - comparision of technolo-
gies, in Proceedings of the 27th European Solid-State Device Research
Conference (H. Gr unbacher, ed.), pp. 2427, Sept. 1997.
[I.4] Nokia, <http://www.forum.nokia.com>, Nokia 9000i communicator.
[I.5] Motorola Inc., <http://mot-sps.com>, Reference Designs : Yellow-
stone 900 MHz Preview, Sep 1997.
[I.6] A. A. Abidi, Direct-conversion radio transceivers for digital communi-
cations, IEEE J. of Solid-State Circuits, vol. 30, pp. 13091410, Dec.
1995.
[I.7] J. Crols and M. S. J. Steyaert, A single-chip 900 MHz CMOS receiver
front-end with a high performance low-IF topology, IEEE J. of Solid-
State Circuits, vol. 30, pp. 14831492, Dec. 1995.
[I.8] J. Crols, Full integration of wireless transceveir systems. PhD thesis,
Katholieke Universiteit Leuven, Leuven, Belgium, 1996.
[I.9] E. A. Vittoz, Low-power design : Ways to approach the limits, in Di-
gest of Technical Papers, IEEE International Solid-State Circuits Con-
ference, pp. 1418, 1994.
[I.10] J.-P. Colinge, Silicon-on-Insulator Technology : Materials to VLSI.
Boston Dordrecht London: Kluwer Academic Publ., 2nd ed., 1997.
[I.11] S. P. Voinigescu, S. W. Tarasewicz, T. MacElwee, and J. Ilowski, An
assessment of the state-of-the-art 0.5 m bulk CMOS technology for RF
applications, in IEDM 95, Technical Digest, pp. 721724, 1995.
[I.12] J.-P. Colinge, J. Chen, D. Flandre, J.-P. Raskin, R. Gillon, and D. Van-
hoenacker, A low-votlage, low-power microwave SOI MOSFET, in
Proceedings of the IEEE Int. Silicon-on-Insulator Conference, pp. 128
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[I.13] J. Burghartz, Silicon RF technology the two generic approaches,
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[I.14] C. Wann et al., High-performance 0.07 mCMOS with 9.5 ps gate delay
and 150 GHz f
t
, IEEE Electron Device Letters, vol. 18, pp. 625627,
Dec. 1997.
I-23
Introduction
[I.15] J.-P. Raskin, Modeling, Characterizatiiion and Optimization of MOS-
FETs and Passive Elements for the Synthesis of SOI MMICs. PhD
thesis, Universite catholique de Louvain, Dec. 1997.
[I.16] A. J. Hauberton-Herve, SOI : Materials to systems, in International
Electron Device Meeting, Technical Digest, pp. 310, 1996.
[I.17] C. H. Wann, K. Noda, T. Tanaka, M. Yoshida, and C. Hu, A compar-
ative study of advanced MOSFET concepts, IEEE Trans. on Electron
Devices, vol. 43, pp. 17421752, Oct. 1996.
[I.18] Y. Ohtomo, S. Yasuda, M. Nogawa, J.-i. Inoue, K. Yamakoshi,
H. Sawada, M. Ino, S. Hino, Y. Sato, Y. Takei, T. Watanabe,
and K. Takeya, A 40 Gb/s 8 8 ATM switch LSI using 0.25 m
CMOS/SIMOX, in ISSCC 97, Digest of Technical Papers, pp. 154
155, Feb. 1997.
[I.19] A. R. Alvarez, ed., BiCMOS Technology and Applications. Kluwer Aca-
demic Publ., 2nd ed., 1993.
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ch. 2, pp. 2165.
[I.21] B. Edholm, J. Olsson, and A. S oderb arg, A self-aligned lateral bipo-
lar transistor realized on SIMOX-material, IEEE Trans. on Electron
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on Electron Devices, vol. 42, pp. 506512, Mar. 1995.
[I.23] C. A. Garcia, R. E. Reedy, and M. L. Burgener, High-quality CMOS in
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Sinderen, A 3.5 mW 2.5 GHz diversity receiver and a 1.2 mW 3.6 GHz
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ternational Solid-State Circuits Conference, 1998.
[I.25] Karl Suss Dresden Gmbh, Manual Probe System PM 8 HF, 1996.
I-24
Chapter II
On-wafer characterisation
at microwave frequencies
II.1 Introduction
Scattering parameters measurements are probably the fundamental microwave
measurement technique. At least are they at the origin of all results shown in
the present work. This urged the need to develop a thorough insight into
the foundation of the measurement technique. Particularly because there ex-
isted some shadow areas around the way to deal properly with dicult cases
such as very lossy planar lines. The publication of results from an investiga-
tion mandated by service providers to the microwave industry in the United
States, [II.1], came at the right time. The paper proposed a rigorous framework
allowing to deal very generally with the problems concerning lossy waveguides,
and announced several convincing results, such as a the comparison of a mea-
surement of the power dissipated in a resistor with the prediction based on the
measured scattering parameters. The theory from [II.1] has been adopted here,
and veried repeatedly by several experiments reported below.
Some new solutions had however to be found concerning the practical as-
pects of the theory, particularly the operational determination of the reference
impedance. Two original schemes have been proposed. Some material is shown
in this chapter indicating the validity of the method, but the most convincing
validation remains unseen : the megabytes of data satisfactorily de-embedded
by the technique ...
A deliberate and unique choice made in this work is the option for in-situ
calibration : using scattering parameters de-embedding techniques to correct
for the parasitic inuence of probe-pads and feeding lines. This choice proved
II-1
On-wafer characterisation at microwave frequencies
to be successful and eectively remedies to several problems experienced by
other techniques and reported in the literature.
This chapter is organised as follows :
Section II.2 introduces the basic concepts related to electro-magnetic
elds propagating in waveguides.
Section II.3 builds forth on these basic concepts to develop a waveguide
circuit theory providing the general framework for scattering parameters
measurements.
The calibration methods of interest for on-wafer probing are reviewed in
section II.5.
Section II.6 provides an in-depth discussion of reference impedance de-
termination methods.
Finally, two de-embedding strategies are analysed and compared in sec-
tion II.7 : the newly proposed in-situ calibration and the widely used
immittance correction.
II.2 Uniform waveguides
This section introduces rigorous denitions of the basic concepts which are
useful to describe the electro-magnetic behaviour of waveguides. A uniform
waveguide may be broadly dened as an axially independent structure sup-
porting electro-magnetic waves. These waves are described by the Maxwell
equations in the frequency domain coupled to appropriate boundary conditions
accounting for materials interfaces and impenetrable surfaces. The eigenvalue
problem is separable and the axial solutions are exponential, [II.2, II.3]. In
general there are many linearly independent solutions of this problem, each of
which is proportional to a mode of the waveguide.
In this section, only a single mode is considered which propagates along
OZ, the longitudinal axis, in both directions. All materials will be assumed to
be isotropic, so that the permitivity and the permeability reduce to scalars.
II.2.1 Modal electro-magnetic elds
In order to have a unique representation of each mode, normalised modal elds
are introduced. For a mode propagating in the forward direction increasing
z the normalised modal electric and magnetic elds are denoted by

e e
z
and

h e
z
, respectively where
e and

h are independent of z. The normali-
sation scheme used need not be specied here, any xed but otherwise arbitrary
normalisation of the modal elds will do. For example, a widely used scheme
is :
_
S
[
e
t
[
2
dS = 1 (II.1)
_
S
h
t
2
dS = 1 (II.2)
II-2
The modal propagation constant is composed of real and imaginary parts :
+ (II.3)
To get a clear understanding of the eigenvalue problem, the transverse com-
ponent of the modal elds,

e
t
and

h
t
, are expressed in terms of their longitu-
dinal component,

e
z
= e
z

u
z
and

h
t
= h
z

u
z
:
_
2
+
2
_
e
t
= e
z
+
u
z
h
z
(II.4)
_
2
+
2
_
h
t
= h
z

u
z
e
z
(II.5)
The dierential equations governing the longitudinal components can then be
formulated as :
_
2
+
2
+
2
_
e
z
=

e
t
(II.6)
_
2
+
2
+
2
_
e
z
=

h
t
(II.7)
These equations are in general quite complicated. In many conventional waveg-
uides, and are piecewise homogeneous, so that the right-hand side of equa-
tions (II.6) and (II.7) vanish. Even so, these equations remain complicated
since the various elds components are coupled through the boundary condi-
tions. In general, the solutions of the boundary value problem possess a full
suite of components. In certain cases, it may be possible to nd either a TE
(e
z
= 0) or TM (h
z
= 0) solution. Equation (II.4) and (II.5) ensure that TEM
(e
z
= 0 = h
z
) exist only in a domain of homogeneous with the eigenvalue
satisfying =
2
. This forbids TEM solutions in the presence of multiple
dielectrics, as often exist in open planar waveguides or waveguides bounded by
lossy conductors.
II.2.2 Waveguide voltage and current
For every mode propagating in the forward direction, described by
_
e
t
,

e
z
,

h
t
,
h
z
, there exists a mode propagating in the opposite direction and and satis-
fying equations (II.4)(II.7) with propagation constant () and components
_
e
t
,
e
z
,
h
t
,

h
z
. This latter is the backward propagating mode.

In general, the total elds

E and

H in a single mode of the waveguide are
linear combinations of the forward and backward mode elds. Their transverse
components can therefore be represented by :
E
t
= C
+
e
z
e
t
+ C
e
z
e
t

V
V
c
e
t
(II.8)
H
t
= C
+
e
z
h
t
C
e
z
h
t

I
I
c
h
t
(II.9)
where V and I are the waveguide voltage and the waveguide current. The
normalisation constants V
c
and I
c
were originally suggested by Marks and
Williams in [II.1]. They allow V and V
c
to have the units of voltage, I and I
c
II-3
those of current, while

E
t
,

e
t
,

H
t
and

h
t
have the units appropriate to elds.
Omitting V
c
and I
c
forces to use unnatural dimensions.
One interesting consequence of the formulation of (II.8)(II.9) is that the
normalised forward mode has waveguide voltage V(z) = V
c
e
z
and waveguide
current I(z) = I
c
e
z
. For the normalised backward-propagating mode, the
waveguide voltage and current are : V(z) = V
c
e
+z
and I(z) = I
c
e
+z
.
II.2.3 Power
The net complex power P(z) crossing a given transverse plane is given by the
integral of the Poynting vector over the cross section 5 :
P(z) =
_
S
E
t

H
t
u
z
dS =
V(z) I
(z)
V
c
I
c
P
c
(II.10)
where the absence of the 1/2 factor is due to the use of phasers. The power P
c
is dened as :
P
c

_
S
e
t

h
t
u
z
dS (II.11)
In accordance with the analogy to electrical circuit theory, one requires that :
P = V I
(II.12)
This can not be achieved with arbitrary choices of the normalisation constants
V
c
and I
c
, so that the following constraint must be imposed :
P
c
= V
c
I
c
(II.13)
which allows equations (II.10) and (II.12) to be simultaneously satised. Either
V
c
or I
c
may be chosen arbitrarily; the other is determined by equation (II.13).
The magnitude of P
c
depends on the normalisation which determined the modal
elds

e and

h ; in fact, equation (II.13) can even be used to specify the
normalisation. The phase of P
c
does not depend on this normalisation since the
phase relationship between

e and

h is xed, to within a sign, by Maxwells
equations. This sign ambiguity can be resolved by explicitly distinguishing
between the forward and backward modes. The most concise means of making
this distinction is to dene the forward mode as that in which the power ows
in the +z direction; that is :
Re(P
c
) 0 (II.14)
II.2.4 Characteristic impedance
The forward-mode characteristic impedance can then be dened by :
Z
c

V
c
I
c
=
V
c
2
P
c
=
P
c
I
c
2
(II.15)
II-4
The equivalence of these expressions again demonstrates the analogy to elec-
trical circuit theory. According to Brews, [II.4], Marks, [II.1], and Schelkuno,
[II.5], the equivalence of the three denitions of Z
c
follows from equation (II.13).
The three denitions would in general be inconsistent if P
c
, V
c
and I
c
were de-
ned independently for example, in terms of some power, voltage drop and
current in the waveguide without regard to (II.13).
Z
c
is independent of the normalisation of the modal elds

e and

h which
aected [P
c
[. While its magnitude does depend on the choice of either V
c
or
I
c
, its phase is independent of all normalisations. As pointed out by Brews,
[II.6, II.4], the phase of the characteristic impedance Z
c
of the mode is a xed,
inherent and unambiguous property of the mode. Equations (II.14) and (II.15)
constrain the sign of Z
c
such that :
Re(Z
c
) 0 (II.16)
In order to illustrate the close correspondence between this denition of Z
c
and conventional denitions of the characteristic impedance, the special case of
TE, TM and TEM modes in homogeneous matter is considered. Each of these
has elds which satisfy :
u
z

e
t
=
h
t
(II.17)
where the wave impedance is constant over the cross section. In this case,
Z
c
=
V
c
2
_
S
e
t
2
dS
(II.18)
Since the modal eld
e
t
is normalised, the denominator is xed. The magnitude
of Z
c
therefore depends only on V
c
. However, the phase of the characteristic
impedance is equal to that of the wave impedance. This corresponds to most
conventional denitions.
For TEM modes, is equal to the intrinsic wave impedance
_
/ ( 377
in free space), with the result that :
arg(Z
c
) =
1
2
_
arg() arg()
(II.19)
For example, if is real, then arg(Z
c
) =
1
2
where tan Im()/ Re() is
the dielectric loss tangent. When V
c
is chosen to be the voltage between the
ground and signal conductors, Z
c
is equal to the conventional TEM character-
istic impedance.
II.2.5 Normalisation of waveguide voltage and current
Although the phase of either V
c
or I
c
can be chosen arbitrarily, the choice is
of little signicance. The important quantity is the phase relationship between
V
c
and I
c
, which, due to the constraint (II.13) and the fact that the phase of P
c
is xed, is unalterable. The phase relationship between V
c
and I
c
is a unique
property of the mode.
II-5
The magnitude of Z
c
is determined by the choice of V
c
and I
c
. Given the
constraint (II.13) and having selected a modal eld normalisation, a value may
be assigned to only one of the two variables.
1. One useful normalisation denes the constant V
c
by analogy to a voltage
using a line integral along the path L :
V
c
=
_
L
e
t

u
l
dl (II.20)
The path L is conned to a single transverse plane. The integral does
not in general represent a potential dierence because it depends on the
path between a given pair of points.
2. Another widely used normalisation denes the constant Z
c
as the current
owing along the axial direction in the principal conductor. The cross
section 5
cond
lies in the transverse plane and its normal

u
n
points along
u
z
.
I
c
=
_
S
cond
e
z

u
n
dS (II.21)
The choice of either scheme 1 or 2 is purely a matter of convenience, dictated
by the type of waveguide considered and the applications which are envisioned.
In particular, when dealing with small devices embedded in transmission lines,
it is very useful to ensure that either the waveguide voltage V or the I correspond
to the voltage or current experienced by these loads.
In the case of coplanar waveguides (CPW) on SOI substrates, the domi-
nant propagation mode is of the TM type, in fact a quasi-TEM mode see
appendix A. Marks pointed out in [II.1], that in such case, the integral in (II.20)
depends only on the end-points, not on the path between them.
Considering loads embedded in a typical CPW on SOI, the normalisation
scheme 1 seems more appropriate for shunt loads. The integration path L can
indeed be chosen so that its end-points correspond to the terminals of the
loads. In the case of a small shunt resistor, this will ensure that the measured
high-frequency conductance will correspond to the measured DC-value. For
series loads, the scheme 2 is more appropriate for identical reasons. As the
dominant propagation mode of the CPW is quasi-TEM, the dierence in the
amplitude of Z
c
resulting from scheme 1 or 2 may be expected to be relatively
small. Typically around 5 %, [II.7].
II.2.6 Transmission line equivalent circuit
In analogy with classical transmission line theory it is possible to dene a dis-
tributed equivalent circuit for a single waveguide mode. Brews, [II.4], proposed
to base the denition of the distributed immittances on the following equations :
Z
Z
c
(II.22)
Y
/Z
c
(II.23)
II-6
II.3 General waveguide circuit theory
These denitions allow to derive expressions of the distributed immittances
Z
and Y
in terms of the modal elds

e and

h . Details are presented in
appendix A.
In this section, the previous results are applied to develop a waveguide cir-
cuit theory. This theory will provide the tools necessary to describe the mi-
crowave on-wafer measurement system. Travelling waves, pseudo-waves and
power waves are discussed rst. Then the scattering and pseudo scattering
matrices are introduced, followed by the transfer matrix and the impedance
matrix. Finally, the transformation of reference impedance is investigated and
the question of the load impedance is discussed.
II.3.1 Travelling wave intensities
The forward and backward travelling waves are dened according to Marks and
Williams, [II.1], by normalising the forward and backward modes with respect
to power :
a
c

_
Re(P
c
) C
+
e
z
=
_
Re(P
c
)
2 V
c
_
V + Z
c
I
_
(II.24a)
b
c

_
Re(P
c
) C
e
+z
=
_
Re(P
c
)
2 V
c
_
V Z
c
I
_
(II.24b)
This normalisation ensures that, in the absence of the backward wave, the unit
forward wave with a
c
= 1 carries unit power.
It can be shown that a
c
and b
c
are independent of the arbitrary normali-
sation of V
c
. While their phases depend on the phase of the modal eld

e
t
in
the same way that C
+
and C
do, a
c
and b
c
are independent of the magnitude
of

e
t
. This normalisation independence suggests that a
c
and b
c
are physical
waves rather than simply mathematical artifacts.
Expressing the waveguide current and voltage in function of the travelling
waves a
c
and b
c
, one may then apply equation (II.12) to obtain the net real
power as a function of a
c
and b
c
:
V(z) =
V
c
_
Re(P
c
)
_
a
c
(z) + b
c
(z)
_
(II.25)
I(z) =
I
c
_
Re(P
c
)
_
a
c
(z) b
c
(z)
_
(II.26)
Re(P(z)) = [a
c
(z)[
2
[b
c
(z)[
2
+ 2 Im(a
c
(z) b
c
(z))
Im(Z
c
)
Re(Z
c
)
(II.27)
This demonstrates that the net real power crossing a reference plane is not
equal to the dierence of of the powers carried by the forward and backward
waves acting independently, except when the characteristic impedance is real
or when either a
c
or b
c
vanishes.
II-7
The reection coecient
c
is dened by :
c
(z)
b
c
(z)
a
c
(z)
(II.28)
It is related to the voltage standing wave ratio, VSWR, which is usually mea-
sured by the slotted waveguide technique :
VSWR
max
z
E
t
(z)
min
z
E
t
(z)
=
max
z
V
c
(z)
min
z
V
c
(z)
a
c
b
c
a
c
b
c
=
1 +
(II.29)
The reection coecient is however not a power reection coecient, and it
may exceed 1 if Z
c
is not purely real.
Particular values of
c
occur in the presence of a short circuit or of an open
circuit, dened, respectively, as a perfectly conducting wall, or a magnetic
wall, spanning the entire cross section of the waveguide. The conducting wall
forces the tangential electric eld to vanish at the reference plane and therefore
requires V = 0 and b
c
= a
c
. As a result, the reection coecient of the short
is 1. The magnetic wall forces the tangential magnetic eld to vanish and
hence I = 0 and b
c
= a
c
. The reection coecient of the open is thus +1.
II.3.2 Pseudo-waves
A new set of parameters will now be introduced, the pseudo-waves, which in
contrast to the travelling waves, are mathematical artifacts, but with rather
convenient properties. Pseudo-waves are a formal generalisation of the travel-
ling waves, based on the choice of an arbitrary reference impedance Z
r
, with
the sole stipulation that Re(Z
r
) 0. According to Marks and Williams, [II.1],
the complex pseudo-wave amplitudes can the be dened by :
a
V
c
V
c
_
Re(Z
r
)
2
Z
r
_
V + Z
r
I
_
(II.30a)
b
V
c
V
c
_
Re(Z
r
)
2
Z
r
_
V Z
r
I
_
(II.30b)
These equations may be inverted and the real net power crossing a transverse
plane evaluated in function of the newly dened parameters :
V =
V
c
V
c
Z
r
_
Re(Z
r
)
_
a + b
_
(II.31)
I =
V
c
V
c
Z
r
_
Re(Z
r
)
_
a b
_
(II.32)
Re(P) = [a[
2
[b[
2
+ 2 Im(a b
)
Im(Z
r
)
Re(Z
r
)
(II.33)
Comparing equations (II.24) and (II.30), one can see that a(Z
r
= Z
c
) =
a
c
and b(Z
r
= Z
c
) = b
c
. Although the multiplicative factor in (II.30) is
II-8
complicated, it is the only factor that satises this criterion and also ensures
that a and b satisfy the simple power expression II.33.
Since pseudo-waves are equivalent to the actual travelling waves when the
reference impedance is equal to the characteristic impedance of the mode, this
is the natural choice of reference impedance. On the other hand, it is not
always the most convenient choice. For instance, when Z
c
varies greatly with
frequency as is the case for CPW on low-resistivity SOI substrates the
resulting measurements using Z
r
= Z
c
may be dicult to interpret; a constant
Z
r
may be preferable.
Another choice of reference impedance is in common use : that which makes
(Z
r
) vanish at a given point on the line. The primary eect of this choice of
Z
r
is to make the pseudo-reection coecient b/a vanish. As discussed
later in this chapter, several calibration schemes force the pseudo-reection
coecient of some standard termination, usually a resistive load, to vanish.
Those schemes thereby impose this particular choice of reference impedance.
Interestingly, the open and the short circuit, I
c
= 0 and V
c
= 0, respec-
tively, result in pseudo-reection coecient values which are independent of
Z
r
:
open
= +1 and
short
= 1.
II.3.3 Power-waves
In addition to the travelling waves and the pseudo-waves, other quantities
may be dened using linear combinations of V and I. A popular alternative
are the power-waves rst introduced by Belevitch, [II.8, II.9], and revisited by
Kurokawa in his famous paper [II.10] :
a
V + Z
p
I
2
_
Re(Z
p
)
(II.34a)
b
V Z
p
I
2
_
Re(Z
p
)
(II.34b)
where Z
p
is the impedance of the generator either source if turned on or
sink if turned o connected at the some waveguide port.
The power-waves were devised specically to satisfy the following equation
independently of the value of Z
p
:
P Re(V I
) =
2
(II.35)
where P is the net real power transfered at the port. Equation II.34 shows that
when V/I = Z
p
, the quantity b vanishes. In other words when the generator

is conjugate matched to the loading waveguide circuit, P = P
av
=
2
. The
quantity a is thus an intensity corresponding to the available power of the
generator, P
av
.
When Z
p
is real, the power-waves reduce to pseudo-waves with Z
r
= Z
p
.
Otherwise they do not coincide. The power-waves are not equal to the travelling
waves for any choice of Z
p
unless the characteristic impedance is real.
II-9
Power-waves have some peculiar properties. For instance, they are not as
easily connectable as pseudo-waves or current and voltage are. At the junc-
tion of two identical waveguides characterised by their own inward referential
system, the continuity of the electric and magnetic elds must be imposed,
translating into the following connection rules :
V
1
= V
2
(II.36)
I
1
= I
2
(II.37)
b
1
= a
2
(II.38)
a
1
= b
2
(II.39)
For the power-waves, however, the continuity of the electric and magnetic elds
translates into the following awkward connection rules :
_
b
1
a
1
_
=
1
Re(Z
p
)
_
Re(Z
p
) Im(Z
p
)
Im(Z
p
) Re(Z
p
)
_ _
a
2
b
2
_
(II.40)
These counter-intuitive rules are related to the fact that the net power crossing
a plane is not simply the dierence of the power carried by the travelling waves
considered independently. When the port impedance Z
p
is real, the connection
rules coincide with those of the pseudo-waves.
Another remarkable peculiarity of the power-waves, is that their reection
coecient b/a is not generally equal to 1 in the case of a short circuit,
V = 0, but rather :
short
=
Z
p
Z
p
(II.41)
These considerations illustrate the fact that power-waves are not a judicious
concept to use when attempting to measure devices embedded in lossy waveg-
uides which are characterised by a complex Z
c
. Marks and Williams develop
the argument further in [II.1], stating that no specic calibration technique
exist which allows direct measurement of power-waves and that modication
of existing calibration methods to measure power-waves rather than pseudo- or
travelling waves is not feasible. At present, the only method to measure a
power-wave reection coecient is to deduce it from the pseudo-wave reec-
tion coecient, provided the reference impedance is known. The impossibility
to measure directly the power-wave reection coecient, does not preclude
the value of this concept as a design tool for microwave circuits, particularly
ampliers and lters.
II.3.4 Load impedance
At a reference plane, at which only a single mode exists, the load impedance is
dened in terms of the waveguide voltage and current :
Z
load

V
I
(II.42)
II-10
The load impedance, like I and V is independent of the reference impedance.
Unlike the result of low-frequency circuit theory, however, Z
load
is not a unique
property of the one-port itself but instead depends on the elds of the mode
incident upon it. Illumination of the same device by a dierent waveguide,
or even a dierent mode of the same waveguide may result in a drastically
dierent Z
load
. Z
load
also depends on the normalisation which determines V
c
and I
c
for this aects V and I. Combining equations II.42, II.32 and II.31, the
load impedance can be related to the reection coecient :
load
(Z
r
) =
Z
load
Z
r
Z
load
+ Z
r
(II.43)
This equation may also be solved for Z
load
:
Z
load
= Z
r
1 +
load
(Z
r
)
1
load
(Z
r
)
(II.44)
This produces the same result regardless of the reference impedance with re-
spect to which
load
is dened. If Z
r
is chosen equal to the characteristic
impedance Z
c
, these two equations become identical to those of ordinary waveg-
uide circuit theory.
Equation (II.43) denes the reection coecient
load
as a bilinear trans-
form of the normalised load impedance z
load
Z
load
/Z
r
. Interesting properties
of this class of transforms is that circles and lines circles of innite radius
in the plane of complex impedances z
load
are mapped onto circles in the com-
plex reection coecient plane and vice-versa. Particular cases are
load
= 1
which corresponds to the open circuit Z
load
= , and
load
= 1 which cor-
responds to the short circuit Z
load
= 0, both independently of the actual value
of Z
r
. These features form the basis of the Smith chart, where normalised
resistance and reactance loci are represented as circles or arcs.
In the case of complex port impedances, the expression of the power reec-
tion coecient in function of the load impedance is not a bilinear transforma-
tion of the normalised impedance z
load
Z
load
/Z
p
:
load
(Z
p
) =
Z
load
Z
p
Z
load
+ Z
p
(II.45)
This prohibits the application of the Smith chart and its associated constructs
to the power reection coecient normalised to complex port impedances.
II.3.5 Scattering matrix for pseudo-waves
A linear waveguide circuit is considered which connects an arbitrary number
of (generally) non identical, uniform semi-innite waveguides which are uncou-
pled away from the junction. In each waveguide, a cross-sectional reference
plane is chosen at which only a single mode exists. If the mode of interest is
dominant, this can be ensured by choosing the reference plane suciently far
from the junction so that higher-order modes have decayed to insignicance.
For each waveguide port i, a reference impedance is chosen Z
r(i)
, in terms of
II-11
which the pseudo-wave amplitudes a
i
(Z
r(i)
) and b
i
(Z
r(i)
) at port i are dened
by equations (II.30). The orientation is such that the forward direction is to-
ward the junction. Column vectors are dened which contain the pseudo-wave
amplitudes :
b =
_
_
b
1
.
.
.
b
N
_
_
a =
_
_
a
1
.
.
.
a
N
_
_
(II.46)
The vector of outgoing pseudo-waves b is linearly related to the vector of in-
coming pseudo-waves a by the pseudo-scattering matrix S :
b = S a (II.47)
Although S depends on the choice of reference impedance at each port, explicit
reference to this fact has been suppressed to simplify the notations.
Likewise, vectors containing incoming and outgoing travelling wave inten-
sities, a
c
and b
c
, can be dened. These vectors are related by the (true)
scattering matrix S
c
:
b
c
= S
c
a
c
(II.48)
If Z
r(i)
= Z
c(i)
for each port i, the S = S
c
. In other words, the pseudo-
scattering matrix is equal to the scattering matrix, when the reference impedance
at each port is chosen equal to the respective characteristic impedance. A typ-
ical example is the scattering matrix of a waveguide section of length L :
S =
_
0 e
L
e
L
0
_
(II.49)
The reection coecient
c
is the single elements scattering matrix S of a
one-port.
II.3.6 Transfer matrix
In the case of a linear waveguide circuit possessing an even number of access
ports, the transfer matrix can be dened. The denition relies on the classi-
cation of ports as input or output accesses, the number of inputs and outputs
being equal. Let b
i
denote the vector of outgoing pseudo-waves at the input
ports and b
o
the outgoing pseudo-waves at the output ports. a
i
and a
o
denote
the incoming pseudo-waves at the input and output ports, respectively. The
wave vectors at the input and output ports are then linearly related by the
transfer matrix :
_
b
i
a
i
_
= T
_
a
o
b
o
_
(II.50)
In order to relate the transfer matrix T to the scattering matrix S, it is rt
necessary to ensure that this latter is properly organised:
_
b
i
b
o
_
= S
_
a
i
a
o
_
=
_
S
ii
S
io
S
oi
S
oo
_ _
a
i
a
o
_
(II.51)
II-12
The transfer matrix T is then given by :
T =
_
S
io
S
ii
S
1
oi
S
oo
S
ii
S
1
oi
S
1
oi
S
oo
S
1
oi
_
(II.52)
The transfer matrix of a waveguide section of length L referred to the charac-
teristic impedance Z
c
can be obtained from equation (II.49) above,
T =
_
e
L
0
0 e
+L
_
(II.53)
The transfer matrix of a cascade of compatible multi-port circuits is simply
the product of the individual transfer matrices as long as the connecting ports
are composed of identical waveguides, with identical reference impedances,
joined without discontinuity. The denition of the transfer matrix implies
some preferential forward direction, from the input ports to the output ports.
A transfer matrix may equally well be dened in the opposite, reverse direction.
T
rev
is however not equal to the inverse of T
for
:
_
b
i
a
i
_
= T
for
_
a
o
b
o
_
(II.54)
_
b
o
a
o
_
= T
rev
_
a
i
b
i
_
(II.55)
T
rev
=
_
0 I
I 0
_
T
1
for
_
0 I
I 0
_
(II.56)
where 0 is the null matrix of dimension
N
2
; I is the identity matrix of dimension
N
2
; N being the total number of ports.
II.3.7 Immittance matrices
The impedance matrix Z and the admittance matrix Y relate the column vec-
tors V and I, whose elements are the waveguide voltages and currents at the
various ports :
V = Z I (II.57)
I = YV (II.58)
In contrast to S and T, Z and Y are independent of the reference impedance
since V and I are also. This makes them particularly interesting for metro-
logical purposes. Also, most of the existing active device models are based
on predictions of charge and currents in function of applied voltages, so that
their equivalent circuits are naturally formulated in terms of admittance or
impedance.
According to Marks and Williams, [II.1], the relation between Z and S is :
S = U
_
Z Z
r
__
Z +Z
r
_
1
U
1
(II.59)
II-13
and inversely :
Z =
_
I U
1
S U
_
1
_
I +U
1
S U
_
Z
r
(II.60)
Here Z
r
is a diagonal matrix whose elements are the Z
r(i)
and U is another
diagonal matrix dened by :
U diag
_
V
c(i)
V
c(i)
_
Re(Z
r(i)
)
Z
r(i)
_
(II.61)
Marks and Williams claim that the factor U generalises previously published
results to problems including complex elds and reference impedances. Similar
results may be obtained for the admittance matrix Y, which is the inverse of
Z.
II.3.8 Change of reference impedance
As discussed earlier, the most convenient choice of reference impedance de-
pends on the circumstances. In order to accommodate the various choices, the
relationship between the pseudo-wave amplitudes based on dierent reference
impedances is considered. By expressing a(Z
rn
) and b(Z
rn
) in terms of V and
I using equation (II.30) and then V and I in terms of a(Z
rm
) and b(Z
rm
) using
equations (II.31) and (II.32), the following linear relationship can be obtained :
_
a(Z
rn
)
b(Z
rn
)
_
= Q
nm
_
a(Z
rm
)
b(Z
rm
)
_
(II.62a)
where the impedance transformation matrix is given by :
Q
nm

_
1 Im(Z
rm
)/ Re(Z
rm
)
1 Im(Z
rn
)/ Re(Z
rn
)
1
1
2
nm
_
1
nm
nm
1
_
(II.62b)
nm

Z
rm
Z
rn
Z
rm
+ Z
rn
(II.62c)
Marks and Williams, [II.1], pointed out that (II.62) constitutes the exact
expression of a complex impedance transform. Pseudo-waves can hence be ac-
curately referred to as impedance-transformed travelling waves. Interesting
properties of the transforms are that :
1. Two consecutive transforms can be represented as a single transform by
from the initial to the nal reference impedance by :
Q
nm
Q
mp
= Q
np
(II.63)
2. The transform from a reference impedance to itself is represented by the
identity matrix :
Q
nn
= I (II.64)
II-14
II.4 Measurement set-up
3. As a result the inverse transformation is represented by :
_
Q
nm
1
= Q
mn
(II.65)
Equation (II.62) allows to evaluate the eect of the complex impedance
transformation on the reection coecient. The reection coecient is trans-
formed by :
(Z
rn
) =

nm
+ (Z
rm
)
1 +
nm
(Z
rm
)
(II.66)
This expression conrms the statement made previously that the reection of
the perfect short and open circuits is independent of the reference impedance.
(Z
rm
) = 1 indeed results in (Z
rn
) = 1, and (Z
rm
) = +1 in (Z
rn
) = +1
independently of
nm
. The unique status of the short and open is related to
their unique physical manifestation. A perfect match (Z
rm
) = 0 results in
(Z
rn
) =
nm
. Conversely, if (Z
rm
) =
nm
then (Z
rn
) = 0.
II.4 Measurement set-up
Figure II.1 shows the ow-chart of the on-wafer measurement setup. The vector
network analyser (VNA) is connected by 90 cm coaxial cables to the on-wafer
probes which launch the signal in a coplanar waveguide structure on the SOI
wafer. Reected and transmitted signals from the device-under-test (DuT)
travel back to the analyser, are picked-up by the directional couplers, detected,
and normalised with respect to the emitted signal to give the raw S-parameters
readings.
Systematic errors. At 1.0 GHz, the wavelength in the coaxial cables is on
the order of 20 cm, so that signals travelling through the system experience
important phase-shifts. The total attenuation from the cabling and probes at
the same frequency lies around 1.0 dB. The signals are nally also aected
by multiple reections caused by the connectors at the cables ends and the
waveguide transitions occurring inside the probes.
The combination of all these eects tend to mask the inuence of the DuT
on the raw VNA readings. The calibration methods developed in section II.5
characterise the systematic errors of the measurement systems and allow to
correct them. They are however constrained in their accuracy by hardware
limitations such as the nite directivity of the couplers, the dynamic range of
the receivers, the noise level, ..., which tend to put a lower bound on the level of
the DuT signals which can be discriminated from parasitic system responses.
To keep the measurement accuracy to an acceptable level, it is of primary
importance to limit the total attenuation of the measurement system as well as
the number of sources of signal reections. In practice, this means the use of the
shortest possible length of cable with the minimum number of interconnections.
II-15
O
n
-
w
a
f
e
r
c
h
a
r
a
c
t
e
r
i
s
a
t
i
o
n
a
t
m
i
c
r
o
w
a
v
e
f
r
e
q
u
e
n
c
i
e
s
SOI Wafer
Wiltron 360B Vector Network Analyser
DuT
Probe Probe
CPW CPW
Coaxial Cable Coaxial Cable
Directional Couplers Directional Couplers
Matched Load
Source
Switch
Receiver Receiver Receiver Receiver
2 dB
90 cm, 3 dB
245 m, 0.5dB 245 m, 0.5 dB
90 cm, 3 dB
2 dB
a
A
b
B
a
B
b
A
b
1
a
1
a
2
b
2
Figure II.1: Flow-chart of the measurement setup. Line lengths and maximal attenuation (at 40 GHz) are given.
I
I
-
1
6
II.5 Calibration methods
Repeatability errors. Calibration schemes do not correct for random or
repeatability errors. The possible sources of such errors must be well controlled.
The most delicate issue is, in the case of on-wafer probing, the repeatability of
the signal launch from the probes to the coplanar waveguide.
Positioning : Horizontal position is important, as any oset of probe
position in the axial direction will translate into a similar oset of the ref-
erence planes, which may signicantly inuence the apparent performance of
small devices. Using adequate positioning marks, it was possible to reduce
the uncertainty in axial position below 10.0 m, probably around 5.0 m. This
latter value translates into a 2.0 % uncertainty on the parasitic capacitances of
a typical MOSFET.
Contacts : A second important factor is the quality of the three contacts
established by the probe with the metal of the CPW. In the case of an alu-
minium metallisation, which is a rather soft material covered by a thin rigid
oxide layer, the probe-tips must be able to cut through the oxide and establish
contact with the metal on a wide area. Narrow probe tips below 5.0 m
tend to pierce through the metallisation and reach the underlying insula-
tion layer. Skating motions induced by vibrations then repel the metal away
from the probe tips until the contact is broken. Carbonero et al., [II.11], have
shown that tungsten probe-tips making 20 m wide footprints are an adequate
solution for aluminium metallisations.
In order to obtain three simultaneous contacts of good quality one for
the signal conductors, two for the ground the planarity of the probe with
respect to the landing pads must be carefully checked. A mismatch in the resis-
tance of the ground contacts can cause an unbalanced excitation of the CPW,
generating unwanted modes and modifying the apparent value of the scattering
parameters. It has been experienced that a single deteriorated ground contact,
hardly detectable by DC resistance measurements of an integrated short cir-
cuit, modies the apparent scattering parameters of that device substantially,
in a way which recalls the inuence of a large inductance.
The most important VNA calibration methods will be reviewed in this section.
Their characteristic features will be analysed in function of the specic needs
of on-wafer measurements.
The purpose of calibration is to characterise the measurement apparatus in
terms of some model in order to be able to remove unwanted inuences on the
measurements. VNA calibration methods characterise the network analyser
together with its cables and probes as a linear waveguide circuit, according to
the theory of section II.3. De-embedding techniques then allow to evaluate the
scattering parameters of a device connected at the reference planes from the
measurements of the distant network analyser. For on-wafer characterisation,
it is particularly interesting to able to locate the reference planes on the silicon
II-17
wafer as close as possible to the devices. This allows to remove probe-pad
parasitics from the device response by absorbing them into the measurement
apparatus. Appending the probe-pads to the apparatus requires to have strictly
identical pads for all devices, including the calibration structures.
This major constraint can practically only be met by implementing the
calibration structures with the adequate probe-pads in-situ on the wafer, in
the vicinity of the devices to be tested. This in order to reduce the variation
of substrate and metallisation parameters to a minimum. Implementation of
calibration structures to very strict absolute requirements in a CMOS SOI tech-
nology is rather an utopia. A more realistic approach is to fabricate calibration
structures that can be used as transfer standards. The notion of transfer stan-
dard is taken here in the broad sense, meaning either structures characterised
with respect to a master calibration or structures whose parameters may be
accurately determined a posteriori.
II.5.1 The transfer-matrix formalism
Several authors [II.12, II.13] have shown that, in the absence of leakage at the
reference planes, the network analyser together with its cables and probes could
be rigorously modelled by two transfer matrices, one for each port.
_
b
A
a
A
_
= T
A
_
b
1
a
1
_ _
b
1
a
1
_
= T
DuT
_
a
2
b
2
_ _
b
B
a
B
_
= T
B
_
a
2
b
2
_
(II.67)
The VNA is supposed to measure the waves b
A
and a
A
at its rst port, and b
B
and a
B
at its second. The VNA usually operates in two modes, the forward and
the reverse mode. In the forward mode, denoted by index f, the microwave
source is connected to port A, emitting a wave a
Af
. In the reverse mode denoted
by index r, the microwave source is connected to port B, emitting a wave
a
Br
. Due to the nite isolation of the internal switch some leakage will occur,
so that a
Bf
and a
Ar
are rarely exactly zero. Combining the readings in the
forward and the reverse mode, the basic measurement equation is obtained :
_
b
Af
b
Ar
a
Af
a
Ar
_
. .
M
A
= T
A
T
DuT
T
B
1
_
a
Bf
a
Br
b
Bf
b
Br
_
. .
M
B
(II.68)
where T
B
1 stands for the reverse transfer matrix at port B. It should be
noted that :
Equation (II.68) allows some level of indetermination in the error coe-
cients. Indeed, multiplying T
A
and T
B
by the same scalar constant does
not aect the result.
Strictly speaking, equation (II.68) is only valid when the device-under-test
, DuT, has a non zero forward transmission. It will be shown next how
this equation can be modied to be able to deal with double one-ports.
II-18
Normalised error-boxes
In order to lift the indetermination on the error matrices T
A
and T
B
, the
normalised transfer matrix is introduced :
T
X
= t
X
t
X
t
X

_
t
X11
t
X12
t
X21
1
_
(II.69)
The reverse normalised transfer matrix is dened as :
T
X
1 =
1
t
X
T
X
1 (II.70)
These denitions allow to transform the measurement equation (II.68) into :
M
A
=
t
A
t
B
T
A
T
DuT
T
B
1 M
B
(II.71)
Where it appears clearly that the level of the constants t
A
and t
B
can be
chosen arbitrarily, as long as their ratio is kept equal to the value imposed by
the calibration.
Double one-ports
A double one-port is a two-port device with zero forward and reverse trans-
mission. It will be shown below, that det(M
B
) is in all cases proportional to
the forward S-parameter of the DuT, S
DuT
. This will allow to formulate a
modied measurement equation which is valid in all situations.
Multiplying the equation (II.68) on both sides with the transposed adjoint
matrix of M
B
, denoted

M
B
, yields :
M
A
M
B
=
t
A
t
B
T
A
T
DuT
T
B
1 det(M
B
) (II.72)
Other algebraic manipulations and the substitution of T
DuT
by its expressions
in S-parameters give :
t
A
t
B
T
1
A
M
A
M
B
T
1
B
1
=
det(M
B
)
S
DuT21
_
det(S
DuT
) S
DuT11
S
DuT22
1
_
(II.73)
This last equation clearly shows that, when non-zero, the forward transmission
is directly proportional to det(M
B
). Looking at the ow-chart of the measure-
ment setup, [II.14], one can see that if the DuT has no forward transmission
then the apparent reection coecient at port B,
B
b
B
/a
B
, has a unique
value depending principally on the reection coecient seen at the DuT, both
in forward and in reverse mode. As result, det(M
B
) is also zero.
The determinant of the readings matrix M
B
being at all times proportional
to S
DuT
, the modied measurement equation presented below is valid in all
cases.
M
A
M
B
=
t
A
t
B
T
A
T
DuT
T
B
1 (II.74a)
where T
DuT
det(M
B
) T
DuT
(II.74b)
II-19
De-embedding formula
Heuermann and Schiek published in [II.15] the following de-embedding formu-
lae, which are robust and computationally quite ecient :
C

T
A
M
A
M
B
_
0 1
1 0
_
T
B
_
0 1
1 0
_
(II.75a)
S
11
=
C
12
C
22
(II.75b)
S
12
=
det(M
A
) det(T
B
)
C
22
(II.75c)
S
21
=
det(M
B
) det(T
A
)
C
22
(II.75d)
S
22
=
C
21
C
22
(II.75e)
where the denotes the transposed adjoint matrix.
II.5.2 SOLT procedure
The Open-Short-Load-Through calibration method is typically a transfer stan-
dard method. Indeed the implementations of the calibration structures in a
planar technology are aected by signicant parasitics which must be properly
characterised as the SOLT method requires accurate knowledge of all reection
coecients. The SOLT method has been used in the present work to extend the
bandwidth of the calibration beyond the limits imposed by the TRL method
presented below. A TRL calibration was rst performed, and the SOLT
structures were measured. An equivalent circuit was extracted and used to
predict the characteristics of the SOLT independently of the bandwidth limit
of TRL. This complicated procedure has however been rarely used, mainly be-
cause validity of TRL was found to extend far enough below the recommended
low-frequency limit.
The SOLT method proceeds in two steps : a single port calibration is
performed at each VNA port separately using the open, the short and the load;
then a two-port calibration is obtained by combining the single-port corrections
with a coecient deduced from the measurement of the through.
One-port calibration
The single port measurement is described by :
b
X
=
DuT
a
X
b
i
=
DuT
a
i
(II.76)
where is the raw reading of the VNA at port X, and is the pseudo-
reection coecient to be determined. The measurement equation can nally
be constructed as follows :
DuT
=
t
X11

DuT
+ t
X12
t
X21

DuT
+ 1
(II.77)
II-20
This last equation clearly shows that the normalisation constants t
A
and t
B
do
not inuence the one-port measurement.
Using the measurements of the short,
, the open,
o
and the load,
together with their known true characteristics,
,
o
and
, respectively, the
calibration equations may be formulated :
_
_
o
1
o
_
_
_
_
t
X11
t
X12
t
X21
_
_
=
_
_
_
_
(II.78)
Two-port calibration
When both VNAports are individually calibrated in reection, their normalised
transmission matrix is known. To be able to correct transmission measure-
ments, the ratio of the scaling factors t
A
and t
B
must be determined.
Marks and Williams, [II.1, II.16] investigated the eects of the electro-
magnetic reciprocity on the pseudo-scattering parameters. They concluded
that in all generality, the electro-magnetic reciprocity does not necessarily lead
to symmetry of the scattering matrix; It does result in symmetry in some par-
ticular cases, such as a junction with identical waveguides at all ports. The
scattering matrix of the through is thus symmetric, so that the determinant of
the its transfer matrix det(T
) is equal to 1. This property may be used to

determine t
A
/t
B
. From the two-port measurement equation (II.68),
det(M
A
) =
t
A
t
B
det(t
A
) det(T
)
. .
=1
det(t
B
1 ) det(M
B
) (II.79)
and nally :
t
A
t
B
=
det(M
A
) det(t
B
)
det(M
B
) det(t
A
)
(II.80)
The index indicates measurements of the through structure.
II.5.3 TAN self-calibration procedures
The TAN method makes use of the redundancy of the calibration equations to
compensate for the partial knowledge of the characteristics of the calibration
structures. This process, called self-calibration, consists in two steps : the
determination of the true characteristics of the calibration structures, followed
by the actual calibration of the system.
Calibration structures
Three structures are required : a through connection (T), a matched attenuator
or transmission line (A) and a symmetrical, not necessarily reciprocal, network
(N). The TAN method thus postulates the following form for the scattering
II-21
and transfer matrices of the calibration structures :
S
=
_
0 1
1 0
_
S
=
_
0 S
r
S
f
0
_
S
=
_
R
S
r
S
f
R
_
(II.81)
T
=
_
1 0
0 1
_
T
=
_
S
r
0
0 S
1
f
_
T
=
1
S
f
_
S
f
S
r
R
2
1
_
(II.82)
where index stands for the through, index for the attenuator or line and
index for the network. The consequences of these assumptions are the fol-
lowing, [II.1, II.12] :
1. The expression of S
forces to have identical reference impedances at both

ports. It also ensures that the reference planes are located in the middle
of the section of transmission line serving as through connection.
2. The shape of S
forces the reference impedance to be equal to the charac-

teristic impedance of the line, or to some more complicated combination
of the parameters of the attenuator, [II.1]. If the -structure is a pair of
identical one-port loads, then Z
r
is set equal to the load impedance.
3. The -structure serves essentially to lift the indetermination on the ratio
t
A
/t
B
.
The measurement equation (II.68) applied to the through-connection yields :
N
M
A
M
1
B
=
t
A
t
B
t
A
T
t
B
1 =
t
A
t
B
t
A
t
B
1 (II.83)
For the attenuator and the -device, the modied measurement equation (II.74)
is used in order to accommodate for a possible zero transmission :
N
M
A

M
B
=
t
A
t
B
t
A
T
t
B
1 (II.84)
N
M
A

M
B
=
t
A
t
B
t
A
T
t
B
1 (II.85)
where the modied transfer matrices are dened by :
T
det(M
B
) T
=
_
S
r
0
0 S
1
f
_
(II.86)
T
det(M
B
) T
=
1
S
f
_
S
f
S
r
R
2
1
_
(II.87)
Determining the characteristics of the standards
Combining equations (II.84) and (II.85) with (II.83) to eliminate t
B
1 yields
the following two equations :
N
N
1
= t
A
T
t
1
A
(II.88)
N
N
1
= t
A
T
t
1
A
(II.89)
II-22
Multiplying these two equations a third useful equation is obtained :
N
N
1
N
1
= t
A
T
t
1
A
(II.90)
These three equations show that the true characteristics of the calibration
structures on the right-hand side are related to the measurements by a
similarity transform dened by matrix t
A
. The properties of such a transform
are that the eigenvalues are conserved, as well as the determinant and the
trace. These features allow to determine the elements of T
and T
from the
measured data without any knowledge of t
A
.
Equation (II.88) is particularly interesting in this respect, as it establishes
that the transmission characteristics of the standard can be determined inde-
pendently of any assumption on the error networks t
A
and t
B
. This equation
can be easily generalised to coupled lines or multi-mode propagation : each
of the propagation constant can be determined from the eigenvalues of the
measurement matrix !
Following the method outlined by Eul and Schiek in [II.15], a set of ve
equations is obtained allowing to determine the ve unknowns :
trace(N
N
1
) = trace(T
) (II.91)
det(N
N
1
) = det(T
) (II.92)
trace(N
N
1
) = trace(T
) (II.93)
(II.94)
det(N
N
1
) = det(T
) (II.95)
trace(N
N
1
N
1
) = trace(T
) (II.96)
The -standard Solving equations (II.91) and (II.92) allows to determine
the transmission parameters of the -structure :
S
r
=

2
(II.97)
S
f
=
1
r
(II.98)
If the magnitude of S
r
is below a very small threshold, then the -structure is
most probably a double one-port and a sign distinction for S
r
is not necessary.
In the alternative, the sign ambiguity on the root for the normalised inverse
transmission S
r
must be lifted.
1. If there are signicant losses, then the right choice is the root which leads
to S
r
< 1 and S
r
< 1.
2. If the losses are expected to be small, then the root must be chosen
according to an approximate knowledge of the electrical length of the
-device.
II-23
The -standard The remaining equations (II.94)(II.96) yield :
S
f
=
1 S
f
S
r
S
f
_
_ (II.99)
S
r
= S
(II.100)
R
=
_
S
f
_
S
_
+ 1 (II.101)
The sign ambiguity in the third equation can be easily resolved using a priori
information on the phase of the reection coecient R
.
Solving for the error coecients
The resolution method shown below was published by Heuermann and Schiek,
[II.15]. It is robust, in the sense that the set of equations never becomes sin-
gular. Their original paper contains however several errors in the nal system
of equations. All these errors have been corrected in the expressions below,
which were extensively tested and veried, both by computer simulations and
experimentation.
The measurement equation (II.83) is solved for the product of the B error
coecients with the scaling factor :
t
B
t
B
t
A
= N
1
t
A
(II.102)
Substituting the results in equations (II.84) and (II.85), yields :
N
N
1
t
A
= t
A
T
(II.103)
N
N
1
t
A
= t
A
T
(II.104)
Only three equations are needed to determine the normalised coecients for
port A. From the set concerning the -standard, the equations involving the
forward and reverse transmission are used directly. From the set of equations
concerning the -standard, the sum of the two equations being linear with
respect to the reection coecient is used.
_
_
N
11
+ N
21
S
r
0 N
12
+ N
22
S
r
0 N
11
+ N
21
+ S
1
f
0
R
S
1
f
N
11
+ N
21
+ S
1
f
R
S
1
f
_
_
_
_
t
A11
t
A12
t
A21
_
_
=
_
_
0
S
1
f
N
12
N
22
S
1
f
N
12
N
22
_
_
(II.105)
where the following notations where used :
N
N
1
N
1
(II.106)
II-24
Line
Short
Open Through
50.0 Resistor
Figure II.2: Calibration kit allowing to perform a TRL calibration and to
determine the reference impedance.
Practical applications
The TAN procedure described in the previous subsections is generic. Many
practical calibration procedures may be derived. The most wide-spread are
the TRL, Through-Line-Reect and the TRM, Through-Match-Reect. Some
authors prefer to substitute the L of line to the T of through.
The TRL calibration The method relies on the measurements of two line
sections of dierent length and of a reection element, which is usually an
oset-short or oset-open. The scattering matrix of the line, the -standard
and of the reect, the -standard are given below :
S
=
_
0 e
(L
)
e
(L
)
0
_
(II.107)
S
=
_
e
(2L
)
0
0
e
(2L
)
_
(II.108)
L
and L
are the physical line lengths measured from end to end, L
is
the oset length, measured from the device itself to the end of the abutting
line. The propagation constant is a natural by-product of the calibration
method. This is allows to move the reference planes along the CPW, and
hence compensate oset lengths.
Because of the nite length of the transmission lines, the method is band-
limited. Indeed, in the absence of substantial losses, the system of equations
collapses at every frequency where the length dierence is a multiple of half a
wavelength. The system is considered to be numerically sound when :
9
Im
_
_
L
__
n
8
9
where n N (II.109)
II-25
The TRL algorithm has been used intensively for the present work. The
required calibration standards are easily implemented in a SOI CMOS tech-
nology, even with a single metallisation level. The imperative constraint of
symmetry for all calibration structures can be readily obeyed using a proper
layout. Horizontal non-uniformity in the SOI substrate and contact repeata-
bility were the principal problems encountered. To minimise the impact of a
sometimes poor contact repeatability, the reect standard is implemented as
a pair of open circuits. Open circuits are however very sensitive to the sub-
strate parameters, so that non-uniformity becomes critical. The problem may
be avoided by presenting the same individual structure to both ports alterna-
tively.
As indicated in the discussion about the calibration structures on page II-22,
it is the line standard which sets the reference impedance in the TRL algorithm.
The reference impedance Z
r
is set to the characteristic impedance Z
c
of the
line. This latter is generally unknown, as it depends in a complex fashion on
the substrate parameters, several of which being not accurately known. It is
thus necessary to nd some means of determining the reference impedance in
order to be able to exploit the measurement results. Several original solutions
to this problem have been developed. They are described in section II.6 below.
The TRM calibration The method uses two identical broadband loads as
-standard to set the reference impedance. Eul and Schiek introduced this
scheme in [II.17], with the idea that resistors would mimic innite transmission
lines, thereby resolving the bandwidth limitation of TRL. Resistors were fabri-
cated and precisely trimmed to 50.0 at DC, assuming that the load impedance
seen the by the coplanar waveguide at microwave frequencies would be equal to
this value. Williams and Marks, [II.18], warned against the inaccuracies result-
ing from that assumption and proposed to model the resistor parasitics with
an inductance which was determined with respect to a reference calibration.
The scattering matrices of the TRM standards have the following expres-
sions :
S
=
_
0 0
0 0
_
S
=
_
e
(2L
0
0
e
(2L
_
(II.110)
Major advantagse of the TRM method are that it requires only three cal-
ibration structures which can all be compactly implemented, and that it is
inherently broadband. The TRM method does not allow to determine the
propagation constant, so that the reference planes can not be moved.
TRM has never been used for in-situ calibrations on the SOI wafers. The
main reason is that to obtain a coherent calibration setting the referenc impedance
to some well dened value requires to fabricate a pair of identical resistors.
Systematic DC resistance measurement of microwave resistors designed to be
nominally 50.0 have shown that the discrepancies between matched resistors
were rarely lower than 5.0 % in the UCL technology. This was considered to
be too high to be tolerable for the TRM calibration. The discrepances are due
to the weak resistivity of the silicided polysilicon which was used as resistive
material. Weak resistivity translated into narrow strip widths, the length of the
II-26
II.6 Reference impedance determination
resistor being xed by the waveguide geometry. This narrow width rendered
the resistor very sensitive to lithographic process variations. A possible solu-
tion would have been to measure a single resistor alternatively at both ports.
This implies however a 180 degrees rotation of the wafer on the chuck wich is
a cumbersome manipulation. TRL was nally found much more adequate.
TRM calibrations using standards on a commercial alumina substrate were
nevertheless routinely applied as a preliminary to the in-situ TRL on SOI. The
purpose of this calibration was mainly to locate the reference planes suciently
close to the probe-tips to render fault detection easier during the measurement
of the SOI calibration structures. The alumina TRM calibration eventually
served as reference calibration for the calibration comparison method devel-
opped in section II.5.3.
Accurate knowledge of the reference impedance of a scattering parameters cal-
ibration is of primary importance. It is required in order to transform the
S-parameters to impedance or admittance, which are the basic parameters for
the description of integrated active or passive devices. The presence of di-
electric relaxation frequencies of the SOI substrate in the measurement band
causes important variations of the characteristic impedance of CPWs, which
in the case of a TRL calibration translate into important variations of the
reference impedance. A proper scheme for the determination of the reference
impedance is thus mandatory if one wants to exploit the results of an in-situ
TRL calibration.
II.6.1 Propagation constant measurement
Marks and Williams proposed in [II.19] to base the determination of the char-
acteristic impedance of a CPW on the following equation :
Y
= G
+ C
= /Z
c
(II.111)
On low-loss material, the conductance can be neglected with respect to
the susceptance, provided that the frequency is not so high that transverse
currents in the conductors become signicant. Furthermore, taking advantage
of the fact that the dominant mode of a CPW is of the quasi-TEM-type, they
proposed to compute C
theoretically from the waveguide dimensions using

the quasi-static approximation. This allows to reduce the determination of the
characteristic impedance to a propagation constant measurement.
As the propagation constant is a natural by-product of the TRL calibration
procedure, the present method is very well suited to estimate the reference
impedance of such a calibration. This approach is of course not suitable for
lossy substrates such as low-resistivity SOI wafers, where the contribution of
G
is non-negligible. Furthermore, due to the layered structre of the SOI

substrate, the capacitance C
varies importantly in the measurement band. An

alternative scheme based on the distributed series impedance equation (II.22)
II-27
is also excluded not only because of the skin-eect, but also due to the dielectric
transitions of the substrate, see appendix A.
II.6.2 Load measurement
According to section II.3.4, the load impedance and the reection coecient
are related by :
Z
load
= Z
r
1 +
load
1
load
(II.112)
= Z
r
z
load
(II.113)
To obtain the value of the reference impedance Z
r
, it is necessary to compare
the normalised impedance z
load
obtained from the scattering parameters, to the
absolute impedance value Z
load
measured according the appropriate primary
denition : power-current, power-voltage or voltage-current. On MMICs at
high frequencies, voltage and current are not readily measurable, so that esti-
mates of the load impedance must be obtained indirectly, by deduction from
other measurable quantities. Here, it is inferred from combined DC resistance
and scattering parameters measurements of a resistor, a short and an open.
It has been shown by Walker et al. [II.20], that the intrinsic resistance of
thin-lm planar resistors can be reasonably considered not to vary with fre-
quency from DC to 40 GHz. The parasitics involved in every practical reali-
sation of the resistors are, however, well frequency dependent. In their paper,
Walker et al. introduced an equivalent circuit model based on a parallel capac-
itance and a series inductance, which allowed them to account for the parasitic
eects. Equation (II.114) shows the generic model proposed here, which gen-
eralises the one from Walker et al., in the sense that no assumptions are made
on the behaviour of the parasitics, so that both substrate and conductor losses
can be included.
Z
load
(R
i
) =
R
i
+ Z
e
1 + Y
e
(R
i
+ Z
e
)
(II.114)
The parallel and series extrinsic parasitics, Y
e
and Z
e
, are estimated by
characterising the open and the short derived from the resistor structure by,
respectively, removing the thin-lm conductive strip or replacing it with a good
conductor. Letting R
i
tend accordingly to innity or zero yields :
Z
load
() =
1
Y
e
Z
o
(II.115)
Z
load
(0) =
Z
e
1 + Y
e
Z
e
Z
(II.116)
The absolute value for the intrinsic resistance R
i
of the resistor is postulated
to be equal to the intrinsic resistance value obtained from DC measurements
of the three devices :
R
i
=
R
(DC)
R
o(DC)
R
(DC)
R
o(DC)
R
(DC)
R
o(DC)
R
(DC)
R
o(DC)
(II.117)
II-28
where index indicates the resistor, index o the open and index the
short. On the other hand, at high frequency, the normalised value of the intrin-
sic resistance, r
i
, can be deduced from the scattering parameters measurements
of the devices, using :
r
i
=
z
z
o
z
o
z
z
o
z
o
z
(II.118)
Finally, the reference impedance is determined by relating equations (II.117)
and (II.118) using equation (II.113) :
Z
r
=
R
i
r
i
(II.119)
Validation
This procedure has been tested on a variety of substrates and compared to
theoretical predictions and to other measurement-based methods. Figures II.3
shows results obtained on a low-loss alumina substrate after calibrating the
VNA system with the TRL algorithm. The impedance values resulting from
the new method, Z
c[new]
, deviate over the whole band less than 2.0 % both from
the values measured according to the method of Marks and Williams, [II.21],
Z
c[Marks]
, and from numerical predictions of the characteristic impedance for
the line standard according to Heinrich, [II.22], Z
c[Heinrich]
. The good agree-
ment between Z
c[Marks]
and Z
c[Heinrich]
can be partly explained by the fact
that the distributed capacitance required as input by the method of Marks and
Williams was deduced from the calculations by Heinrich.
Figure II.4 compares results obtained on lossy silicon substrates, after a
VNA system calibration using the TRL procedure with standards fabricated
on the silicon wafer. Measurement results using the new method, Z
c[new]
,
agree very well with theoretical predictions of the characteristic impedance by
Huynen, [II.23], Z
c[Huynen]
.
Discussion
The method described above determines primarily a reference impedance. It
could be applied equally well to determine the reference impedance of a SOLT,
a TRL or a TRM calibration. The examples shown above concern however
only TRL calibrations which impose the characteristic impedance as reference
impedance.
As explained in section II.2.4, the magnitude of the characteristic impedance
Z
c
is arbitrary, while its phase is a unique property of the propagation mode.
The present load measurement method sets the magnitude of Z
c
by forcing DC
and high-frequency measurements of the intrinsic resistance of a thin lm resis-
tor to coincide. The interesting feature is that at least some level of coherence
between the DC and microwave measurements is ensured, provided that the
current density in the resistive strip has the same distribution at DC and RF.
This will be the case if the strip is suciently resistive and has small transverse
II-29
0 10 20 30 40
5
4
3
2
1
0
Im(Z
r
)
_
GHz
Z
r[Heinrich]
Z
r[Marks]
Z
r[new]
50
51
52
53
54
55
0 10 20 30 40
_
_
GHz
Re(Z
r
)
Z
r[Heinrich]
Z
r[Marks]
Z
r[new]
Figure II.3: Comparing various reference impedance determination methods in
the case of a CPW on low-loss alumina.
II-30
GHz
Re(Z
r
)
0
10
20
30
40
50
60
0 5 10 15 20 0 5 10 15 20
10
15
20
0
5
Im(Z
r
)
GHz
Figure II.4: Comparing Z

c[new]
(dotted lines) and Z
c[Huynen]
(solid lines), the
measured and the predicted characteristic impedance, respectively. The CPW
was fabricated on a SOI substrate having a resistivity of 20 cm. .
dimensions so that skin-eect and lateral current-crowding are minimised. The
longitudinal dimension must also be small in order to avoid distributed eects
inside the resistor.
Finally, one may wonder to which current or voltage normalisation scheme
the extracted characteristic impedance corresponds best. Initial hints have
been given in section II.2.5. It is not possible to say much more as the voltage
and the current normalisation scheme proposed there do not result in important
variations of the theoretically predicted Z
c
. The result of gure II.4 are based
on the voltage normalisation scheme.
II.6.3 Calibration comparison
Williams and Marks, [II.24], proposed the concept of calibration comparison.
The idea is to apply two calibrations consecutively so that information can be
extracted from the error matrix relating the two. The normalised measurement
equation (II.71) after the rst calibrations yields :
M
A(1)
M
B(1)
= T
A(01)
T
DuT(1)
T
B
1
(01)
(II.120)
The second set of calibration standards is then measured, and the second cali-
bration is applied, transforming the measurement equation into :
M
A(2)
M
B(2)
= T
A(01)
T
A(12)
T
DuT(2)
T
B
1
(12)
T
B
1
(12)
(II.121)
The matrices T
A(12)
and T
B
1
(12)
describe the dierences between calibra-
tions 1 and 2. These dierences are due to the use of dierent calibration stan-
dards which may impose dierent reference impedances and reference planes.
II-31
Each set of standards may be implemented dierently, on separate wafers. A
general model for the matrices T
X(12)
is the following :
T
X(12)
= T
L
1
1
T
Y
o
. .
Z
r1
Q
12
T
L
2
..
Z
r2
(II.122)
The matrix T
L
2
accounts for the length of transmission line separating the
probe from the reference planes of the second calibration. The matrix is referred
to Z
r2
. Q
12
is the impedance transformation from reference impedance Z
r2
to
Z
r1
, the reference impedance of the rst calibration. T
Y
o
account for the shunt
load seen at the probe-tips when transferring the probes with calibration 1 onto
the substrate of calibration 2. This shunt load is typically due to dierences in
substrate material and in CPW geometry. T
L
1
1
is the transfer matrix allowing
to rewind the reference plane of calibration 1 back to the probe tips. T
L
1
1
and
T
Y
o
are referred to Z
r1
.
T
Y
o
=
_
1 Z
r1
Y
o
1
2
Z
r1
Y
o
1
2
Z
r1
Y
o
1 + Z
r1
Y
o
_
(II.123)
The expression for T
Y
o
shows that the inuence of this matrix on T
X(12)
may
be neglected provided that Z
r1
Y
o
1, as T
Y
o
then tends towards the unity
matrix, I. This occurs when the calibration standards of both sets are su-
ciently similar. This will be assumed to be true, for the sake of developments
below.
Setting T
Y
o
= I in equation (II.122) and developping the expressions for
the transmission line matrices yields :
T
X(12)
= Q
1c
1
_
e
+ L
1
0
0 e
L
1
_
Q
c
1
1
Q
12
Q
2c
2
_
e
L
2
0
0 e
+ L
2
_
Q
c
2
2
(II.124)
where the additional impedance transform matrices allow to switch from the
reference impedance Z
r
to the characteristic impedance Z
c
for each line sec-
tion. Exploiting the commutativity of the product of symmetric matrices and
the specic properties of the impedance transform allows to simplify equa-
tion (II.124) into :
T
X(12)
= Q
12
_
e
(L
2
L
1
)
0
0 e
+ (L
2
L
1
)
_
(II.125)
Williams and Marks, [II.24], used equation (II.125) to extract estimates of
12
allowing to relate both reference impedances according to the theory devel-
opped in section II.3.8. Their result is however based on simplied expressions
assuming that the reference impedances are real. This assumption is too re-
strictive for the needs of the present work, and a new expression was derived
from equations (II.62) and (II.125) allowing to determine
12
in the case of
II-32
Im(Z
r
)
_
_
GHz
0 10 20 30 40
20
10
0
10
20
_
_
GHz
Re(Z
r
)
20
30
40
50
60
0 10 20 30 40
Figure II.5: Comparing the load measurement method (rings) and the cali-
bration comparison method (crosses), applied without correcting for the shunt
stub admittance.
II-33
complex reference impedances :
12
=
_
T
X(12)12
T
X(12)21
T
X(12)11
T
X(12)22
=
_
t
X(12)12
t
X(12)21
t
X(12)11
(II.126)
where :
12

Z
r2
Z
r1
Z
r2
+ Z
r1
(II.127)
Equation (II.126) allows to determine Z
r1
if Z
r2
is known or vice-versa,
provided that the sign ambiguity can be lifted. The ambiguity can not be
easily resolved, unless one has some estimate of what the phase of
12
should
be. For example by building estimates of the unknown impedance Z
r
.
Discussion
This method has been compared to the load measurement method in the case
of a 20 cm SOI substrate. The results presented in gure II.5, show that both
methods agree well at low frequencies, while they diverge continuously when
the frequency is increased. This divergence can be explained by the fact that
the reference calibration used structures implemented on an alumina substrate,
while the target calibration relied on the SOI structures shown in gure II.2,
which have a dierent layout. As a consequence, the assumption of similar
calibration structures does not apply, and T
Y
o
,= I induces an error on the
estimation of
12
in (II.125).
Correct results will be obtained if Y
o
can be somehow estimated and cor-
rected for in equation (II.122). This may be performed by measuring an adhoc
structure for example, the head to head connection of two identical open
stubs, yielding Y = 2 Y
o
when measured with a probe-tip calibration. The
need for this additional calibration structure is perceived as a disadvantage of
the calibration comparison method. The application of the calibration compar-
ison method is also somewhat complicated by the fact that when Z
r1
and Z
r2
are close to each other,
12
may experience many zero crossings requiring to
be careful about the sign to choose in equation (II.126). These considerations
explain that the calibration comparison method was used only when resistor
structures were not available or unusable for the determination of the reference
impedance according to subsection II.6.2.
II.7 De-embedding strategies
The organisation of the de-embedding process for on-wafer measurements will
be discussed here. It rarely consists in a single calibration mainly because
of the metrology constraint of traceability. To make valid comparisons with
measurements made elsewhere one is required to be able to relate his own
measurements to some master standard. In the case of on-wafer scattering
parameters measurements this can be done by using commercially available
calibration kits which should be delivered with adequate correction factors
determined with respect to a master calibration at present, suppliers of
calibration kits all refer to the National Institute of Standards and Technology
II-34
II.7 De-embedding strategies
of the United States of America. These commercial calibration kits are usually
fabricated on an alumina substrate with a thick gold metallisation.
To measure its own devices, a user must transfer the probes after calibration
on the standards substrate onto the wafer of interest. This wafer is generally
not alumina, but rather silicon or another semiconductor. The dimensions of
the probe pads and of the waveguides are most probably also dierent. It is
thus necessary to perform additional corrections to obtain the characteristics
of the DuT corresponding to its intended use in a future circuit. The most
widespread approach is the immittance correction method described below.
This method suers several serious drawbacks, which have been avoided in this
work by introducing an alternative approach : in-situ calibration.
II.7.1 Immittance corrections
This method was rst proposed by van Wijnen for bipolar devices, [II.25]. It
was later enhanced by Fraser, [II.26], and by Cho, [II.27]. The method is based
on the adoption of the equivalent circuit depicted in gure II.6 to describe
the probing structure into which the DuT is embedded. Cho showed that all
six elements of the equivalent circuit can be determined from the measured
characteristics of three devices :
1. An open circuit, obtained by removing the DuT and leaving the lines
corresponding to access nodes 1 and 2 open.
2. A short circuit, obtained by replacing the DuT by metal lines connecting
all three access nodes together.
3. A through connection, obtained by replacing the DuT by a metal line
connecting nodes 1 and 2 together, while node 3 is left dangling.
DuT
1 2
3
Port A Port B
Z
a1
Z
a2
Z
a3
Y
a1
Y
a2
Y
a3
Figure II.6: Equivalent circuit model for the immittance correction method.
The method is unable to determine the true characteristics of the three
devices used, so that ideal characteristics are assumed : There is no fringing
capacitance for the open ends, the metal lines of the short and through have
II-35
neither inductance nor resistance. These assumptions limit the applicability
of the method to small device geometries where the parasitics of the short
and the through are negligible. These assumptions also result in a general
overestimation of the corrections to apply which, in the case of transistors,
may result in articially high apparent values for several characteristics, such
as the current gain, as discovered by Kim, [II.28].
Finally, the model topology uses only two complex parameters to charac-
terise the transition from the probe-tips to the device itself. The two remaining
parameters, Y
a3
and Z
a3
, account only for some parasitic coupling between in-
put and output. The theory of the electro-magnetic reciprocity, [II.16], shows
that three complex parameters are generally required to model the passive two-
port transition corresponding to a single set of probe-pads, accommodating one
probe. The model of gure II.6 is thus an oversimplication which may not
account properly for the characteristics of the probe-pads at high-frequencies.
II.7.2 In-situ calibration
To avoid the limitations imposed by restricted equivalent circuit topologies,
a very general model is used, in agreement with the developments of subsec-
tion II.6.3. This model, shown in gure II.7, is compatible with the rigorous
calibration methods described in section II.5, so that any of these algorithms
may be used to determine T
A(12)
and T
B(12)
, where index 1 refers to the
alumina calibration and index 2 to the in-situ calibration on SOI.
DuT
1 2
3
Port A Port B
T
A(12)
T
B(12)
Figure II.7: Equivalent circuit model for the in-situ TRL calibration.
According to the discussion at the end of subsection II.5.3, the TRL method
is preferred and used in conjunction with a reference impedance determination
method. Both procedures use as sole calibration structures those shown in
gure II.2, which are all implemented in the immediate vicinity of the DuTs,
hence the name in-situ. Aside from the comprehensive model for the transitions
at port A and B, the in-situ TRL calibration has the advantage to be able to
locate the reference planes at precise positions along the CPWs feeding the
test devices. This allows to minimise the input and output adjacent parasitics,
while allowing to avoid the pitfall of overestimated corrections : The reference
planes can always be located at some distance from the device themselves, so
that probe placement errors do not result in an incursion of the reference plane
II-36
II.8 Conclusion
inside the device region.
II.8 Conclusion
This chapter presented the rigorous framework which is the foundation of the
scattering parameters measurements performed in this work. The main feature
in the theory of Marks and Williams, [II.1], which proved essential for the
development of the present work, is the ability to deal very generally with
lossy waveguides. This allowed to consider the application of S-parameters
calibration techniques to the de-embedding of coplanar waveguide structures
fabricated with standard metallisation processes on any type of silicon material,
either high- or low-resistivity.
In-situ calibration was introduced as an ecient and reliable de-embedding
strategy, remedying to the limitations of the widely used immittance correction
method. The error-model associated with S-parameters calibration techniques
such as the SOLT, the TRM or the TRL, is indeed more general, providing an
increased exibility in the design of the probing structure. Furthermore, the
TRL calibration algorithm has the ability to locate the reference planes of the
measurements precisely at an arbitrary position along the feeding waveguide,
minimising the risk of overestimated corrections which is the major drawback
of the immittance correction approach.
Two original solutions were presented for the determination of the reference
impedance of S-parameters calibrations on lossy substrates : the load measure-
ment method and the calibration comparison method. Accurate determination
of the reference impedance is indeed mandatory if one wants to exploit the
results of a TRL calibration, as this calibration sets the reference impedance
equal to the characteristic impedance of the CPW, which is generally unknown
a priori.
The load measurement method proceeds by comparison of the DC and RF
characteristics of a resistor, while the calibration comparison method extracts
information about the impedance transform from the T-matrices relating two
successive calibrations. The load measurement method was found to be more
exible, allowing more freedom in the design of the probing structure. Both
methods were extensively tested and validated by a long series of measurements
at the microwave laboratory of the UCL.
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[II.21] R. B. Marks, A multiline method of network analyser calibration,
IEEE Trans. on Microwave Theory and Techniques, vol. 39, pp. 1205
1215, July 1991.
[II.22] W. Heinrich, Full-wave analysis of conductor losses on mmic transmis-
sion lines, IEEE Trans. on Microwave Theory and Techniques, vol. 38,
Oct. 1990.
[II.23] I. Huynen and B. Stockbroeckx, Variational principles compete with
numerical iterative methods for analyzing distributed electromagnetic
structures, in Proceedings of the NUMELEC97 Conference, (Lyon,
France), pp. 1921, Mar. 1997.
[II.24] D. F. Williams, R. B. Marks, and A. Davidson, Comparison of on-
wafer calibrations, in 38th ARFTG Conference Digest, pp. 6881, Dec.
1991.
[II.25] P. J. van Wijnen, H. R. Claessen, and E. A. Wolsheimer, A new
straightforward calibration and correction procedure for on-wafer high
frequency S-parameters measurements (45 MHz - 18 GHz), in IEEE
1987 Bipolar Circuits and Technology Meeting, 1987.
[II.26] A. Fraser, R. Gleason, and E. W. Strid, GHz on-silicon-wafer probing
calibration methods, in IEEE 1988 Bipolar Circuits and Technology
Meeting, 1988.
[II.27] H. Cho and D. Burk, A three-step method for the de-embedding of
high-frequency s-parameters measurements, IEEE Trans. on Electron
Devices, vol. 38, pp. 13711375, June 1991.
[II.28] C.-H. Kim, C. S. Kim, H. K. Yu, and K. S. Nam, An isolated-open pat-
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Letters, vol. 8, pp. 9698, Feb. 1998.
II-39
Chapter III
Modelling fully depleted
SOI MOSFETs
III.1 Introduction
This chapter describes the development of a model for the SOI MOSFET, ded-
icated to the simulation and design of analogue microwave circuits. To attain
the level of computational eciency required in circuit simulators, simplifying
assumptions are needed which allow to formulate the model as a set of explicit
analytical expressions. As many other successful MOSFET models, the model
detailed below relies on the charge-sheet and gradual channel approximations
for the development of its fundamental expressions. These assumptions are,
strictly speaking, only applicable to long-channel devices operating in the linear
regime. Microwave MOSFETs, on the other hand, are typically short chan-
nel devices operated in saturation in order to obtain the desired high-frequency
performances. Several model enhancements will be proposed allowing to extend
the applicability of the basic charge-sheet model to short-channel devices : A
modication of the threshold voltage accounting for the Drain Induced Barrier
Lowering eect and a semi-analytical model of the saturation region accounting
for the channel length modulation eect.
Various important microwave circuits such as mixers and oscillators, operate
in large signal conditions, with transistors being driven across several operating
regimes. To deal with such cases, the model relies on innitely derivable inter-
polation functions to ensure smooth transitions of the characteristics between
several operating regimes. Two such interpolation functions are introduced :
one for the inversion charge density, allowing to predict both the weak and
strong inversion characteristics with a single mathematical expression, and a
III-1
Modelling fully depleted SOI MOSFETs
second interpolation function controlling the transition between the linear and
the saturated operating regimes.
The most original contributions contained in this chapter concern the dy-
namic aspects of the transistor behaviour at microwave frequencies. An al-
ternative formulation of the charge model is proposed which better accounts
for the distribution of dynamic currents inside the SOI MOSFET than the
conventional model which was initially intended for bulk devices. This alterna-
tive charge model is then generalised into a multi-section channel model which
allows to simulate charging delays occurring in the channel at microwave fre-
quencies. The dispersive behaviour of the interface traps, which react only
to low-frequency stimuli, is correctly rendered thanks to the introduction of
dedicated state-variables representing the charging level of the traps. Finally,
an elaborate substrate coupling model is presented, which reproduces the be-
haviour of the SOI structure in a very wide band around its dielectric relaxation
frequencies.
This chapter covers the elaboration of the MOSFET model in detail, start-
ing from the fundamental equations, pointing at underlying assumptions and
working towards the evaluation of the macroscopic quantities used to represent
the device in circuit simulators : terminal currents and charges. This com-
prehensive approach facilitates the assessment of basic model limitations and
gives direct insight in the relationship between macroscopic model concepts
threshold voltage, inversion charge, ... and microscopic concepts such as
those used in device simulators carrier densities, electric eld distributions,
etc. Comparison of model predictions with measurements will be avoided here,
as chapter IV is entirely devoted to parameter extraction and model validation.
The present chapter is thus organised as follows :
After a brief description of the device structure and its operation modes,
the present section discusses the modelling needs which are translated
into specic modelling objectives.
Section III.2 presents the development of a charge-sheet model with a
special attention devoted to bidimensional eects and the dispersive be-
haviour of the interface states.
Section III.3 introduces the transport equations to obtain an expression
of the static conduction current.
Section III.4 deals with the quasi-static evaluation of dynamic currents
and proposes a new topology of the charge model which is better suited
for the SOI MOSFET.
Section III.5 presents several original schemes allowing to extend the ap-
plicability of the quasi-static current and charge expressions to higher
frequencies where non-quasi-static eects become important.
Section III.6 completes the modelling task by presenting a global equiva-
lent circuit accounting for both the useful and the parasitic eects which
inuence the device response at microwave frequencies.
III-2
III.1 Introduction
Section III.7 reviews the limitations of the model in terms of layout di-
mensions, biasing conditions and frequency range.
III.1.1 The SOI MOSFET structure
Figure III.1 depicts the cross-section of a typical SOI MOSFET device. As ex-
plained in the introductory chapter, the MOS transistor is fabricated in a thin
crystalline lm on top of an oxide layer which isolates it from the wafer sub-
strate. Metal interconnections with contact to the source and drain diusions
are also shown.
Polysilicon (Gate)
Silicide (Source)
p silicon (Film)
Silicide (Gate)
Diusion (Source)
p
silicon (Substrate)
Passivation oxide
Metal (Drain)
Field oxide
Gate oxide
Buried oxide
Figure III.1: The SOI MOSFET structure
The device presented here is an enhancement n-channel MOSFET. Due to
the higher mobility of electrons, n-channel transistors have better performance
at high-frequencies, and these devices will most probably constitute the core of
circuits designed for microwave operation. For this reason, the present chapter
concentrates exclusively on n-channel enhancement MOSFETs. The comple-
mentary transistor in the SOI CMOS technology of the micro-electronics labo-
ratory of the UCL is an accumulation p-channel device. Far less has been pub-
lished about the modelling of accumulation devices as for enhancement devices.
However, a static current and charge model of the accumulation transistor is
under development at the micro-electronics laboratory and all renements pre-
sented in the present chapter for high-frequency, short-channel n-MOSFETs
could be transposed to it.
III.1.2 Operating modes of the generic SOI MOSFET
structure
The operating modes of the generic SOI structure have been extensively studied
by Flandre in [III.1]. The four most important ones for enhancement MOS-
FETs are illustrated here for convenience. The gure shows the prole of the
electric potential across the lm, with respect to the Fermi potential,
F
. The
rst mode is characteristic of thick lm SOI devices which are partially depleted
III-3
V
Gf
sf
sb
V
Gb
F

F

F

F
1. 2. 3. 4.
Gate
Oxide
Si lm
Oxide
Substrate
Figure III.2: Operating modes of the SOI MOSFET. Horizontally, the poten-
tial. Vertically, the position in the SOI structure.
in normal operation. The three other modes are more specic to fully depleted,
thin-lm devices in normal operating conditions.
1. A quasi-neutral exists at the centre of the lm, which decouples the front
and back depletion regions. The front and back interface are inverted.
The structure behaves as two back-to-back bulk-MOS devices.
2. A coupling exists between the front and back depletion regions and both
interfaces are inverted.
3. The front surface is inverted, the depletion regions spans across the whole
lm and the back surface is depleted.
4. The front surface is inverted, the back surface is accumulated.
A single SOI transistor can be forced into all four of regimes by applying
suitable bias voltages to the front and back gates, but the natural condition is
considered to be the one occurring at V
Gf
= 0 = V
Gb
.
III.1.3 Thin-lm SOI MOSFETs
In the case of suciently thin lms, the coupling between the front and the back
depletion regions always exists, so that only the operating modes listed above
under (24) need to be considered. The fully-depleted mode (3) is the most
favourable one. The body-factor and the sub-threshold slope are then close to
ideal and the normal electric eld at the front interface is reduced compared
to the other modes, allowing higher mobility in the inversion channel. These
features allow fully depleted SOI MOSFETs to show very good performances,
as explained by Colinge in his book, [III.2]. Accordingly, the remainder of this
work is devoted to thin-lm, fully depleted MOSdevices.
III-4
III.1 Introduction
III.1.4 Splitting the device in intrinsic and extrinsic re-
gions
In order to simplify the modelling task, the various phenomena governing the
behaviour of the MOSFET are considered separately, identifying the regions
where each dominates and neglecting eventual weak interactions between them.
Applying this divide et impera, one is lead to consider the region where the
useful eect originates : The intrinsic region which encloses the semiconduc-
tor lm, and is horizontally delimited by the source and drain diusions, and
vertically by the front and back gates. This region is modelled by currents
and charges, which can be expressed as non-linear functions of the controlling
voltages, so that the corresponding small-signal equivalent-circuit elements are
bias-dependent. The complementary eects are then termed extrinsic, as they
can generally be located around (outside) the intrinsic region. They are the
overlap capacitances, the diusion resistances, the gate resistance, etc. Most
of these eects can be modelled using linear circuit elements.
III.1.5 Requirements for a good MOSFET model for
analogue circuit design
In an interesting paper, [III.3], Tsividis and Suyama reviewed the most current
short-comings of MOSFET models, and proposed a set of guidelines applicable
to new models for analogue circuit design. According to them,
The ideal model should :
1. meet common requirements for digital work, such as reasonable I-V char-
acteristic accuracy, ..., charge conservation, etc;
2. give accurate values for all small-signal quantities such as transconduc-
tances and capacitances. In particular, all of these parameters should be
continuous with respect to any terminal voltage;
3. give good results even when the device operates non- quasi-staticly, or at
least degrade gracefully for such operation, as frequency is increased;
4. give accurate predictions for both white noise and 1/f noise, including in
the triode region;
5. meet requirements 13 above over large bias ranges, including when non-
zero back gate voltage, and encompassing the weak, moderate and strong
inversion regions;
6. do all of the above over the temperature range of interest;
7. do all of the above for any combination of channel width and length values
for a given technology;
8. require the user to specify the geometrical dimension for each device, and
one set of model parameters valid for all devices of the same type and
independent of dimensions;
III-5
9. provide a ag every time an attempt is made to use it outside of its limits
of validity;
10. have as few parameters as possible (but just enough), and those param-
eters should be linked as strongly as possible to the ones related to the
device structure and fabrication process;
11. be linked to an ecient and simple parameter extraction method requiring
as few test devices and test points as possible;
12. provide links to device simulators.
This work does not attempt to meet the above requirements in all generality,
but rather tries to focus on the aspects which are specic to SOI MOSFETs
operating in RF front-ends of portable communications equipment.
Microwave operation at low-voltage, low-power
To obtain useful gain at microwave frequencies, short-channel transistors must
be considered. Accurate modelling of short-channel eects on both the current
and the charges is thus mandatory.
Although carrier transit-times as small as a few picoseconds can be achieved
in short-channel devices driven strongly into saturation, channel propagation
delays nevertheless have a signicant inuence on the microwave performance
of the device in the majority of biasing conditions. The need for adequate non-
quasi-static extensions of the model can be further explained by an increased
visibility of the non-quasi-static eects due to the drastic reduction of the gate,
source and drain resistances by the silicidation steps.
Finally, low-voltage operation requires proper modelling of weak and mod-
erate inversion characteristics, which are more sensitive to the back-gate bias
conditions.
Nonlinear behaviour
To model the nonlinear behaviour of the device at DC and at high-frequency
coherently, it is necessary to account for the dispersive character of some phys-
ical phenomena. Indeed, such processes as self-heating or dynamic threshold
voltage variations due to interface states exhibit time-constants in excess of
100 microseconds. Such large time-constants render these processes essentially
inactive at microwave frequencies, while still allowing a response to slow (DC)
stimuli. To develop a unied model capable of accurate predictions of both
the DC and RF device characteristics, it is necessary to account properly for
the time-constants governing the dispersive processes by introducing additional
state-variables such as the temperature or the occupation level of the interface
states.
The purpose of nonlinear modelling is the prediction of mixing and inter-
modulation products in mixers, of the level of harmonics in oscillators, of the
gain-compression in ampliers, etc. For most of these applications it is neces-
sary to produce good estimates of the higher-order derivatives of the current
III-6
III.2 Charge-sheet models for the intrinsic device
and charges versus the terminal voltages. Mixing products, for example, de-
pend upon the second-order derivatives, while inter-modulation products in-
volve at least the third-order derivatives. The continuity of all current- and
charge-voltage characteristics, as well as of all their derivatives is thus a very
important requirement for the model, together with the ability to reproduce the
measured characteristics with sucient accuracy, including even their higher
order derivatives.
Parameter extraction - Noise modelling - Statistical modelling
As indicated by Tsividis and Suyama it is important to devise models based
on physical considerations and to avoid introducing purely empirical param-
eters. Having model parameters which can be related to physical properties
of the materials helps not only to reduce the number of unknowns, but also
allows to formulate bounds which are very useful when using an optimiser to
perform parameter extraction. Additionally, a physical framework favours the
development of model enhancements, such as the ability to predict noise or
to evaluate the inuence of statistical variations. Extraction procedures using
an optimiser require many evaluations of the model responses to compute the
error functions and their derivatives. It is highly desirable to have an ecient
implementation of the model in order to avoid that the extraction procedure
becomes prohibitively time- consuming. It is also very important to have a
well-behaved program, which is able to handle extreme cases nicely, in order
to avoid the waste of computation time which would result from aborting the
execution because of one single irrealistic test-point chosen by the optimiser.
III.2 Charge-sheet models for the intrinsic de-
vice
In static operation, the intrinsic SOI MOSFET structure can be considered to
be two-dimensional. The polysilicon gate strip behaves as an equipotential,
because it does not support any charging current. The diusions are laterally
equipotential too, as they are connected at regular intervals to metal lines
running parallel to the gate strip.
However, this rst level of simplication does not allow an analytical treat-
ment of sucient generality, and fails to produce the framework required to
devise ecient numerical models for circuit simulation. Solutions of the 2D
Poisson equation in restricted operating conditions have been reported, as e.g.,
for sub-threshold conduction, by Agrawal et al., in [III.4]. Even in that case
the resolution of a set of transcendental equations is required, which represents
a heavy numerical burden. To make the problem analytically tractable in the
case of the bulk MOSFET, Brews, [III.5], suggested to combine the following
two additional assumptions :
1. The gradual channel approximation, which states that the longitudinal
component of the electric eld, responsible for carrier motion in the chan-
III-7
nel region, is much smaller than the transverse component, so that the
surface potential can be evaluated using the 1D Poisson equation.
2. The charge-sheet approximation states that the thickness of the inversion
region is innitely small, and allows to simplify considerably the evalua-
tion of the inversion charge, as described by Tsividis in [III.6].
These two assumptions form the foundation of the modelling approach
which is used here. Strictly speaking, they are only applicable to long-channel
devices operating in the triode mode or being slightly saturated. Several means
of extending the validity of the expressions to short-channel devices and their
specic behaviour will be introduced. It will be shown additionally how re-
sponses to time-varying excitations can be evaluated using the (quasi-) static
model.
III.2.1 Surface potential and charge density equations
When studying SOI lms, the potential reference is conveniently chosen equal
to the level of the source-diusion. Combined with the fact that at thermal
equilibrium the source sets the Fermi-level of the lm, this choice allows to
write concise carrier densities expressions.
V
Gf
V
S
V
D
V
Gb
OX
OY
Gate width : L
Gate oxide thickn. : t
of
Film thickn. : t
b
Buried oxide thickn. : t
ob
Figure III.3: Idealised geometry of the SOI MOSFET structure, showing the
denition of the geometrical parameters.
Electric eld
In agreement with the gradual channel approximation, a single section of the
SOI MOSFET structure at some point along OX is considered. Gausslaw is
applied to the region enclosing the front gate-oxide, so that a rst equation is
III-8
obtained relating the electric eld and the potential at the front interface of
the SOI lm, S
sf
and
sf
, respectively, to the potential of the gate, V
Gf
:
C
of
(V
Gf
W
f

sf
) + Q
of
+ Q
if
(
sf
) =
Si
S
sf
(III.1)
where C
of
is the front oxide capacitance per unit area.
A similar procedure at the back of the lm yields a relationship between
the back gate potential, V
Gb
, the electric eld at the interface with the back
oxide, S
sb
, and the corresponding potential,
sb
:
C
ob
(V
Gb
W
b

sb
) + Q
ob
+ Q
ib
(
sb
) =
Si
S
sb
(III.2)
Q
of
and Q
ob
are eective charge densities located at the interfaces and
accounting for the total xed charge trapped in the oxide layers. Q
if
and Q
ib
represent the variable charge stored in surface states or in oxide traps located
in the immediate vicinity of the Si Si O
2
interfaces . The occupation level of
these interface traps is controlled by the surface potential. To account properly
for the time-constants involved in the trapping mechanisms, Q
if
and Q
ib
are
considered as additional state variables, the behaviour of which is governed by
a specic model that will be developed in a following section.
Carrier densities
In a semiconductor material at thermal equilibrium, the electrons concentration
n and the holes concentration p are governed by the following equations :
n = n
i
exp
_
E
F
E
i
kT
_
(III.3)
p = n
i
exp
_
E
i
E
F
kT
_
(III.4)
where E
F
is the Fermi level and E
i
= (E
v
+ E
c
) /2 is the intrinsic energy level,
half-way between the valence and the conduction band. In the absence of any
externally applied electric eld (at E
i
= E
i0
), the material is neutral, and the
mobile carriers must compensate for the charge density of the acceptor ions,
N
a
:
N
a
= p
0
n
0
(III.5)
When a vertical electric eld is present, the carrier concentrations change,
and are given at thermal equilibrium by the next pair of equations, where
F
= (E
i0
E
F
) is the Fermi potential in the absence of electric eld,
T
is
the thermal voltage (k T/q) and is the electric potential :
n = n
i
exp
_

F
T
_
(III.6)
p = n
i
exp
_
T
_
(III.7)
When the SOI MOSFET is turned on, the silicon lm is not in thermal
equilibrium anymore, and the above equations have to be modied. Non-
equilibrium conditions are introduced into the equations using dierent Fermi
III-9
levels for electrons and holes. For an n-channel fully-depleted SOI MOSFET,
the contribution of holes to the current is negligible with respect to that of
the electrons, so that, according to Mallikarjun and Bhat [III.7], the quasi-
Fermi level of the holes can be assumed to be constant across the lm and
equal to the Fermi-level in the absence of conduction. The quasi-Fermi level
of the electrons, on the other hand, varies along the channel (OX direction),
reecting the forces driving the electron current : diusion and drift. It is
constant perpendicularly to the channel (OY ), as there is no current ow in
that direction. Finally, equations (III.3) and (III.4) can be rewritten as :
n(x, y) = n
i
exp
_
(x, y)
Fn
(x)
T
_
(III.8)
p(x, y) = n
i
exp
_
(x, y)
Fp
(x)
T
_
(III.9)
Surface potential equations
Applying now the gradual channel approximation, a single section of the struc-
ture is considered at some point along the OX axis, where the electric eld and
the potential are related to the charge density, neglecting the contribution of
electric eld components parallel to the channel :
dS
dy
=
(y)
Si
(III.10)
S =
d
dy
(III.11)
(y) = q
_
p(y) n(y) N
a
_
(III.12)
To obtain suitable expressions relating the front and back surface potentials, the
dierential form of Gausslaw, (III.10), is transformed into expression (III.13),
where the explicit spatial dependency has been removed :
d(S
2
)
d
=
2()
Si
(III.13)
Equation (III.13) can then be integrated analytically across the silicon lm :
S
2
sf
S
2
sb
=
_

sf
sb
2()
Si
d (III.14)
The integral on the right-hand side has been computed by Mallikarjun and
Bhat in [III.7] as the dierence of the following primitive, evaluated at the
III-10
front and at the back interfaces :
G
2
(,
F
,
Fn
)
_

2()
Si
d
=
2qp
0
Si
_
exp
_
T
_
+

T
+ exp
_
2
F
T
_
_
exp
_
+
F

Fn
T
_
T
exp
_
F

Fn
T
_
_
_
(III.15)
Finally, by rearranging the terms of (III.14), a new equation is obtained which
relates quantities evaluated separately on both sides of the lm, thus revealing
the coupling existing between the surface potentials at the front and the back
interface :
S
2
sf
G
2
(
sf
,
F
,
Fn
) = S
2
sb
G
2
(
sb
,
F
,
Fn
) (III.16)
Integrating equation (III.13) from the back interface to any point in the lm,
one can see that relationship (III.16) is valid everywhere, and allows to obtain
the following useful expression for the electric eld :
S() =
_
+ G
2
(,
F
,
Fn
) (III.17)
Combining this expression of the electric eld with (III.11) to obtain dy, and
integrating across the lm, an additional equation is obtained which, together
with (III.1), (III.2), (III.16) and (III.17), can be solved numerically for the
surface potentials
sf
and
sb
:
t
b
=
_

sf
sb
d
S()
(III.18)
This solution scheme was rst used for SOI MOS structures at thermal equi-
librium by Ortiz-Conde et al. in [III.8]. It was later applied to conducting
MOSFET structures by Mallikarjun and Bhat in [III.7].
The charge-sheet and the depletion approximations
The charge-sheet assumption, christened as such by Brews in [III.5], states that
the inversion layer can be considered to be innitesimally thin. Knowing from
quantum mechanical simulations that the actual inversion layer thickness is in
the order of 1.0 nanometer, which is about one hundredth of the lm thickness
of a fully depleted device, this approximation seems quite reasonable.
Applying Gauss law over the front- and back-channel regions, equations
are obtained, which relate the sheet densities to the surface electric eld and
the eld just inside the lm, past the inversion layers. This latter electric
eld is evaluated using (III.17) by virtue of the depletion approximation (d.a.),
considering the same device, with the same applied surface potentials, but
III-11
neglecting the contribution of the mobile charge carriers in the expression of G
(III.15).
Q
nf
=
Si
_
S
sf
S
sf (d.a.)
_
(III.19)
Q
nb
=
Si
_
S
sb
S
sb(d.a.)
_
(III.20)
III.2.2 A numerical charge-sheet model
Using the numerical device model outlined on page III-10, Ortiz-Conde, [III.8],
and Mallikarjun, [III.7], have shown that the value of parameter can be closely
approximated by computing G using the depletion approximation :
G
2
(d.a.)
() =
2qp
0
Si
_

T
_
(III.21)
Substituting this value in (III.17) and solving (III.18) then yields an expression
for parameter depending explicitly on the surface potentials :
(d.a.)
=
_
sf

sb
t
b
qp
0
2
Si
_
2
2qp
0
Si
_
sb

T
_
(III.22)
This expression is very important as it allows to circumvent the numerical
evaluation of integral (III.18), and simplies considerably the resolution of the
surface potential equations. Indeed, it is now sucient to solve numerically
the two explicit equations derived from (III.16) using (III.22) together with
(III.1) and (III.2) for the surface potentials
sf
and
sb
. Developments can be
driven even further, using equations (III.21) and (III.22) in (III.17) to evaluate
S
sf (d.a.)
and S
sb(d.a.)
, and nally obtain the channel charge densities :
Q
nf
= C
of
_
V
Gf
V
fbf
+
Q
b
2C
of
+
Q
if
C
of
sf

C
b
C
of
_
sf

sb
_
_
(III.23)
Q
nb
= C
ob
_
V
Gb
V
fbb
+
Q
b
2C
ob
+
Q
ib
C
ob
sb

C
b
C
ob
_
sb

sf
_
_
(III.24)
Where V
fbf
and V
fbb
are the at-band voltages at the front and back interface
respectively, and are given by :
V
fbf
W
f

Q
of
C
of
(III.25)
V
fbb
W
b

Q
ob
C
ob
(III.26)
Q
b
is the xed body charge, while C
b
is the unit-area capacitance measured
across the body :
C
b

Si
t
b
(III.27)
Q
b
qN
a
t
b
(III.28)
III-12
This numerical procedure was originally proposed by Mallikarjun and Bhat
in [III.7]. According to the authors, it is quite general, as it allows to treat all
operating modes of SOI devices from fully depleted to partially depleted with
back-accumulation. This procedure forms the core of the charge-sheet model
developed for thin-lm fully-depleted devices by Luiz Ferreira in his doctoral
thesis, [III.9].
The originality of expressions (III.23) and (III.24) reside in their explicit
dependency upon the trapped interface charges Q
if
and Q
ib
.
III.2.3 An analytical approximate charge-sheet model
Depleted back channel
The present work focuses on thin-lm SOI MOSFETs which are known to
operate normally in the fully-depleted mode with a single inversion layer located
at the interface of the silicon lm with the front oxide. Taking that into account,
some simplications to the model developed in the previous section can be
obtained. Indeed, if the back channel is depleted, then its inversion charge will
be very small and approximately zero :
Q
nb
= 0 (III.29)
Imposing this condition and using equation (III.24), it is possible to express
the back surface potential as a function of the front surface potential and the
applied gate voltages. Substituting in (III.23) yields a simplied expression of
the inversion charge in the front channel :
Q
nf
= C
of
_
V
Gf
V
fbf
+
Q
b
2C
of
+
Q
if
C
of
sf
+
C
bob
C
of
_
V
Gb
V
fbb
+
Q
b
2C
ob
+
Q
ib
C
ob
_
_
(III.30)
f
1 +
C
bob
C
of
(III.31)
C
bob

C
b
C
ob
C
b
+ C
ob
(III.32)
Inversion charge expressions
At this point, however, the model is not explicit, as the front surface potential
must still be derived numerically from equation (III.22), taking (III.29) into
account. Iniguez proposed an interesting alternative in his paper [III.10], based
on the work by Shur et al., [III.11]. Shurs group used quantum mechanics
to evaluate the inversion charge density in bulk MOSFETs as a function of
the surface electric eld. They also proposed a formula relating the gate-
source voltage to the inversion charge density, which agrees well with their
III-13
quantum mechanical results at all bias points. Adapted to the fully depleted
SOI MOSFET by Iniguez, this formula reads :
V
Gf
V
Thf
(V
C
) =
f

T
log(
Q
nf
Q
nfTh
)
Q
nf
Q
nfTh
C
of
(III.33)
where V
Thf
is the front gate threshold voltage which depends upon the channel
potential V
C

Fn
,
f
is the body factor, and Q
nfTh
is the inversion charge
density at threshold. As such, equation (III.33) does not make the model
explicit, because it can not be solved directly for Q
nf
. Nevertheless, in weak
inversion, when the inversion charge is small, the rst term on the right hand
side dominates, and (III.33) can be approximated by :
Q
nf
= Q
nfTh
exp(
V
Gf
V
Thf
T
) (III.34)
In strong inversion, the second term on the right hand side dominates, and
(III.33) reduces to :
Q
nf
= C
of
_
V
Gf
V
Thf
_
(III.35)
To cover the whole bias range with a single expression, Iniguez proposed
in [III.10] to interpolate between weak and strong inversion using innitely
derivable functions :
Q
nf
=C
of
wkstg

log
_
1 +
Q
nfTh(wk)
C
of
wkstg
exp
_V
Gf
V
Thf (wk)
T
_
+ exp
_V
Gf
V
Thf (stg)
wkstg
_
_
(III.36)
In this formula
wkstg
is a parameter controlling the transition from weak to
strong inversion, V
Thf (wk)
and V
Thf (stg)
represent, respectively, the threshold
voltage in weak and strong inversion. It can be veried that (III.36) tends to
(III.35) in strong inversion, as the sum inside the logarithm is then dominated
by the third term, where the exponential rises more sharply because of
wkstg
. In weak inversion, on the other hand, because of its sharper slope, the third
term vanishes and the logarithm can be approximated around 1.0 by its Taylor
series expansion, the rst term of which is equal to (III.34).
q
nf
=C
of
wkstg
log
_
1 +
_
Q
nfTh(wk)
C
of
2
wkstg
exp
_V
Gf
V
Thf (wk)
T
_
+ exp
_V
Gf
V
Thf (stg)
wkstg
_
_
(III.37a)
Q
nf
=
4q
nf
2
C
of
T
+
_
_
C
of
T
_
2
+ 4q
nf
2
(III.37b)
III-14
Equations (III.37a) and (III.37b) form together an enhanced version of (III.36),
which has, according to Iniguez, more precise derivatives. Using either (III.37a)
(III.37b) or (III.36) together with (III.29) and (III.30) an explicit model is
obtained which allows to compute the surface potential,
sf
, as well as the
inversion charge density, Q
nf
, directly from the externally applied voltages.
Aside from being explicit, the model of this section has also the distinctive
advantage of covering the whole bias range from weak to strong inversion.
Nowhere else in the literature has any other model been found up till now,
which features these two major advantages.
Threshold voltages and associated inversion charge
To complete the analysis, expressions have to be found for the threshold volt-
ages, V
Thf (wk)
and V
Thf (stg)
and for the inversion charge density at threshold,
Q
nfTh(wk)
. It is commonly accepted that the transition between weak and
strong inversion occurs when the surface potential
sf
is about 2
F
above the
Fermi-level; see Tsividis, [III.6], page 88, or Lim and Fossum [III.12]. Using
sf
= V
C
+ 2
F
in equation (III.30) one obtains :
V
Thf (mod)
= V
fbf

Q
b
2C
of
if
C
of
+
f
_
V
C
+ 2
F
_
bob
C
of
_
V
Gb
V
fbb
+
Q
b
2C
ob
+
Q
ib
C
ob
_
(III.38)
In this transition region, designated as moderate inversion by Tsividis, neither
the weak inversion nor the strong inversion approximations hold. Typically,
these approximations are valid for surface potentials up to a few
T
away from
V
C
+ 2
F
, on either side. This explains why dierent values are needed for
the threshold voltages, which represent the upper limit of weak inversion for
V
Thf (wk)
, and the lower limit of strong inversion for V
Thf (stg)
.
V
Thf (wk)
= V
Thf (mod)
+
f
wk
where
T

wk
< 0 (III.39)
V
Thf (stg)
= V
Thf (mod)
+
f
stg
where
stg
2
T
(III.40)
where
wk
and
stg
are the surface potential dierences at the front interface
between moderate and weak or strong inversion respectively.
Mallikarjun and Bhat published analytical expressions of the sub-threshold
charge densities for thin-lm SOI MOSFETs in [III.13], from which Q
nfTh(wk)
can be readily obtained :
Q
nfTh(wk)
=
Q
T
C
bf
_
f
_
V
C
+ 2
F
+
wk
_
_
2
f
__
V
Gb
V
fbb
+
Q
ib
C
ob
+
Q
b
2C
ob
_
b
2C
bf
_
1
(III.41)
III-15
III.2.4 A dynamic model for the interface traps
Surface states or traps located in the vicinity of the Si Si O
2
interface may
capture electrons from the channel. The amount of charge stored in these
traps at equilibrium (when all transients have decayed) depends on the the
applied electric eld, the energy distribution of the traps and the Fermi-level of
the carriers. It is common practice in MOSFET modelling to assume a uniform
distribution of traps across the bandgap, [III.1], [III.13], [III.14], as it leads to
simple expressions of the threshold voltage and inversion charge. For a static
analysis, the simplied expressions of Q
if
and Q
ib
are :
Q
if
(
sf
) = C
if

sf
with
sf

sf
V
C

F
(III.42)
Q
ib
(
sb
) = C
ib

sb
with
sb

sb
V
C

F
(III.43)
They can be injected directly into (III.23), (III.24) to obtain adequate threshold
voltage and inversion charge expressions.
Capture of electrons by surface states is a recombination process which
involves the emission of phonons. Capture of electrons by oxide traps involves
tunnelling through the potential barrier of the oxide, either directly from the
conduction band to a trap at the corresponding energy level, or indirectly after
capture by a surface-state. According to Tewksbury, [III.14], the time-constants
involved in these trapping mechanism range from a fraction of a nanosecond,
in the case of fast surface-states, down to a few milliseconds, even seconds, for
oxide traps.
Tewksbury explains in his paper, [III.14], that, even in modern technologies
with high-quality oxide material and interfaces, traps may signicantly degrade
the performance of analogue circuits. They can induce transient threshold
voltage shifts of several millivolts which take a few milliseconds to decay. This is
particularly the case in switched-capacitor networks, or A/D converters. Traps
have also been found responsible for the dispersive behaviour of the output
conductance in MOSFETs. In the case of short-channel MOSFETs, accurate
prediction of the output conductance is necessary, which, in turn, calls for the
ability to predict the level of trapped charge. As microwave circuits (e.g. :
mixers, oscillators) may involve both slowly and rapidly varying signals, the
dynamic behaviour of the traps must by properly accounted for.
d
if
dt
+

if

sf
if
= 0 with
if
Q
if
/C
if
(III.44)
d
ib
dt
+

ib

sb
ib
= 0 with
ib
Q
ib
/C
ib
(III.45)
Equations (III.44)(III.45) constitute a rst order model for the dynamic be-
haviour of the interface traps. It is similar to the RC model introduced by
Tewksbury in SPICE. It could be rened by introducing a more complicated
dependency of Q
if
and Q
ib
on
if
and
ib
and also by splitting up the interface
charges in several components responding with dierent time-constants.
III-16
V
Gf
V
S
V
D
V
Gb
(0, 0)
(L, t
b
)
= Q
nb
(x)
= Q
nf
(x)
(0, HFilm)
(L, 0)
= q N
a
Figure III.4: Boundary conditions for the 2D Poisson equation.
III.2.5 Short channel eects
All the previous developments are based on the gradual channel approximation
which considers that the longitudinal component of the electric eld S
x

x
is negligible with respect to the transverse component S
y

y
, so that
the 2D Poisson equation reduces to a one-dimensional dierential equation as
indicated below :
2
(x, y) =
(x, y)
Si
=
q N
a
Si
(III.46a)
2
(x, y)

2
(x, y)
y
2
(III.46b)
The boundary conditions for the potential at the diusions are :
(0, y) =
Jn
and (L, y) = V
DS
+
Jn
(III.46c)
where
Jn
is the built-in potential of the junctions at source and drain. At the
interfaces with the front and back oxides the conditions are :
(x, 0)
=
1
Si
_
Q
nf
+ Q
if
+ C
of
_
V
Gf
V
fbf
(x, 0)
_
_
(III.46d)
(x, t
b
)
=
1
Si
_
Q
nb
+ Q
ib
+ C
ob
_
V
Gb
V
fbb
(x, t
b
)
_
_
(III.46e)
The gradual channel approximation is no longer valid when short-channel
devices are considered. Several eects limit the applicability of gradual channel
approximation in this case. Veeraraghavan and Fossum, [III.15], analysed them
and proposed modelling solutions for the SOI MOSFET. They identied the
following eects : channel-length modulation, charge-sharing and drain-induced
conductivity enhancement.
III-17
Channel-length modulation
This eect results from the velocity-saturation of carriers at high eld and
induces a complex two-dimensional electric eld distribution in the vicinity of
the drain. It will be treated in more detail later as it is more closely related to
carrier transport.
Charge-sharing
It is due to the fringing eld emanating from the source and drain diusions
towards the back gate, which reduce the fraction of depletion-charge controlled
by the front gate. Charge-sharing is introduced in the charge-sheet model by
replacing the lm charge density Q
b
by an eective value which is a function of
V
D
and V
S
. Colinge, [III.2], showed that the voltage-shift due to charge-sharing
remains small as long as the channel-length is kept above 0.5 micrometer for
a lm-thickness on the order of 100 nanometer. Additionally, the threshold
voltage shift can be controlled by reducing the lm-thickness when scaling
down to deep sub-micrometer devices. As a result, this issue will not be dealt
with in more detail here.
Drain-induced conductivity enhancement
The presence of a non-zero longitudinal electric eld modies the potential
distribution and hence the concentration of carriers as can be anticipated from
equation (III.6). Veeraraghavan and Fossum, [III.15] proposed to express the
potential in the active zone as the sum of
0
, the solution at V
DS
= 0, with
, a correction for V
DS
,= 0 :
(x, y) =
0
(x, y) + (x, y) (III.47)
Substituting expression (III.47) in the 2D Poisson equation yields a dierential
equation describing the distribution of the incremental potential :
2
_
(x, y)
= 0 (III.48a)
(x,0)
=
1
Si
_
Q
nf
+ Q
if
C
of

_
(III.48b)
(x,t
b
)
=
1
Si
_
Q
nb
+ Q
ib
C
ob
_
(III.48c)
(0, y) = 0 (III.48d)
(L, y) = V
DS
(III.48e)
The boundary conditions (III.48b) and (III.48c) are obtained considering that
the electric eld in the oxide is mainly vertical. This assumption is quite
reasonable for the front-gate oxide which is rather thin and supports a rather
high transverse eld, particularly in inversion. For the back-gate oxide, the
assumption is rather approximate, but results in an acceptable mean value for
the transverse eld S
sb
. Conditions (III.48d) and (III.48e) simply state that
the diusions are equipotentials.
III-18
Considering that the longitudinal electric eld at V
DS
= 0 is very almost
zero everywhere in the active region, one may correctly approximate the po-
tential distribution
0
by
(1D)
, the solution obtained by the one-dimensional
approach developed on page III-10.
To obtain closed-from expressions relating the incremental surface poten-
tials,
sf
and
sb
, to the incremental inversion charges, Q
nf
and Q
nb
in a manner similar to (III.23) and (III.24), Veeraraghavan and Fossum in-
troduced the additional assumption that the partial derivatives of are not
strongly coupled :
x
2
=
y
2
(III.49)
Computer simulations showed that can be considered constant across the
active region and approaches zero as the channel-length increases. Integrating
(III.49) along the OX axis, the dependence of is inferred :
=
2
L
2
_
V
DS
+ S
x
(0, y) L
_
2V
DS
L
2
(III.50)
since the incremental longitudinal eld S
x
at the source is typically much less
than the average eld V
DS
/L. Next, by integrating (III.49) twice along the
OY direction one obtains equations relating the values of and

y
at the
front and the back interface together. Combined with the boundary conditions
(III.48b) and (III.48c), these allow nally to write the incremental counter-part
of equations (III.23) and (III.24) :
Q
nf
(x) = C
of
_
Q
if
(x)
C
of
sf
(x)
b
C
of
_
sf
(x)
sb
(x) +
t
2
b
L
2
V
DS
_
_
(III.51)
Q
nb
(x) = C
ob
_
Q
ib
(x)
C
ob

sb
(x)
b
C
ob
_
sb
(x)
sf
(x) +
t
2
b
L
2
V
DS
_
_
(III.52)
Combining equations (III.51) and (III.52) with (III.23) and (III.24) written
in terms of
0
, expressions are obtained which relate the inversion charges Q
nf
and Q
nb
to the surface potentials
sf
and
sb
in the two-dimensional case :
Q
nf
= C
of
_
V
Gf
V
fbf
+
Q
b
2C
of
+
Q
if
C
of
sf
b
C
of
_
sf

sb
+
t
2
b
L
2
V
DS
_
_
(III.53)
Q
nb
= C
ob
_
V
Gb
V
fbb
+
Q
b
2C
ob
+
Q
ib
C
ob
sb
b
C
ob
_
sb

sf
+
t
2
b
L
2
V
DS
_
_
(III.54)
III-19
Applying the condition for a depleted back-channel (III.29), a new expression is
obtained for V
Thf (mod)
which now accounts for the drain-induced conductivity
enhancement eect :
V
Thf (mod)
= V
Thf (mod)
V
DS
=0
_
1 +
C
b
C
b
+ C
ob
_
C
b
t
2
b
C
of
L
2
V
DS
(III.55)
where V
Thf (mod)
V
DS
=0
stands for the value given by equation (III.38), which
does not account for two-dimensional eects.
III.3 Static conduction current
In this section the conduction current in the linear regime is evaluated based
on the gradual-channel approximation using the inversion charge equations de-
veloped in section III.2. For the current in saturation, a specic model is
developed to obtain the surface potential prole in the saturation region, and
evaluate the channel-modulation eect.
III.3.1 Carrier velocity
A realistic carrier transport model for short-channel MOS devices needs to
account for the following phenomena :
1. The saturation of velocity at high longitudinal eld, caused by collisions
with other carriers and atoms in the crystal;
2. The reduction of mobility with increasing normal eld, as the carriers
are pressed harder onto the oxide interface and experience a more surface
roughness scattering.
Results of rigorous analyses of carrier transport in nMOSFETs have been
published, but it has not been possible yet to obtain analytical expressions of
the current using them, as indicated by, amongst others, Sodini et al., [III.16].
Therefore, simplied or empirical expressions are used, such as :
v
n
=
(x)
(x)
1 +

e
(x)
v
n(sat)
(III.56)
which relates the longitudinal electric eld S
to the carrier velocity and is,

strictly speaking, valid only for pMOSFETs with = 1. Expression (III.56)
was used for nMOSFETs by Veeraraghavan and Fossum in [III.15], with = 2.
One can see that when > 1, (III.56) reaches v
n(sat)
, when the longitudinal
eld is equal to the nite value S
sat
:
S
sat
v
n(sat)
e
_
1
_ (III.57)
III-20
In this case, a piece-wise model may be used which strictly limits the carrier
velocity to v
n(sat)
:
v
n
=
_
_
_
(x)
_
1 +

e
(x)
v
n(sat)
_
1
for
<
S
sat
v
n(sat)
otherwise
(III.58)
The longitudinal eld can be estimated in the framework of the charge-sheet
model using :
S
(x) =
sf
x
=
1
f
C
of
_
dQ
nf
dx
+
dQ
if
dx
+
C
bob
C
ob
dQ
ib
dx
_
(III.59)
The reduction of mobility due to surface roughness scattering is evaluated
by means of an eective electric eld, S
e
, which reects the normal eld
experienced on the average by all carriers in the channel.
e
=

0
1 +
S
e
=

0
1 +

2
S
eD
+S
eS
(III.60)
S
e
S
sf

Q
nf
2
Si
=
_
sf

sb
t
b
b
2
Si
_
nf
2
Si
(III.61)
where equation (III.61) computes the average electric eld inside the inversion
layer.
III.3.2 Triode operation
According to Tsividis, [III.6], the front-channel current can be split into drift
and diusion components, J
drift
and J
di
and can be related to the evolution
of the quasi-Fermi level for the electrons :
I
Cf
(x) = J
drift
(x) + J
di
(x) = W Q
nf
(x)
dV
C
dx
(III.62)
The drift current density is obtained by multiplying the drift velocity v
n
from
(III.56) with the charge density Q
nf
and the device width W :
J
drift
(x) = W v
n
= W Q
nf
(x) S
(x)
= W
Q
nf
f
C
of
_
dQ
nf
dx
+
dQ
if
dx
_
(III.63)
where, for simplicity, Q
ib
(x) is replaced by the uniform value
1
2
(Q
ibS
+ Q
ibD
)
for the evaluation of the mobility, , and of the inversion charge, Q
nf
, while the
dependency
Q
ib
x
is neglected. The expression for the diusion current density
is :
J
di
(x) = W D
n
d
dx
_ Q
nf
q
= W
T
dQ
nf
dx
(III.64)
III-21
Injecting expressions (III.63) and (III.64) into (III.62) yields an equation which
relates the current to the local inversion charge :
I
Cf
(x) = W
_
Q
nf
f
C
of
d
dx
_
Q
nf
+ Q
if
+
T
dQ
nf
dx
_
(III.65a)
=
e
_
1 +

e
v
n(sat)

f
C
of
d
dx
_
Q
nf
+ Q
if
_
1
(III.65b)
In static operation, the current is constant along the channel, so that, writ-
ing I
Cf
(x) = I
DS
, one nally obtains a dierential equation describing the
inversion-charge prole as a function of the drain-source current and the inter-
face charge :
_
Q
nf
f
C
of
+
I
DS
Wv
n(sat)
f
C
of
_
d
dx
_
Q
nf
+ Q
if
T
dQ
nf
dx
+
I
DS
W
e
= 0 (III.66)
This last result was obtained assuming that the longitudinal eld is below the
critical eld for velocity saturation S
sat
, so that the rst option of (III.58) is
valid. Consequently, (III.66) is only valid in the portion of the channel which
is in linear operation. Integrating along the channel from x = 0 to x = L
and solving for I
DS
, yields the expression of the static drain-source conduction
current as a function of the inversion charge densities at the source and drain :
I
DS
=
W
L
e
1 +

e
_
Q
nifD
Q
nifS
_
v
n(sat)
f
C
of
L
T
_
Q
nfD
Q
nfS
_
_
Q
nfS
+ Q
nfD
__
Q
nifD
Q
nifS
_
2
f
C
of
_
(III.67)
where Q
nif
is dened by :
Q
nif
(x) Q
nf
(x) + Q
if
(x) (III.68)
Equation (III.67) has been developed for static operation. As a result, one
could use (III.42) together with (III.30) to relate Q
if
directly to Q
nf
and elimi-
nate it from the expressions of the static current and the static inversion-charge
prole. However, one of the purposes of the developments in this work is to ob-
tain expressions which would be valid in dynamic operation, and in particular,
in situations where the signals are so fast that the interface charge has no time
to respond. In this case, its prole corresponds to a long-term average of the
inversion-charge prole which may be very dierent from the instantaneous pro-
le. For this reason (III.67) assumes that Q
nf
(x) and Q
if
(x) are independent
functions of position. It is noteworthy that the equation depends exclusively
on the values of the charge densities at the end-points of the channel. It is
thus not necessary to track the evolution in time of the whole interface-charge
density prole, but only to compute the state of the interface-charge density
at the source and drain using two separate lumped RC circuits.
III-22
V
Gf
_
V
I
DS
_
A
10
6
10
5
10
4
10
3
10
2
0.2
0 0.2 0.4 0.6 0.8
0.4
Frozen interface charge
Dynamic interface charge
Figure III.5: Inuence of the interface charge on the drain current at V
DS
= 0.1
V. The density of interface states N
if
is 1.67 10
11
cm
2
V
1
III.3.3 Saturation
Saturation appears at the drain of the MOSFET when the inversion charge
density in the channel becomes so small, that the carriers must be driven at
their saturation velocity to maintain the current ow. A further increase of
the drain potential extends the region where the saturation velocity is reached
towards the source, and forces the inversion layer to fan out vertically. In
these conditions, the longitudinal component of the electric eld becomes so
important that the gradual channel approximation is not accurate anymore.
Taking into account that the continuity of the steady-state current implies a
constant inversion charge in the saturation region and using an integral form of
the potential equations, it is however possible to build a useful model including
velocity saturation and channel length modulation, as shown by El-Banna and
El-Nokali in [III.17] for bulk MOSFETs, and by Veeraraghavan and Fossum
in [III.15] for SOI MOSFETs. This approach will be adapted to the framework
developed in the present work, and a peculiar attention will be devoted to the
inuence of interface states.
Saturation voltage
When saturation occurs, the channel is conveniently subdivided into two parts :
the linear region, extending from the source to the point where the chan-
nel is virtually pinched o, that is to say, where the minimal inversion
charge is reached and, hence, where the saturation velocity is attained;
the saturated region, extending from the pinch-o point to the drain.
III-23
In the linear region, the modelling approach from section III.3.2 is applicable,
and using equation (III.67) with the appropriate charge density and channel
length, a rst expression of the current is obtained :
I
DS(sat)
=
W
L
(sat)
e
1 +

e
_
Q
nifP(sat)
Q
nifS
_
v
n(sat)

f
C
of
L
T
_
Q
nfP(sat)
Q
nfS
_
_
Q
nfS
+ Q
nfP(sat)
__
Q
nifP(sat)
Q
nifS
_
2
f
C
of
_
(III.69)
where Q
nfP(sat)
and Q
nifP(sat)
stand for the charge densities evaluated at the
pinch-o point. L
(sat)
is the distance between the pinch-o point and the
source. In the saturated region, the current is simply the product of the satu-
ration velocity and the inversion charge density :
I
DS(sat)
= Q
nfP(sat)
v
n(sat)
W (III.70)
At the pinch-o point, the continuity is ensured by equating the expressions
from the linear and saturated regions, (III.69) and (III.70). Solving this set of
equations yields an expression for the inversion charge density Q
nfP(sat)
which
can be re-injected in either of the above equation to obtain the saturation
current.
Q
nfP(sat)
=
2 q
0
q
1
+
_
q
1
2
4 q
2
q
0
(III.71a)
q
2
2 (III.71b)
q
1
2Q
nfS
+
_
2
__
Q
ifP(sat)
Q
ifS
_
2
f
C
of
_
T
+
v
n(sat)
L
(sat)
e
_ (III.71c)
q
0
Q
nfS
_
2
f
C
of

T
Q
nfS
+ Q
ifP(sat)
Q
ifS
_
(III.71d)
Evaluating equation (III.33) at the source and at the pinch-o point, it is
possible to relate the saturation channel potential to the source voltage and
the charge densities. The value obtained from (III.72) can then be compared
to the applied drain voltage to decide whether the MOSFETis operating in
saturation or not.
V
P(sat)
= V
S
+
T
log(
Q
nfS
Q
nfP(sat)
)
Q
nfS
Q
nfP(sat)
f
C
of
ifS
Q
ifP(sat)
f
C
of
(III.72)
Strictly speaking, Q
ifP(sat)
is not known at this stage. Indeed, only Q
ifS
and
Q
ifD
are evaluated using the model developed in section III.2.4 and no expres-
sion of the distribution Q
if
(x, t) is available. For the sake of simplicity, Q
if
(x, t)
is assumed to be constant across the saturation region and equal to Q
ifD
.
III-24
Surface potential prole in the saturation region
In the saturation region, the inversion charge has a constant value imposed
by (III.70) combined with the continuity of the steady-state current. The
exact distribution of the inversion charge in the OY direction is governed by
the 2D Poisson equation for which no closed-form solution exist. However a
macroscopic approach based on the integral form of Gausslaw allows to derive
some useful results as demonstrated by several authors, [III.15], [III.18], [III.17].
Gausslaw applied to an innitesimally thin strip of the active lm yields :
_

Si
dS =
_
dV =
_
Q
b
+ Q
nf (sat)
_
dx (III.73)
In the same manner as in section III.2.5, the electric eld and the charges are
expanded in a component satisfying the equation at V
DS
= 0, and an increment
for V
DS
,= 0.
_

Si
S
0

dS =
_
Q
b
+ Q
nf0
_
dx for V
DS
= 0 (III.74)
_

Si
dS = Q
nf (sat)
dx for V
DS
,= 0 (III.75)
V
Gb
V
Gf
V
S V
D
L
(sat)
Pinch-o point
dx
Gaussian box
-
-
-
-
-
- -
-
- -
- - -
--
- -
- - - - -
--
Figure III.6: The boundary between the linear region and the saturation re-
gion : the pinch-o point
Only equation (III.75) is of interest here, as the solution of (III.74) cor-
responds to the one-dimensional developments of section III.2. The surface
III-25
integral on the electric eld can be expanded as follows :
_

Si
dS
=
_
t
b
0
_
S
x
(x + dx, y) S
x
(x, y)
_
dy + dx
_
S
y
(x, t
b
) S
y
(x, 0)
_
=
Si
dx
_
_
t
b
0
S
x
(x + dx) S
x
(x, y)
dx
dy + S
sb
S
sf
_
=
Si
dx
_
_
t
b
0
S
x
x
dy + S
sb
S
sf
_
=
Si
dx
_
_
t
b
0
x
2
dy + S
sb
S
sf
_
=
Si
dx
_

2
x
2
_
_
t
b
0
dy
+ S
sb
S
sf
_
(III.76)
The integral of the surface potential is approximated by the value
t
b
2
(
sf
+
sb
) and equation (III.52) with the condition Q
nb
= 0 is used to obtain a
relationship linking
sf
and
sb
, so that :
2
x
2
_
_
t
b
0
dy
t
b
2
_
1 +
C
b
C
b
+ C
ob
_
d
2
sf
dx
2
(III.77)
Assuming that the electric eld are mainly vertical in the front and back oxide
layers, the incremental surface electric eld can be expressed in function of the
surface potential increments :
S
sf
=
Q
if
C
of

sf
Si
(III.78)
S
sb
=
Q
ib
C
ob

sb
Si
=
1
Si
_
Q
ib

C
ob
C
b
+ C
ob
_
Q
ib
C
b
_
t
b
L
_
2
V
DS
+ C
b

sf
_
_
(III.79)
The constant value of the inversion charge increment in the saturation region
Q
nf (sat)
can be related to
sf
at the pinch-o using the charge-sheet model :
Q
nf (sat)
= C
of
_
Q
if
C
of
f

sfP(sat)
+
C
bob
C
of
C
b
Q
ib
+
C
b
C
of
_
t
b
L
_
2
_
C
ob
+ 2 C
b
C
ob
+ C
b
_
V
DS
_
(III.80)
Substituting the new expressions back into equation (III.75), and remembering
that Q
if
and Q
ib
were assumed constant across the saturation region, one
nally obtains a dierential equation which governs the potential prole from
III-26
the pinch-o point to the drain :
l
2
CLM
d
2
sf
dx
2

sf
+
0
= 0 (III.81a)
The boundary conditions are :
sf
(x = L
(sat)
) =
sfP(sat)
(III.81b)
d
sf
dx
x=L
(sat)
=
S
sat
(III.81c)
sf
(x = L) =
sfD
(III.81d)
The characteristic length l
CLM
and the independent term
0
are dened as :
l
CLM
t
b
_
C
b
2
f
C
of
_
1 +
C
b
C
b
+ C
ob
_
(III.82)
0

sfP(sat)

2 C
b
2
C
ob
+ C
b
_
t
b
L
_
2 V
DS
f
C
of
(III.83)
Channel-length modulation
The solution of (III.81) has the general form :
sf
=
1
sinh(
x L
(sat)
l
CLM
) +
2
cosh(
x L
(sat)
l
CLM
) +
0
(III.84)
where
0
is the independent term of the equation, while
1
and
2
are
are determined by the boundary conditions at x = L
(sat)
.
1
=
S
sat
l
CLM
(III.85a)
2
=
2 C
b
2
C
ob
+ C
b
_
t
b
L
_
2 V
DS
f
C
of
(III.85b)
The third boundary condition, which imposes the surface potential value at
the drain, allows to determine the length of the saturation region, L
(sat)

L L
(sat)
:
L
(sat)
= l
CLM
_
asinh(
sfD

sfP(sat)

2
_
(
1
)
2
(
2
)
2
)
asinh(

2
_
(
1
)
2
(
2
)
2
)
_
(III.86)
This last equation describes the channel length modulation eect. It is
mainly inuenced by the drain voltage over-drive with respect to the channel
pinch-o voltage as suggested by the argument
sfD
sfP(sat)
. Veeraragha-
van and Fossum suggested in [III.15] to use the following approximation :
sfD

sfP(sat)
V
D
V
P(sat)
(III.87)
III-27
When the channel length is not excessively short with respect to the lm thick-
ness, then
2
0 and the channel length modulation equation reduces to :
L
(sat)
= l
CLM
asinh(
V
D
V
P(sat)
1
) (III.88)
As the interface charge density was assumed to be constant across the satu-
ration region, there is no explicit inuence of the interface charge density on
equation (III.88). However, the charging level of the interface states at the
drain-end inuences V
P(sat)
and thus L
(sat)
indirectly.
Together with (III.71) and (III.72), equation (III.88) forms the channel
length modulation model. This model is not explicit, but can be resolved by
relaxation, starting with L
(sat)
= L, that is to say L
(sat)
= 0. Convergence
always occurs within less than 10 iterations.
III.3.4 Unied model
The previous section focussed on the saturated operating mode on its own.
When trying to combine the expressions developed there, with the ones re-
sulting from the analysis of the triode (linear) operating mode of the MOS-
FET some problems arise. Classically, the transistor is considered to switch
abruptly into saturation as soon as the drain voltage exceeds the saturation
voltage V
P(sat)
.
This approach has as major draw-back, that if the continuity can be ensured
for the quantities themselves, their derivatives are not generally continuous,
which as mentioned in section III.1.5, can cause simulation problems. To elude
these problems, McAndrew et al. proposed in their paper on bulk MOSFETs,
[III.19], to use innitely derivable interpolation schemes to generate smooth
transitions between the continuous chunks of the piece-wise model. Iniguez
applied this idea when developing his physical models, and particularly the
one for the SOI MOSFETs, [III.20]. According to this approach, an eective
value is introduced for the channel potential at the pinch-o point, which is
computed in such a way that it evolves to the required limits in saturation and
in linear operation :
V
P(e)
= V
P(sat)
V
P(sat)
log
_
1 + exp
_
linsat
[1 V
D
/V
P(sat)
]
_
_
log(1 + exp(
linsat
))
(III.89)
where
linsat
is a tting parameter controlling the transition from triode to
saturated operation. One can easily verify that, in all cases V
P(e )
V
P(sat)
,
and that it tends to V
P(sat)
when V
D
V
P(sat)
and to V
D
when V
D
V
P(sat)
.
The eective pinch-o potential V
P(e)
is substituted to V
P(sat)
in (III.88)
to obtain the eective value for the channel length modulation, L
(eff)
, which
determines the length of the linear region, L
(eff)
. This new length is then
injected in (III.71), so that an updated value is obtained for V
P(sat)
from equa-
tion (III.72). This iterative process converges after less than ten iterations.
It ensures a smooth transition from the triode operating regime to satura-
tion. The nal value of V
P(e)
allows to evaluate the eective inversion charge
III-28
V
Gf
V
S
V
Gb
L
(eff)
0
= 0 V
D
Q
nfS
V
P(sat)
k
V
P(e)
k
Q
nfP(sat)
k
L
(eff)
k
Q
nfP(e)
k = 0
k = k + 1
k = 0
(III.37)
(III.71)
(III.72)
(III.89)
(III.88)
(III.37)
Figure III.7: The owgraph of the unied model.
III-29
density at the pinch-o point, Q
nfP(e)
, with equation (III.37) and hence the
drain-source current.
0 0.5 1 1.5 2 2.5 3
0
5
10
15
20
25
30
35
40
3
2.5
2
1.5
1
0.5
0
-0.5
V
D
_
V
I
DS
_
mA
V
Gf
_
V
Figure III.8: Static current versus drain voltage at various gate voltages.
III.4 Dynamic currents
When the voltages applied at the terminals of the MOSFET vary, dynamic
transient current components appear. For the intrinsic MOS device, these
current are mainly related to charge rearrangement in the device, as opposed to
inductive eects. The complete dynamic current model for the SOI MOSFET
takes the form :
I
Gf
(t) =
d
dt
_
Q
Gf
_
V
Gf
(t), V
Gb
(t), V
D
(t), V
S
(t)
_
_
(III.90)
I
Gb
(t) =
d
dt
_
Q
Gb
_
V
Gf
(t), V
Gb
(t), V
D
(t), V
S
(t)
_
_
(III.91)
I
D
(t) =
d
dt
_
Q
D
_
V
Gf
(t), V
Gb
(t), V
D
(t), V
S
(t)
_
_
+ I
DS
_
V
Gf
(t), V
Gb
(t), V
D
(t), V
S
(t)
_
(III.92)
I
S
(t) =
d
dt
_
Q
S
_
V
Gf
(t), V
Gb
(t), V
D
(t), V
S
(t)
_
_
I
DS
_
V
Gf
(t), V
Gb
(t), V
D
(t), V
S
(t)
_
(III.93)
In the next subsections the charges associated with device terminals will be
computed. The surface potential distribution is rst introduced, as it is a
III-30
prerequisite for the integration of the charge densities across the device. Front
and back gate charges are then easily evaluated. The partition of the total
channel charge into source and drain components is also briey discussed. After
evaluation of the source and drain charges, an alternative formulation of the
charge model is presented.
III.4.1 Surface potential prole
The static surface potential distribution along the channel has been discussed
in section III.3.2. When dynamic signals are applied at the device terminals,
the prole described by equation (III.66) may be signicantly altered by the
presence of charging currents. A general treatment of this problem is found in
numerical device simulators which are capable of transient analyses. Reports
exist which describe the interfacing of a device simulator and a circuit simulator,
and the successful simulation of some basic circuits. The computational burden
is however quite heavy, so that for design purposes alternative simplied
solutions are still required.
When the input signals vary suciently slowly with respect to the time
needed for the rearrangement of the channel charge, one may assume that,
however varying in time, the prole corresponds at all instants to one solu-
tion of (III.66). This quasi-static assumption has proven very useful for the
development of device models of all types, which, regardless of the inherent
speed limitation of the approach, demonstrated the ability to correctly predict
responses up to high frequencies. The quasi-static assumption will be exploited
next to obtain expressions of the charges, while its limitations will be addressed
in section III.5.
In order to simplify the computation of the charge integrals, equation
(III.66) is reformulated as :
dx =
W
e
I
DS
_
_
Q
nf
f
C
of
+
I
DS
Wv
n(sat)
f
C
of
T
_
dQ
nif
+
T
dQ
if
_
(III.94)
This formulation reveals that the dierential dQ
nif
is present in all terms except
the last one, which will be considered negligible. Indeed, the contribution of
this last term might become signicant only in deep sub-threshold operation
when the inversion charge density Q
nf
and the applied longitudinal electric eld
are small. In this case the total charge stored in the intrinsic device is small,
so that an eventual bias in its evaluation will remain of marginal importance.
Neglecting the term
T
dQ
if
and replacing the I
DS
by a ctitious current
F
DS
:
dx =
W
e
F
DS
_
Q
nf
f
C
of
+
F
DS
W v
n(sat)

f
C
of
T
_
dQ
nif
(III.95)
The ctitious current F
DS
is evaluated in the same way as I
DS
in section
III-31
III.3.2, by integrating equation (III.95) along the whole channel :
F
DS
=
W
L
(eff)
e
1 +

e
v
n(sat)

f
C
of
L
(eff)
_
Q
nif
P(e)
S
nf
_
P(e)
S
f
C
of
_
_
Q
nif
P(e)
S
(III.96)
where the following short-hand notations were introduced :
_
f
b
a
f(b) f(a) (III.97)
f
_
b
a

_
f(b) + f(a)
_
/2 (III.98)
As indicated previously, F
DS
very closely approximates I
DS
above threshold,
and eventually departs from I
DS
in sub-threshold operation if at all, de-
pending on the state of the interface charge.
The advantage of the manipulation described above is that, in all subsequent
integrations, a common factor Q
nifx
Q
nifS
will appear which will cancel the
corresponding factor contained in F
DS
rendering the model numerically robust
at V
DS
= 0. This manipulation is also transparent, in the sense that in the limit,
when Q
if
uniformly tends to zero along the channel, the present model and the
standard one coincide.
Integration of expression (III.95) yields a relationship between the charge
densities and the position along the channel :
x =
W
e
F
DS
_
Q
nif
x
S
_
nf
_
x
S
f
C
of
+
I
DS
Wv
n(sat)
f
C
of
T
_
(III.99)
III.4.2 Front-gate charge
The charge density on the gate is estimated using the one-dimensional model
developed in section III.2, which is a parallel plate approximation of the gate
structure. As a result, the eect of fringing elds in the vicinity of the source
and drain diusions is not accounted for. Applying accordingly Gausslaw to a
narrow vertical strip crossing the gate polysilicon, yields :
Q
Gf
(x, z) = C
of
_
V
Gf
W
f

sf
(x)
_
(III.100)
The total gate charge is then evaluated by integration of Q
Gf
over the whole
gate area. The linear and the saturation region are treated separately, as the
expression of
sf
dier in each region.
Q
Gf
=
__
Q
Gf
dxdz
= W
_
_
L
(eff)
0
Q
Gf
dx +
_
L
L
(eff)
Q
Gf
dx
_
= Q
Gf [0, L
(e)]
+ Q
Gf [L
(e)
, L]
(III.101)
III-32
Linear region In the linear region, equation (III.30) can be used to obtain an
expression of Q
Gf
in function of the applied voltages and the inversion charge
density :
Q
Gf [0, L
(e)]
=
Q
nif [0, L
(e )]
bob
Q
ib[0, L
(e)]
f
C
ob
+ W L
(eff)
_
C
of
f
1
f
_
V
Gf
V
fbf
_
b
2
f
Q
of

C
bob
f
_
V
Gb
V
fbb
+
Q
b
2 C
ob
_
_
(III.102)
where Q
ib
corresponds to the charge stored in the back interface states, while
Q
nif
corresponds to the sum of the charge stored in the channel, Q
nf
, and the
charge trapped in the front interface states, Q
if
.
Q
nif [0, L
(e )]
W
_
L
(eff)
0
_
Q
nf
+ Q
if
_
dx (III.103)
Q
ib[0, L
(e )]
W
_
L
(eff)
0
Q
ib
dx (III.104)
Using the expression of dx from (III.94) the integral in (III.103) can be com-
puted analytically :
Q
nif [0, L
(e)]
= W
2

e
_
Q
nif
P(e)
S
F
DS
_
_
T

F
DS
W v
n(sat)

f
C
of
+
if
_
P(e)
S
f
C
of
_
nif
_
P(e)
S
2
f
C
of
nifP(e )
2
+ Q
nifP(e)
Q
nifS
+ Q
nifS
2
3
f
C
of
_
(III.105)
For the back interface charge, a uniform value has been assumed, chosen as the
average of the interface charge density at the source and the pinch-o point :
Q
ib[0, L
(e )]
W L
(eff)
if
_
P(e)
S
(III.106)
Saturation region From the results of section III.3.3, the following expres-
sion for the front surface potential can be readily deduced :
sf
(x) =
sfP(e )
+
S
sat
l
CLM
sinh(
x L
(eff)
l
CLM
) (III.107)
III-33
In combination with equation (III.101) this last expression allows to evaluate
the contribution of the saturation to the total gate charge :
Q
Gf [L
(e)
, L]
= C
of
S
sat
l
2
CLM
_
cosh(
L
(eff)
l
CLM
) 1
_
Q
nif [L
(e)
, L]
bob
Q
ib[L
(e)
, L]
f
C
ob
+ W L
(eff)
_
C
of
f
1
f
_
V
Gf
V
fbf
_
b
2
f
Q
of

C
bob
f
_
V
Gb
V
fbb
+
Q
b
2 C
ob
_
_
(III.108)
where Q
nif [L
(e )
, L]
and Q
ib[L
(e )
, L]
are given by :
Q
nif [L
(e)
, L]
= W L
(eff)
Q
nifP(e )
(III.109)
Q
ib[L
(e)
, L]
W L
(eff)
if
_
P(e)
S
(III.110)
III.4.3 Back-gate charge
The most straightforward way to obtain the charge on the back-gate is to
impose the charge neutrality to the MOSFET. This condition is expressed by
the following equation :
0 = Q
Gf
+ Q
Gb
+ Q
nf
+ Q
if
+ Q
of
+ Q
ib
+ Q
ob
(III.111)
where Q
of
and Q
ob
account for the xed charge trapped in the front and back
oxides.
III.4.4 Wards channel-charge partitioning scheme
In order to evaluate the drain and source charges, a proper scheme must be
found to perform the partition of the channel charge. Fossum indicated in
[III.21] that the partition scheme is of importance for the correct evaluation
of the transient currents at the drain and source. They pointed out that the
most appropriate scheme was rst introduced by Ward in [III.22]. Wards
partitioning scheme is derived from the continuity equation, which describes
the charging of the inversion layer and the interface states at some point along
the channel :
I
Cf
(x, t)
x
= W
_
Q
nf
(x, t)
t
+
Q
if
(x, t)
t
+
Q
ib
(x, t)
t
_
(III.112)
Integrating (III.112) twice along OX, the following general relationships are
obtained which relate the time-dependent current at the source and drain to
III-34
modications of the charge density proles :
I
S
(t) =
d
dt
_
W
_
L
0
_
1 x/L
_ _
Q
nf
(x, t) + Q
if
(x, t) + Q
ib
(x, t)
_
dx
_
1
L
_
L
0
I
Cf
(x, t) dx
(III.113)
I
D
(t) =
d
dt
_
W
_
L
0
_
x/L
_ _
Q
nf
(x, t) + Q
if
(x, t) + Q
ib
(x, t)
_
dx
_
+
1
L
_
L
0
I
Cf
(x, t) dx
(III.114)
Using the quasi-static assumption detailed in section III.4.1, the space average
of the instantaneous channel current can be approximated by the static current
I
DS
expressed by (III.67). Comparison of the previous two equations with
(III.93) and (III.92) then allows to formulate the denition of the source and
drain charges :
Q
S
W
_
L
0
_
1 x/L
_ _
Q
nf
(x, t) + Q
if
(x, t) + Q
ib
(x, t)
_
dx (III.115)
Q
D
W
_
L
0
_
x/L
_ _
Q
nf
(x, t) + Q
if
(x, t) + Q
ib
(x, t)
_
dx (III.116)
III.4.5 Drain and source charges
Applying the denitions developed in the previous sections, one can easily verify
that the sum of the source and drain charges is equal to the total charge stored
in the channel and in the front and back interface states :
Q
D
+ Q
S
= Q
nf
+ Q
if
+ Q
ib
(III.117)
As all quantities on the right-hand side have already been evaluated in sec-
tion III.4.2, it is sucient to evaluate Q
D
only, as Q
S
can be deduced from the
equation above.
In order to compute the drain-charge integral, it is split into the contribution
from the linear region and the one from the saturation region :
Q
D
= Q
D[0, L
(e)
]
+ Q
D[L
(e)
, L]
(III.118)
Linear region The evaluation of Q
D
in the linear region is performed by sub-
stituting the expression for dx and x from section III.4.1 into equation (III.116).
It is useful at this point to introduce new variables and
0
which allow to
simplify the charge expressions :

Q
nif
f
C
of
+
0
and
0

F
DS
v
n(sat)
W
f
C
of
T
(III.119)
III-35
This procedure yields :
Q
D[0, L
(e )
]
=
f
C
of
W
120 L
_
e
W
_
Q
nif
P(e)
S
F
DS
_
2
_
15
0
_
P(e )
+
P(e)
_
2
+ 12
3
P(e)
+ 24
2
P(e)
S
+ 16
P(e)
2
S
+ 8
3
S
5
if
_
P(e)
S
_
12
0
_
P(e)
+
S
_
+ 9
2
P(e)
+ 10
P(e)
S
+ 5
2
S
_
+ 20
_
Q
if
_
P(e)
S
_
2
_
3
0
+ 2
P(e)
+
S
_
_
+ W
L
2
(eff)
2 L
ib
_
P(e)
S
(III.120)
Saturation region As all charge densities have been assumed constant in
this region, the contribution of the saturation region to the drain charge is
easily evaluated as :
Q
D[L
(e )
, L]
= W
_
L L
(eff)
_ _
L + L
(eff)
_
2 L

_
Q
nifP(e )
+
ib
_
P(e)
S
_
(III.121)
III.4.6 Alternative formulation of the charge model
The formulation of the charge model described in the previous sections stems
from a black box approach of the MOSFET, where each terminal is considered
as a source of charging current. The model structure topology does not
reveal the essential features of the underlying physics of the device. For exam-
ple, the charge conservation must be imposed as an additional constraint on
the charge sources as with the combined equations (III.111) and (III.117). The
translation of this constraint into the model topology, as shown in gure III.9,
fails to account for the fact that the main charging currents occur between the
source/drain terminal and the front gate.
The use of an adequate model topology may enhance the accuracy of circuit
simulation, in particular the evaluation of the capacitances to the back-gate.
For this reason an alternative formulation of the charge model is proposed
which accounts for the specic behaviour of the SOI MOSFET.
III-36
Q
S
Q
D
I
DS
Q
Gf
Source
Back Gate
Drain
Front Gate
Figure III.9: The conventional macroscopic charge model.
Q
GfS
Q
GfD
Q
GfGb
Source Drain
Front Gate
Back Gate
Q
GbS
Q
GbD
I
DS
Figure III.10: The alternative physically-based circuit topology.
III-37
The model is readily deduced from the charge expressions developed above.
Q
GfS

1
f
_
Q
nifS
+
Q
of
2
_
+
1
b
b
_
Q
ibS
+
Q
ob
2
_
1 +
C
bob
C
ob
4
f
Q
b
(III.122)
Q
GfD

1
f
_
Q
nifD
+
Q
of
2
_
+
1
b
b
_
Q
ibS
+
Q
ob
2
_
1 +
C
bob
C
ob
4
f
Q
b
(III.123)
Q
GbS

1
f
f
_
Q
nifS
+
Q
of
2
_
+
1
b
_
Q
ibS
+
Q
ob
2
_
1 +
C
bof
C
of
4
b
Q
b
(III.124)
Q
GbD

1
f
f
_
Q
nifD
+
Q
of
2
_
+
1
b
_
Q
ibD
+
Q
ob
2
_
1 +
C
bof
C
of
4
b
Q
b
(III.125)
Q
GfGb

W L
1/C
of
+ 1/C
b
+ 1/C
ob
_
V
Gf
W
f
+ W
b
V
Gb
_
+ C
of
S
sat
l
2
CLM
_
cosh(
L
(eff)
l
CLM
) 1
_
(III.126)
where the following notations were used for charge integrals :
Q
nifS
W
_
L
0
_
1 x/L
_
Q
nif
dx (III.127)
Q
ibS
W
_
L
0
_
1 x/L
_
Q
ib
dx (III.128)
Q
nifD
W
_
L
0
_
x/L
_
Q
nif
dx (III.129)
Q
ibD
W
_
L
0
_
x/L
_
Q
ib
dx (III.130)
The front and back channel body coecients are dened by :
f
1 +
C
bob
C
of
and C
bob
ob
C
b
C
ob
+ C
b
(III.131)
b
1 +
C
bof
C
ob
and C
bof
of
C
b
C
of
+ C
b
(III.132)
This charge model has been used for the implementation of the SOI MOSFET
routines into the harmonic balance simulator OSA. This model topology is also
at the basis of the small signal distributed channel model developed in the next
section.
III.5 Operation at microwave frequencies
All developments of section III.4 rely on the quasi-static assumption which was
introduced in subsection III.4.1. This assumption reduces the applicability of
III-38
the model to signals which vary slowly with respect to the channel propagation
delay, so that, at this peculiar time-scale, a static distribution may be used
at all instants for the channel charge density. In microwave operation, this
quasi-static condition is generally not met. This can be easily veried using a
simple evaluation of the channel propagation delay used by Tsividis in [III.6]
for similar purposes. The order of magnitude of the channel propagation delay,
O(
Cf
), for a MOSFET at the onset of saturation is estimated on the basis of
the time needed for a carrier to cross the whole channel :
O(
Cf
)
L
2
V
DS
(III.133)
In the case of a 1.0 micrometer channel at 1.0V, the formula predicts an order of
magnitude around 20 picoseconds, which is a non-negligible fraction of the 500
picosecond period of a 2GHz sinusoid. The case of a MOSFET in saturation is
even rather favourable, due to the presence of the strong longitudinal eld which
sweeps the carriers through the device at high speeds. The worst situation in
terms of channel delay is at V
DS
= 0.
In order to extend the applicability of the quasi-static current and charge
expressions to operation at microwave frequencies, it has been proposed to split
the channel into suciently small sections where the quasi-static conditions
would eventually be fullled. Tsividis reported an alternative approach based
on the continuity equation which allowed to obtain analytical expressions of the
small-signal waveforms along the channel in the case of a bulk MOSFET. Using
these waveforms, he proposed a small-signal equivalent circuit topology for the
MOSFET in non-quasi-static operation. A similar approach is developed in
subsection III.5.2 to obtain an analytical model of the worst-case situation,
namely at V
DS
= 0. The draw-back of these analytical models, is that they
apply only to small signals. In order to obtain a model of sucient generality
i.e., allowing large-signal excitations at any bias point the rst approach
will be used : In section III.5.3, the channel is split into discrete chunks, where
the quasi-static current and charge expressions are applied. The analytical
model can then be used to evaluate the accuracy of the discretisation scheme,
and decide in particular whether enough channel sections were introduced.
III.5.1 The non-quasi-static small-signal model topology
Using the current transport and the current-continuity equations, several au-
thors propose analytical expressions for the small-signal waveforms propagating
along the channel of bulk MOSFETs. Using an iterative solution method of
the same systems of equations, Bagheri and Tsividis, [III.23], developed ana-
lytical expressions of all elements of the indenite admittance matrix charac-
terising the bulk MOSFET in non-quasi-static operation. Tsividis proposed in
his book [III.6] the equivalent circuit topology of the gure as implementation
for the NQS admittance matrix in a simulator. The capacitances are derived
III-39
Front Gate
Source
Drain
Back Gate
C
GfDi
R
GfDi C
GbDi
R
GbDi
C
GfSi
R
GfSi C
GbSi
R
GbSi
G
Di
L
Di
C
GfGbi
G
mbi
1+j
1
G
m
1+j
1
Figure III.11: Non-quasi-static small-signal equivalent circuit for the intrinsic
MOSFET.
from the conventional charge model as follows :
C
GfSi

dQ
Gf
dV
S
C
GfDi

dQ
Gf
dV
D
(III.134)
C
GbSi

dQ
Gb
dV
S
C
GbDi

dQ
Gb
dV
D
(III.135)
C
GfGbi

dQ
Gf
dV
Gb
(III.136)
The (trans-)conductances are given by :
G
m

dI
D
dV
Gf
(III.137)
G
mbi

dI
D
dV
Gb
(III.138)
G
Di

dI
D
dV
D
(III.139)
The resistors R
GfSi
, R
GfDi
, R
GbSi
and R
GbDi
as well as the inductor L
Di
model
the NQS eects by introducing several new time-constants which account for
the delays in the channel response. These circuit elements are dened as :
R
GfSi
C
GfSi
= R
GbSi
C
GbSi
=
1
2
(III.140)
R
GfDi
C
GfDi
= R
GbDi
C
GbDi
=
1
3
(III.141)
L
Di
G
Di
=
1
(III.142)
Tsividis, [III.6], reports expressions of the time-constants as a function of the
applied bias-voltages in the case of bulk MOSFETs. These expressions can be
III-40
easily adapted to the SOI MOSFET :
1
=
4
15
1
0
1 + 3 +
2
_
1 +
_
3
(III.143a)
2
=
1
15
1
0
2 + 8 + 5
2
_
1 +
_
2
_
1 + 2
_
(III.143b)
3
=
1
15
1
0
5 + 8 + 2
2
_
1 +
_
2
_
2 +
_
(III.143c)
where and
0
are given by :
1
V
P(e )
V
P(sat)
(III.144)
0

_
V
Gf
V
Thf
_
f
L
2
(III.145)
III.5.2 The distributed channel model at V
DS
= 0
V
C
V
C
+ dV
C
Front Gate
Back Gate
dx C
GfGb
dx C
GfC
dx C
GbC
dx R
Cf
Figure III.12: The distributed equivalent circuit of the channel at V
DS
= 0.
At zero drain/source bias, the surface potential and the inversion charge
density are uniform across the whole device. The small-signal series resistance
R
Cf
and the capacitances of an innitesimal channel section to the front and
back gates, C
GfC
and C
GbC
, are thus constant along the channel. As a result,
the channel of a SOI MOSFET propagates small-signal waveforms applied at
its ends as a distributed RC line when both gates are connected to the RF
ground. Classical transmission-line theory then provides simple expressions for
the propagation constant,
Cf
, the characteristic impedance, z
Cf
, and nally
the admittance matrix of the common-gates SOI MOSFET at V
DS
= 0 , Y
Cf
.
III-41
Frequency
Hz
20
40
60
80
100
120
140
R
(i, j )
10
8
10
9
10
10
R
(2, 2)
R
(1, 2)
R
(2, 1)
R
(1, 1)
10
8
10
9
10
10
0
0.1
0.2
0.3
0.4
-0.5
0
0.5
0.2
1
C
Gf
pF
V
Gf
Figure III.13: The distributed eects in the channel at V

DS
= 0 of a
common-source MOSFET : A series resistance at the gate terminal, resis-
tive coupling between drain and gate, variation of R
(i, j )
Re(Z
(i, j )
) and of
C
Gf

_
Im(Z
(1, 1)
)
1
versus frequency.
Cf

_
j R
Cf
_
C
GfC
+ C
GbC
_
(III.146)
z
Cf

_
R
Cf
j
_
C
GfC
+ C
GbC
_ (III.147)
Y
Cf
=
1
z
Cf
sinh(
Cf
L)
_
cosh(
Cf
L) 1
1 cosh(
Cf
L)
_
(III.148)
The expressions for the capacitances per unit-length of channel are readily
obtained from the alternative charge model, considering a uniform distribution
of charge :
C
GfC
= W
1
f
dQ
nf
dV
C
(III.149)
C
GbC
= W

f
1
f
dQ
nf
dV
C
(III.150)
Using the transcendental equation of the inversion charge proposed by Park
et al. in [III.11], the evaluation of the above expressions can be considerably
simplied :
dQ
nf
dV
C
= Q
nf
_
T

Q
nf
f
C
of
_
1
(III.151)
The series resistance per unit-length follows immediately from equation (III.62)
of the transport model.
R
Cf
R
Cf
/L = W Q
nf
(III.152)
III-42
In order to fully characterise the small-signal response of the SOI MOSFET,
a 4 4 admittance matrix is required which relates the terminal currents to
the applied small-signal voltages as shown in (III.153) :
_
_
I
D
I
Gb
I
Gf
I
S
_
_
= Y
FET

_
_
V
D
V
Gb
V
Gf
V
S
_
_
(III.153)
The sixteen admittance elements can be computed very easily if one considers
the following four independent excitation schemes :
1. Drain excitation, V
D
,= 0, while all other terminals are connected to the
signal ground, V
S
= V
Gb
= V
Gf
= 0;
2. Source excitation, V
S
,= 0, while V
D
= V
Gb
= V
Gf
= 0;
3. Common mode excitation of the gates, V
Gf
= V
Gb
,= 0 while the source
and drain are grounded, V
S
= V
D
= 0;
4. Asymmetric excitation of the gates, V
Gf
=
GbC
/
GfC
V
Gb
,= 0, while
V
D
= V
S
= 0. The peculiar excitation ensures that all points of the chan-
nel remain level with the source and drain, so that the series small-signal
current is uniformly zero in the channel, which simplies the calculations.
Calculating the small-signal currents at all ports, and rearranging the expres-
sions in function of the terminal voltages then yields the small-signal admit-
tance matrix of the MOSFET :
Y
FET
=
_
_
Y
Cf (1, 1)

GbC
k
Y
Cf (1, k)
GbC
k
Y
Cf (k, 1)

2
GbC
k, l
Y
Cf (k, l)
+
_
2
GbC
C
GfC
+ C
GfGb
_
GfC
k
Y
Cf (k, 1)

GfC

GbC
k, l
Y
Cf (k, l)

_
2
GbC
C
GfC
+ C
GfGb
_
Y
Cf (2, 1)

GbC
k
Y
Cf (2, k)
GfC
k
Y
Cf (1, k)
Y
Cf (1, 2)
GfC

GbC
k, l
Y
Cf (k, l)

_
2
GbC
C
GfC
+ C
GfGb
_

GbC
k
Y
Cf (k, 1)
2
GfC
k, l
Y
Cf (k, l)
+
_
2
GfC
C
GbC
+ C
GfGb
_

GfC
k
Y
Cf (k, 1)
GfC
k
Y
Cf (2, k)
Y
Cf (2, 2)
_
_
(III.154)
where the following notations were used :
GfC

C
GfC
C
GfC
+ C
GbC
(III.155)
GbC

C
GbC
C
GfC
+ C
GbC
(III.156)
C
GfC
LC
GfC
(III.157)
C
GbC
LC
GbC
(III.158)
III-43
The capacitance C
GfGb
is the depletion capacitance of the structure and stems
directly from the alternative charge model.
C
GfGb

dQ
GfGb
dV
Gb
(III.159)
This model has proven particularly useful for the wide-band extraction of the
mobility model parameters from S-parameters measurements as described in
another chapter.
III.5.3 A non-quasi-static large-signal channel model
Q
GfC(k)
Q
GfGb
Source
Drain
Front Gate
Back Gate
Q
GbC(k)
I
Cf (k)
k = 1 k = N
k = 0
Figure III.14: Topology of the discrete channel model.
In order to better account for the charging delays, the MOSFET structure is
divided into N chunks along the channel. All chunks have a xed length equal
to L/N. The endpoints of these channel sections are numbered from 0 at the
source to N at the drain. Each channel section is considered to be a transistor
with its own charges and current. The model topology is a generalisation of the
alternative charge model presented in section III.4.6. At each channel point k
located at x = x
k
, two nonlinear charge sources are connected to the front
and back gate. These charges correspond to a weighted integral of the charge
densities around the channel point :
Q
GfC(k)
= Q
GfD[x
k1
, x
k
]
+ Q
GfS[x
k
, x
k+1
]
(III.160)
Q
GbC(k)
= Q
GbD[x
k1
, x
k
]
+ Q
GbS[x
k
, x
k+1
]
(III.161)
where Q
GfD[x
k1
, x
k
]
is the gate/drain charge of section k considered as tran-
sistor with its source at x
k1
and its drain at x
k
. It is evaluated according to
the alternative charge model. Special cases arise at the drain and source of the
complete SOI MOSFET structure :
Q
GfC(0)
= Q
GfS[x
0
, x
1
]
(III.162)
Q
GbC(N)
= Q
GbD[x
N1
, x
N
]
(III.163)
III-44
The state of each channel point is characterised by by a voltage, V
C(k)
, and
a charging level of the interface states Q
if (k)
and Q
ib(k)
. When N is chosen so
that the the last section on the drain-side of MOSFET structure is suciently
long to comprise the whole saturation region in all biasing congurations, then
only this section must be capable of saturation and channel length modula-
tion. All other sections will always function in the linear regime. As a result,
the inversion charge density values Q
nf (k)
necessary for the evaluation of the
charges and the currents can be deduced directly from equation (III.37) for all
channel points except the drain-point, numbered N. The threshold voltage is
evaluated at each channel point according to expression (III.55) with V
DS
be-
ing the drain/source voltage applied to the whole MOSFET structure. Q
nf (N)
is computed according to the unied model described in section III.3.4. The
charges at points N 1 and N must take the contribution of the saturation
region into account.
To obtain the response of the MOSFET to an input wave-form, the simu-
lator into which the model is implemented, must determine all of the channel
point voltages V
C(k)
so that the Kirchos equations at all channel nodes are
veried. These Kirchos equations represent in eect a discrete version of the
continuity equation, and implement a higher-order partitioning scheme than
the Wards scheme. The accuracy gained for the high-frequency response is
however traded for computation time. As N increases, the number of nonlin-
ear current sources increases, and the resolution of the circuit equations slows
down. Careful selection of N is necessary, to obtain accuracy at an aord-
able price. By comparing the responses predicted by the analytical distributed
channel model and the discrete channel model at V
DS
= 0 which is known
to be a worst case situation , one can nd that three channel sections seem
to realise a good compromise.
Frequency
Hz
C
Gf
pF
10
8
10
9
10
10
0.1
0.15
0.2
0.25
0.3
0.35
Transmission line
Three sections
Five sections
Single section
0
20
40
60
80
100
120
10
8
10
9
10
10
140
R
(i, j )
R
(2, 2)
R
(2, 1)
R
(1, 1)
Figure III.15: Comparing the analytical distributed channel model and the
discrete model with N = 1, 3, 5, at V
Gf
= 1.0 V and V
DS
= 0.
III-45
III.6 Small-signal model for the extrinsic device
Up till now, the attention has been focussed exclusively on the intrinsic part
of the device. The intrinsic model does however not suce to describe the
behaviour of the MOSFET at high frequencies. It is now thus necessary to
concentrate on the extrinsic part, which is dened mainly by its complemen-
tarity to the intrinsic part. All physical phenomena which were not accounted
for in the intrinsic model, become de facto part of the extrinsic model. Ac-
cording to the description given in the introductory section III.1.4, the extrinsic
model must account for : diusion and contact resistances, overlap and fring-
ing capacitances from the front gate to the diusions, junction capacitance,
substrate coupling eects, resistivity of the polysilicon gate, edge eects of the
active zone, etc. Several of these eects have even a determining inuence
on the performance of the SOI MOSFET at microwave frequencies, as Jean-
Pierre Raskin and Jian Chen demonstrated in their doctorate thesis, [III.24]
and [III.25].
III.6.1 Diusion and contact resistances
In MOSFET technology, the current leaving the channel must travel some dis-
tance in the diusion regions, in order to reach the nearest contact hole where
a connection to the metal layer is achieved. This short section of the current
path is responsible for the almost all of the extrinsic resistance in series with
the transistor channel. Indeed, even heavily doped silicon oers only a limited
conductivity which combined with the limited lm thickness, results in sheet
resistivities on the order of several tens of /. In comparison, one micrometer
thick aluminium lines have a resistivity on the order of 0.03 /. As demon-
strated by Chen, [III.25], formation of a metal silicide on the diusion region
allows not only to reduce the sheet resistivity down to 2.0 /, but also to
enhance the quality of the contacts to the metal layer. Raskin, [III.24], showed
that reduction of the extrinsic source resistance R
Se
is of primary importance
for the microwave performance of the common source MOSFET : R
Se
not only
produces an unwanted feedback which tends to reduce the power gain of the
MOSFET, but also inuences the noise performance detrimentally.
The contribution of the diusion and contact resistance to the extrinsic
series resistances at the source or drain, is readily evaluated as :
R
Xe
=
L
di
W
r
di
+
1
N
ctct
r
ctct
(III.164)
where W is the width of the active zone, L
di
is the diusion length measured
from the metallurgical junction to the middle of the contact area, r
di
is the
diusion sheet resistivity and r
ctct
is the resistance of an individual contact.
Expression (III.164) is a low-frequency approximation for the extrinsic series
resistances R
Se
and R
De
. It does not account for signal propagation eects
along the drain and source feeding lines. Subsection III.6.3 will show under
which conditions the low-frequency approximation holds for source and drain.
III-46
III.6.2 Parasitic capacitances
Microwave performance of MOSFETs is essentially achieved by down-scaling
of the device geometry. This allows to rise the current gain cut-o frequency
of the intrinsic device at the expense of an increased inuence of the parasitic
capacitance on the device response. Indeed, some parasitic capacitances tend
to be scaling-independent, such as the lateral gate-diusion capacitance, or are
dicult to scale properly, as the gate-diusion overlap capacitance. Adequate
modelling of these capacitances is necessary at microwave frequencies as the
charging currents which they drain become very important and eventually will
contribute signicantly to the degradation of the current gain. Substrate cou-
pling capacitances need also to be properly accounted for, particularly at the
lower end of the microwave spectrum were the SOI substrate eventually goes
through dielectric transitions which imply a radical change in its behaviour.
Overlap and fringing capacitances of the polysilicon gate
The development of submicrometer MOSFET technologies has urged the need
to understand and model the geometry-dependence of the gate parasitic ca-
pacitances, C
GfSe
and C
GfDe

Wang, [III.26], distinguishes among several com-
ponents of the gate parasitic components based on their specic dependence
upon the geometrical parameters of the gate :
1. The overlap capacitance, c
ovlp
, depending on the gate oxide thickness and
the length of the overlap between the gate and the diusion.
2. The lateral capacitance, c
latrl
, depending mainly on the polysilicon thick-
ness, the gate oxide thickness and on the spacer material. It is associated
with the electric eld emerging from the sidewalls of the gate.
3. The inner fringing capacitance, c
inner
, which is associated with the elec-
tric eld emerging from the bottom of the gate and converging towards
the metallurgical junction of the diusions. This capacitance is related to
existence of a depletion region controlled by the gate and the diusion. Its
contribution vanishes when the device is biased in strong accumulation.
4. The top side capacitance, c
top
, which is associated with the electric eld
emerging from the top side of the gate. It depends upon the gate length,
the polysilicon thickness and the gate oxide thickness.
Approximate expressions for the rst three capacitance components were pub-
lished by Shrivastava in [III.27]; Wang proposed an approximation for the top
side capacitance in [III.26]. It is however questionable whether these expres-
sions based on a crude partition of the conguration are capable of sucient
accuracy in order to allow extraction of geometrical parameters by curve-tting.
Huang et al., [III.28] preferred to use two-dimensional device simulation for this
purpose.
Few authors account for the bias-dependence of c
inner
, and simply model
the eect to which it is associated by connecting a constant capacitor between
the gate and the source or drain diusion. This is justied in the case of
III-47
c
top
c
latrl
c
ovlp
c
inner
Metal contact
Gate polysilicon
Buried oxyde
Substrate
Figure III.16: Field lines of the dierential electric eld resulting from a per-
turbation of V
Gf
in the case of a depleted device.
depletion, but in strong inversion the surface potential value
sf
is known to
be pinned at approximately V
C
+ 2
F
, so that one may anticipate that the
inner fringing electric eld will stop varying once saturation is reached. A more
realistic model is obtained if one considers the charge associated with the inner
fringing eld, Q
inner
:
Q
inner[S]
= W c
inner
_
sfS
V
S
_
(III.165)
Q
inner[D]
= W c
inner
_
sfD
V
S
_
(III.166)
These charges simply add to the gate/source and gate/drain charges of the
alternative charge model. This model is valid as long as the lm body remains
depleted : from depletion to inversion.
Substrate coupling capacitances
Many authors involved in SOI MOSFET modelling consider that the underlying
substrate is suciently conducting so as to maintain a uniform potential at the
interface with the buried oxide. This is certainly the case at suciently low
frequency, when the carriers have plenty of time to rearrange themselves close
to the interfaces in order to stop the penetration of a normal electric eld
into the substrate material. At higher frequency, the delays involved in the
mechanisms supplying the carriers diusion or generation/recombination
allow only a partial rearrangement of the carriers so that the electric eld can
penetrate the substrate.
Raskin et al., [III.29], investigated the substrate coupling eects on SOI
wafers. They validated a modelling approach for multi-layer substrates, based
on the translation of the dielectric properties of individual layers into parallel
RC circuits and their interconnection according to the topology of the electric
III-48
Gate polysilicon
S. and D. diusions
Buried oxyde
Substrate
C
DSe
C
Se
C
SGbe
R
SGbe
Figure III.17: Field lines of the dierential electric eld resulting from a high-
frequency perturbation of V
D
int the case of a depleted device.
eld lines. This technique applied to the SOI MOSFET structure yields the
equivalent circuit of gure III.18.
Drain
Back Gate
Source
C
De
C
Se
C
DSe
C
DGbe
R
DGbe
C
SGbe
R
SGbe
C
Gbe
R
Gbe
Wafer back-plane
Figure III.18: Equivalent circuit model of the substrate coupling eects.
The physical correspondence of each equivalent circuit element is illustrated
in gure III.17 : The capacitance C
DSe
accounts for the coupling between
source and drain occurring exclusively through the air or the oxide surrounding
the diusion and the metal. The capacitances C
De
and C
Se
account for the
eld lines crossing the buried oxide. The resistances and capacitances C
XGbe
and R
XGbe
account for eld lines in the substrate under the buried oxide.
The coupling to the wafer back-plane is embodied by R
Gbe
and C
Gbe
. As the
distance involved in this latter coupling is at least two order of magnitude larger
III-49
than the channel length the characteristic distance for the drain/source
coupling , it is clear that at high frequencies the back gate is more inuenced
by the capacitive coupling to the source and drain than by the presence of a
ground contact at the wafer back-plane. The DC voltage at the interface of
the substrate and the buried oxide is however well controlled by the back-plane
contact. The frequency at which the SOI structure switches from the DC to
the RF behaviour depends on the substrate resistivity. For a 200/cm p-type
wafer, the transition occurs around 100 MHz.
III.6.3 Lateral signal distribution in the basic MOSFET
cell
In MOS technology, it is common practice to have metal lines run in parallel to
the polysilicon gate and to connect them at regular intervals with the diusions
along the width of the transistor. This design minimises the source and drain
series resistance as well as the amount of overlap between the various electrodes,
and hence the parasitic capacitance. In technologies with multiple metallisation
levels, variations are possible, such as interconnection of the source lines by
a bridge on top of the gate and drain lines, allowing further reduction in
the gate and source resistance at the cost of an increase in some parasitic
capacitances.
Gate polysilicon
Source metal Drain metal Diusion
W
OZ
OX
Figure III.19: Top view of the basic MOSFET cell in a single metallisation
and single polysilicon layer technology, showing the parasitic impedance of the
feeding lines.
The striking feature of these designs is that at least two of the lines are fed at
their ends, requiring the signal to propagate along the width of the transistor.
In the case of small signals, the structure of gure III.19 can be described very
generally as a section of coupled transmission lines : The distributed shunt
admittance matrix of the system corresponds to a MOSFET device of unit-
width, comprising the intrinsic device, the drain and source series resistances
and the shunt capacitive parasitics. The distributed series impedance matrix
accounts for the resistance of the signal lines as well as their self- and mutual
inductances. The dominating series parasitic eect is the gate resistance. For
III-50
a sheet resistivity of 4.0 / and a gate-width of 1.0 m, the gate resistance
is 4.0 /m, while the inductances result in a reactance of 0.018 /m at 10.0
GHz and the metal resistance amounts to 0.0037 /m, for 8.0 m lines of 1.0
m thick aluminium.
The gate resistance
To evaluate the eect of the resistivity of the gate line, it seems quite reason-
able in view of the gures given above to assume that the metal lines
are equipotential. As indicated in subsection III.6.2 dealing with substrate
coupling, at suciently high frequency the back gate is not tied anymore to
the ground, but behaves as a oating node. These considerations allow to re-
duce the coupled line system to a single transmission line for which the voltage
and current distributions can be readily evaluated using adequate boundary
conditions :
V
Gf
(z) =
V
Gf [in]
cosh(
gate
W)
cosh(
gate
z) (III.167)
I
Gf
(z) =
z
gate
V
Gf [in]
cosh(
gate
W)
sinh(
gate
z) (III.168)
where V
Gf [in]
is the applied voltage at the input of the gate line;
gate
and z
gate
are given by :
gate

_
Z
Gfe
Y
FET(1, 1)
(III.169)
z
gate

_
Z
Gfe
Y
FET(1, 1)
(III.170)
Z
Gfe
is the lineic series impedance of the gate, including both resistive and
inductive eects. Y
FET
is the lineic admittance matrix of the common source
MOSFET structure incorporating the diusion resistances and the capacitive
parasitics. Y
FET(1, 1)
is the diagonal element corresponding to the gate termi-
nal.
Using the voltage waveform of equation (III.167), expressions can be ob-
tained for the hybrid immittance elements of the complete MOSFET cell :
V
Gf
I
Gf
V
D
=0
H
(1, 1)
= z
gate
coth(
gate
W) (III.171a)
I
D
I
Gf
V
D
=0
H
(2, 1)
=
Y
FET(2, 1)
z
gate
gate
(III.171b)
V
Gf
V
D
I
Gf
=0
H
(1, 2)
=
Y
FET(1, 2)
Y
FET(1, 1)
(III.171c)
I
D
V
D
I
Gf
=0
H
(2, 2)
= W
Y
FET(2, 2)
Y
FET(1, 1)
Y
FET(1, 2)
Y
FET(2, 1)
Y
FET(1, 1)
(III.171d)
III-51
These equations call for some comments. As expected, the impedance seen at
the gate, H
(1, 1)
, is aected by propagation eects. The current gain, H
(2, 1)
, is
paradoxally not aected by these eects, as can be seen from equation (III.172b),
which is the exact expansion of (III.171b). The voltage gain, the forward
transadmittance and the maximum available gain are however well inuenced
by the propagation characteristics of the gate line.
Chen pointed out in his thesis, [III.25], that reducing the length of the
gate line is an ecient way of improving the microwave performance of SOI
MOSFETs. Microwave transistors designed in the present work typically have
gate line lengths corresponding to an attenuation of the voltage less than 5 %.
In this case, [
gate
W[ 1.0 so that the hyperbolic cotangent can be closely
approximated by the series development shown in (III.172a) :
H
(1, 1)
z
gate
_
1
gate
W
+

gate
W
3
+ O((
gate
W)
2
)
_
=
1
Y
FET(1, 1)
W
+
Z
Gfe
W
3
(III.172a)
H
(2, 1)
=
Y
FET(2, 1)
Y
FET(1, 1)
(III.172b)
H
(1, 2)
=
Y
FET(1, 2)
Y
FET(1, 1)
(III.172c)
H
(2, 2)
= W
Y
FET(2, 2)
Y
FET(1, 1)
Y
FET(1, 2)
Y
FET(2, 1)
Y
FET(1, 1)
(III.172d)
These equations and particularly expression (III.172a), show that the small-
signal propagation eects along the gate can be modelled accurately by insert-
ing a resistor R
Gfe
in series with the gate terminal of the ideal admittance
matrix Y
FET
:
R
Gfe

W
3
r
poly
(III.173)
Y
FET
W Y
FET
(III.174)
Inductances
As can be inferred from the previous section, a discrete equivalent circuit model
should also suce to describe the inuence of the inductive eects on the signal
distribution in the basic MOSFET cell. The narrowspacing imply an important
magnetic coupling between the conductors, so that an accurate model of the
inductive eects on the cell would require six parameters : three mutual and
three self-inductances. Very few authors have published such models with
some rare exceptions in the case of work on travelling-wave devices. The main
reason for this is that inductive eects emanating from the distribution lines
in the basic MOSFET cell are generally overwhelmed by the contribution of
external inductances.
III-52
This is easily illustrated with the following case-study. In a saturated de-
vice, the majority of the gate current charges the capacitor C
GfSi
and ows
back along the source line. The series inductance per unit-length in the gate
can thus be evaluated as the dierence between the self inductance and the
gate/source mutual inductance, or half of the lineic inductance value obtained
for two coplanar strips, L
CPS
. Equation (III.172a) then allows to deduce the
total series inductance of the gate :
L
Gf [0, W]e
=
W
6
L
CPS
(III.175)
For MOSFETs fabricated at the UCL, L
CPS
= 0.55pH/m and W = 24m,
so that L
Gf [0, W]e
amounts to 2.2 pH, which is only one tenth of the value
routinely extracted from measurements of such transistors.
III.6.4 Dedicated model for the common-source congu-
ration
In order to compensate for the limitation on the transistor width W imposed
by the propagation characteristics of the basic MOSFET cell, several identical
cells are placed in parallel and interconnected to form the interdigitated combs
structure occupying the active zone indicated in gure III.20.
Gate
Drain
Measurement planes
Active Zone Edges
Figure III.20: Layout of a common source MOSFET structure embedded in a
coplanar waveguide.
III-53
The eect of the interconnection of N
cell
basic cells on the equivalent circuit
parameters can be readily evaluated by replacing the width parameter W by
the product N
cell
W in all previous equations, with the exception of equations
involving inductances. The scaling rules for the inductances of the multiple
cell structure are complicated by the mutual coupling between traces and by
the inductance of the cross-connections. One may however expect that the
global inductance values in the multiple cell structure will be less than the
corresponding values for a single cell, so that the contribution of inductive
eects from the active zone is nally quite small.
To be consistent with the measurement procedure described in a previous
chapter, the model must be extended to include the contribution of all regions
enclosed within the reference planes. In particular, the eects of the metal
lines and tapers running from the reference planes to the active zone must be
accounted for. These short interconnections are modelled using the lumped
equivalent circuit of gure III.21. The topology of the shunt sub-circuit is in-
herited directly from the substrate coupling model of Raskin, [III.24]. The in-
ductance L
met
can be approximated using the lineic inductance for the coplanar
waveguide, L
CPW
= 0.4 pH/m, multiplied by an eective length depending
upon the layout geometry. Typically : L
met
L
CPW
60.0 m = 24.0 pH.
C
air
C
box
C
subs R
subs
L
met R
met
Figure III.21: Equivalent circuit for the coplanar waveguide taper structures.
The complete equivalent circuit for the as-measured common-source SOI
MOSFET is shown in gure III.22. The intrinsic part corresponds to three mod-
els described in section III.5. The substrate model is detailed in gure III.18.
The dominant contribution to R
Se
and R
De
comes from the diusion resistance
as explained in subsection III.6.1. The value of R
Gfe
is aected by distribution
eects described in subsection III.6.3. C
GfSe
and C
GfDe
comprise the overlap,
the lateral and the top parasitic capacitances of the gate which were intro-
duced in subsection III.6.2. The inductances L
Gfe
and L
De
are dominated by
the contribution from the lines and tapers. The source inductance L
Se
is at-
tributed to the vertical path connecting the source of all basic cells to ground.
The admittance Y
Gfa
groups the contributions of the shunt elements from the
input line and taper, together with the capacitances due to the crossings of
polysilicon lines and the source interconnection metal. Y
Da
is due to the line
and taper at the output. Y
GfDa
corresponds to the capacitive coupling occur-
III-54
III.7 Model limitations
ring between the gate and drain lines outside of the active zone. The index a
means adjacent designating eects located just outside of the active zone.
Y
Gfa
, Y
Da
and Y
GfDa
are thus by denition independent of W.
Intrinsic
MOSFET
Substrate
Drain
Front Gate
Source
C
GfDe
C
GfSe
L
Gfe
R
Gfe
R
De
L
De
L
Se
R
Se
Y
Gfa
Y
Da
Y
GfDa
Figure III.22: The complete equivalent circuit topology for the SOI MOSFET.
This section discusses the restrictions which apply for the simulation of fully
depleted SOI MOSFETs using the model described in this chapter. A user-
oriented perspective is adopted and all limitations are expressed in terms of
validity ranges constraining input parameters or variables.
III.7.1 Channel length
Three short-channel eects have been identied in section III.2.5 : Channel-
length modulation, drain-induced barrier lowering and charge-sharing. Sec-
tions III.2.5 and III.3.3 provide the means to account for these eects within
the frame-work of the charge-sheet model, thus extending its applicability to
short-channel devices.
The channel-length modulation eect is introduced using the eective chan-
nel length L
(eff)
evaluated according to the algorithm described in section III.3.4
and based essentially on equation (III.88). The main parameter in this equation
III-55
is l
CLM
, the characteristic length, which contains all technological dependen-
cies of equation (III.88). More precisely, in xed biasing conditions, l
CLM
determines the eective channel shortening, L
(eff)
= L L
(eff)
, directly.
l
CLM
t
b
_
C
b
2
f
C
of
_
1 +
C
b
C
b
+ C
ob
_
(III.176)
The ratio (l
CLM
/L) can hence be used as invariant characterising the severity
of the channel-length modulation eect for various SOI MOSFET designs.
Drain-induced barrier lowering is modelled by a threshold voltage correction
given in equation (III.55). This correction is proportional to the applied drain-
source voltage, V
DS
, and the proportionality constant
fD
is given by :
fD

_
1 +
C
b
C
b
+ C
ob
_
C
b
t
2
b
C
of
L
2
=
2
f
l
2
CLM
L
2
(III.177)
where the ratio (l
CLM
/L) can be again identied as a measure of the severity
of the short-channel eect.
Charge-sharing has not been included in the model because Colinge, [III.2],
has shown that, in the case of 100 nm-thick lms, charge-sharing only has an
inuence when L < 0.3 m, which well below the smallest feasible channel
length in the UCL technology.
As already stated in section III.5.3, the discretisation scheme applied to
the channel combined with the constraint that only a single section may be in
saturation, imposes a practical limit on the smallest channel length :
L > N max(L
(sat)
) (III.178)
In the case of the UCL technology, with its 100 nm-thick silicon lm, a maxi-
mum supply voltage of 3.0 V and three channel sections, the limit turns out to
be 0.36 m.
In this work, the model has been successfully used for MOSFETs fabricated
at the UCL with channel lengths in the range of 1.5 m to 0.6 m. Using the
l
CLM
/L invariant, these results can be extrapolated to the LETI technology,
[III.30], where they correspond to channel lengths between 0.5 m and 0.2 m,
thanks to the vertical down-scaling of the structure. As the charge-sharing
eect diminishes when the thickness decreases, one may expect that it will
have no signicant inuence for LETI devices even around 0.2 m.
III.7.2 Biasing conditions
There exist several limitations to the range of biasing conditions over which
the characteristics predicted by the current and charge model are valid. In
the case of the gate voltage, V
Gf
, the limitation stems from the expressions
of the channel charge density, (III.36) or (III.37), which are only valid from
depletion to strong inversion, excluding all negative gate voltages at which
partial depletion or front-accumulation occur. For the UCL technology, the
range is typically : 1.5 V < V
Gf
.
III-56
The back-gate voltage is limited by the condition Q
nb
0 imposed in sec-
tion III.2.1. Accumulation and inversion of the back-channel must be avoided,
so that V
Gb
must be enclosed between the at-band voltage across the buried
oxide and the threshold voltage for the inversion of the back-channel. The
typical range for the UCL MOSFETs is thus approximately : 10 V < V
Gb
<
+10 V.
The drain voltage is limited by the avalanche break-down phenomenon
which is not accounted for in the model. Avalanching not only aects the
current-voltage characteristics but also increases the capacitive drain-gate cou-
pling by the accumulation of holes at the bottom of the lm. At the UCL, the
breakdown voltage lies higher than 3 V for 1.0 m channel lengths. Self-heating
also limits the validity range for the drain-voltage, as the model assumes a xed
temperature for the device. Experience has shown that self-heating becomes
non-negligible when the DC power consumption rises above 0.2 mW/m of
channel width.
III.7.3 Scaling rules
Scaling rules were described in section III.6. The fundamental scaling equations
are (III.173) and (III.174) which dene the scaling along a single gate nger.
Rules (III.173) and (III.174) apply only when the attenuation of the signal
along the gate is suciently low. An upper-bound to the active zone width,
W, can be found if a maximal attenuation along the gate, A
RC(max)
, is specied
at some frequency :
W <
2
acosh(A
2
RC(max)
)
_
C
of
r
poly
(III.179)
In the UCL technology, a maximal attenuation of 0.5 dB at 40 GHz imposes an
upper limit of 30 m on the active zone width.
The scaling rules for a single gate-nger are completed with rules for struc-
tures comprising multiple ngers in subsection III.6.4. The scaling rule for
the number of gate-ngers, N
cell
, is a plain proportionality rule. One may ex-
pect that this rule remains valid as long as the lateral extent of the transistor
structure remains on the order of the ground to ground spacing of the feeding
CPWs.
The additional scaling rules mentioned in subsection III.6.4 also state that
all adjacent admittances are independent on the active zone width, W. This
assumption results in a lower bound on W, because direct coupling between
the gate- and drain-feed becomes important at small W, typically around a few
m.
III.7.4 Frequency
For the non-quasi-static small-signal model of section III.5.1, the frequency
limits of validity has been given by Tsividis, [III.6], and corresponds to the
characteristic pulsation
0
given in equation (III.145). For 1.0 m MOSFETs
in saturation, the limit lies above 40 GHz.
III-57
The distributed channel model of section III.5.2 is essentially broadband,
so that the frequency limitation will be rather determined by the validity of
the extrinsic and adjacent equivalent circuit models, which will be shown in
chapter IV to be valid up to at least 20 GHz. Raskin, [III.24], has shown that
similar equivalent circuits did apply up to 40 GHz for SOI MOSFETs.
The frequency limit of validity in the case of the multiple chunks model of
section III.5.3 depends essentially on the number of channel partitions, N. The
worst-case situation has been identied in section III.5.3 as the zero drain-bias
condition, allowing to evaluate the validity of the multiple chunks model by
comparison with the distributed channel model. The multiple chunks model
will be valid as long as a single channel section is properly approximated by
the discrete equivalent circuit. This constraint can be expressed as :
L
N

Cf
< 1 (III.180)
where
Cf
is given by equation (III.146). Equation (III.180) shows that 3
sections are sucient to describe 1.0 m SOI MOSFETs fabricated at the
UCL up to 40 GHz.
III.8 Conclusion
Contributions of several authors were gathered in this chapter to produce a
state-of-the-art model for the SOI MOSFET operating at microwave frequen-
cies. The conventional charge-sheet model provided the framework onto which
short-channel eects, dynamic interface states and distributed channel eects
were grafted. Unique features of the present work are :
1. The comprehensive treatment of non-quasi-static eects : The introduc-
tion of multiple channel sections in the large-signal current and charge
model; The formulation of a small-signal distributed channel model at
V
DS
= 0, and particularly its use to evaluate the number of discrete
sections required to properly account for NQS eects.
2. The elaborate substrate model providing the adequate environment to the
back-gate : Resistive coupling to the wafer back-plane at DC, capacitive
coupling to the diusions at microwave frequencies.
3. The formulation of the alternative charge model. Its topology reveals
the structure of the underlying charge equations. This should enhance
the accuracy of numerically evaluated derivatives.
4. The combination of the unied inversion charge model from I n`guez, [III.10]
with the modelling approach proposed by Veeraraghavan in [III.15] for
the short-channel eects and particularly the channel length modulation.
5. The introduction of the interface charges as state-variables controlled by
specic time-constants. This was necessary to allow a unied treatment
of both DC and high-frequency responses, particularly in sub-threshold
operation.
III-58
REFERENCES
Frozen interface charge
Dynamic interface charge
0 0.5 1 1.5 2 2.5 3
0
100
200
300
400
500
1
2
3
V
DS
_
V
G
Di
1
_
V
Gf
_
V
-0.5 0 0.5 1 1.5

0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0.18
V
Gf
_
V
C
G
_
pF
V
DS
= 0.0
Figure III.23: Inuence of the interface charge on the output conductance G
Di
and on the total gate capacitance C
G
=
dQ
Gf
dV
Gf
.
The models developed here are compact, in the sense that they use a limited
number of empirical parameters in addition to the technological data. This
was achieved by basing all developments on thorough insight in the underlying
physical phenomena. A second important characteristic of the models is that
the predicted curves are continuous and innitely derivable over the whole bias
range.
The models described in this chapter have been successfully tested on SOI
MOSFETs fabricated mainly at the UCL with channel-lengths ranging from
1.5 m to 0.5 m. Detailled comparisons of predicted and measured character-
istics indicating the validity of the various models are presented in chapter IV.
References
[III.1] D. Flandre, Etude de Faisabilite dune technologie CMOS sur Isolant
(SOI) dans le Domaine des Circuits Digitaux. PhD thesis, Universite
catholique de Louvain, Laboratoire de Microelectronique, 1990.
[III.2] J.-P. Colinge, Silicon-on-Insulator Technology : Materials to VLSI.
Boston: Kluwer Academic Publ., 1991.
[III.3] Y. P. Tsividis and P. Suyama, MOSFET modeling for analog cir-
cuit CAD : Problems and prospects, IEEE J. of Solid-State Circuits,
vol. 29, pp. 210216, Mar. 1994.
III-59
[III.4] B. Agrawal, V. K. De, J. M. Pimpbley, and J. D. Meindl, Short
channel models and scaling limits of SOI and bulk MOSFETs, IEEE
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[III.5] J. R. Brews, A charge-sheet model of the MOSFET, Solid State
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[III.6] Y. P. Tsividis, Operation and Modelling of the MOS Transistor. New
York: Mc Graw-Hill, 1987.
[III.7] C. Mallikarjun and K. N. Bhat, Numerical and charge sheet mod-
els for thin-lm SOI MOSFETs, IEEE Trans. on Electron Devices,
vol. 37, pp. 20392051, Sept. 1990.
[III.8] A. Ortiz-Conde, F. J. Garcia-Sanchez, P. E. Schmidt, and A. SaNeto,
The foundation of a charge-sheet model for the thin-lm MOSFET,
Solid State Electronics, vol. 31, no. 10, pp. 14971500, 1988.
[III.9] L. F. Ferreira, not accepted yet. PhD thesis, Universite catholique de
Louvain, 1998.
[III.10] B. I n`guez, L. F. Ferreira, B. Gentinne, and D. Flandre, A physically-
based C
-continuous fully-depleted SOI MOSFET model for analog

applications, IEEE Trans. on Electron Devices, vol. 43, pp. 568575,
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[III.11] C.-K. Park, C.-Y. Lee, K. Lee, B.-J. Moon, Y. H. Byun, and
M. Shur, A unied current-voltage model for long-channel nMOS-
FETs, IEEE Trans. on Electron Devices, vol. 38, pp. 399406, Feb.
1991.
[III.12] H.-K. Lim and J. G. Fossum, Threshold voltage of thin-lm silicon-
on-insulator (SOI) MOSFETs, IEEE Trans. on Electron Devices,
vol. 30, pp. 12441251, Oct. 1983.
[III.13] C. Mallikarjun and K. N. Bhat, Analytical expressions for subthresh-
old charges and currents in thin-lm SOI MOSFETs, IEE Electronics
Letters, vol. 27, pp. 431433, Feb. 1991.
[III.14] T. L. Tewksbury and H.-S. Lee, Characterization, modelling and min-
imization of transient threshold voltage shifts in MOSFETs, IEEE
J. of Solid-State Circuits, vol. 29, pp. 239252, Mar. 1994.
[III.15] S. Veeraraghavan and J. G. Fossum, A physical short-channel model
for the thin-lm SOI MOSFET applicable to device and circuit CAD,
IEEE Trans. on Electron Devices, vol. 35, pp. 18661875, Nov. 1988.
[III.16] C. G. Sodini, P.-K. Ko, and J. L. Moll, The eect of high elds
on MOS device and circuit performance, IEEE Trans. on Electron
III-60
REFERENCES
[III.17] M. El-Banna and M. A. El-Nokali, A simple analytical model for
hot-carrier MOSFETs, IEEE Trans. on Electron Devices, vol. 36,
pp. 979986, May 1989.
[III.18] H.-C. Chow, W.-S. Feng, and J. B. Kuo, An improved analytical
short-channel MOSFET model valid in all regions of operation for
analog/digital circuit simulation, IEEE Trans. on Computer Aided
Design, vol. 11, pp. 15221528, Dec. 1992.
[III.19] C. C. McAndrew, B. K. Bhattacharya, and O. Wing, A single-piece
C
-continuous MOSFET model including subthreshold conduction,

IEEE Trans. on Electron Devices, vol. 12, pp. 565567, Oct. 1991.
[III.20] B. I n`guez, Analytical MOSFET Modelling with an Innite Order of
Continuity. PhD thesis, Universitat de les Iles Balears, June 1996.
[III.21] J. G. Fossum, H. Jeong, and V. S., Signicance of the channel-charge
partition in the transient MOSFET model, IEEE Trans. on Electron
[III.22] D. E. Ward and R. W. Dutton, A charge-oriented model for MOS
transistor capacitances, IEEE J. of Solid-State Circuits, vol. 13,
pp. 703707, Oct. 1978.
[III.23] M. Bagheri and Y. P. Tsividis, A small-signal DC-to-high-frequency
nonquasistatic model for the four-termminal MOSFET valid in all
regions of operation, IEEE Trans. on Electron Devices, vol. 32,
pp. 23832391, Nov. 1985.
[III.24] J.-P. Raskin, Modeling, Characterization and Optimization of MOS-
[III.25] J. Chen, Development of Metallization Processes on Thin-Film SOI
for Low-Voltage, Low-Power Microwave and High-Temperature Appli-
cations. PhD thesis, Universite catholique de Louvain, Dec. 1997.
[III.26] C. H. Wang, Identication and measurement of scaling-dependent
parasitic capacitances of small-geometry MOSFETs, IEEE Trans.
on Electron Devices, vol. 43, pp. 965972, June 1996.
[III.27] R. Shrivastava and K. Fitzpatrick, A simple model for the overlap
capacitance of a VLSI MOS device, IEEE Trans. on Electron Devices,
vol. 29, pp. 18701875, Dec. 1983.
[III.28] C.-L. Huang, J. V. Faricelli, D. A. Antoniadis, N. A. Khalil, and R. A.
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963, June 1996.
III-61
[III.29] J.-P. Raskin, A. Viviani, D. Flandre, and J.-P. Colinge, Substrate
crosstalk reduction using SOI technology, IEEE Trans. on Electron
[III.30] C. Raynaux, Technological parameters of FD MOSFETs fabricated
at LETI for the SPACE ESPRIT project. Private Communication.
III-62
Chapter IV
Extraction of
SOI MOSFET
model parameters
IV.1 Introduction
The models developed in chapter III require in total about 60 parameters. To
render these models operational that is : capable of accurate predictions ,
it is necessary to determine the proper value of each parameter. The majority
of the model parameters is related to technological or physical characteristics,
and can hence be readily estimated on the basis of available technological or
physical data. This data is however not always complete or can be subject to
signicant uctuations, so that there is still a need for extraction techniques
working on the measured characteristics of individual devices. Furthermore,
a few model parameters are purely empirical, and can only be determined by
comparing model responses with measurements.
The purpose of this chapter is to provide evidence of the validity of the
models proposed in chapter III by confronting the predicted responses with
measurements. The main objective of the present work being the development
of bias-dependent high-frequency models for the SOI MOSFET, this chapter
will focus on the exploitation of high-frequency scattering parameters measure-
ments. The core of the extraction procedure developed in the following pages
is the reliable identication of equivalent circuit parameters in agreement with
the physical interpretations given in chapter III. The most striking achieve-
ment is probably the direct extraction of a mobility versus normal eld curve
from broadband high-frequency measurements, which corresponds very well to
IV-1
Extraction of SOI MOSFET model parameters
data published in the literature see section IV.5.3.
In comparison with the wealth of parameters traditionally used in SPICE
models, the number of parameters required for the unied analytical current
and charge model of chapter III seems quite reasonable. It is however su-
ciently high to prohibit the extraction of parameters values in a single global
optimisation. The extraction strategy developed below is rather a step-by-step
procedure where the complexity of the model builds progressively up. At rst
a simplied three-terminal model of the MOSFET is used. Starting with the
determination of adjacent and extrinsic parasitic circuit elements, the extrac-
tion proceeds inward with the identication of the series parasitics. Then the
complete four-terminal model is introduced and the substrate coupling param-
eters are identied. It will be shown that the approximations involved in the
three-terminal model do not aect the extracted values for the series parasitic
elements, which thus may condently be used in the four-terminal model. Fi-
nally the internal parameters of the analytical current and charge model are
identied : inversion-charge parameters, transport model and saturation model
parameters.
In order to extract each parameter with a minimal uncertainty, care must
be taken to select the biasing conditions at which the S-parameters are the
most sensitive to the parameter in question. The optimal conditions for the
extraction of the shunt parasitic circuit elements will be shown to be the reverse
bias, where the inversion channel is suppressed. For the series parasitic circuit
elements, the optimal condition is saturation. For the extraction of internal
parameters of the analytical current and charge model optimal bias ranges will
also be identied.
The detailed organisation of the present chapter is the following :
At rst, substrate resistivity is identied on the basis of transmission
line measurements in section IV.2. Substrate resistivity is indeed needed
to estimate the conductances associated with parasitic substrate capaci-
tances.
Section IV.3 deals with the three-terminal small-signal equivalent circuit
of the SOI MOSFET. Reliable optimiser-driven extraction of all equiva-
lent circuit parameters is demonstrated, and an original direct extraction
scheme is introduced allowing to determine all series extrinsic elements
in the presence of non-quasi-static eects.
In section IV.4, the simplied three-terminal model is expanded into
a four-terminal small-signal equivalent circuit, accounting for substrate
coupling eects. Optimisation is used to extract parameters values for
the 4-terminal circuit. Results are compared with those of the previous
section.
Section IV.5 focuses on the extraction of the inversion charge and car-
rier transport parameters for the intrinsic MOSFET model. Using the
distributed channel model, broadband two-port scattering parameters
measurements are reduced to one equivalent DC capacitance and one
equivalent DC conductance. To illustrate the validity of the approach, a
IV-2
IV.2 Substrate resistivity
mobility versus normal electric eld curve is reconstructed from measured
data .
The whole extraction procedure is nalised in section IV.6, by the iden-
tication of saturation parameters for the intrinsic current and charge
model of the SOI MOSFET.
IV.2 Substrate resistivity
On silicon substrates the resistivity is essentially controlled by adjusting the
doping level. On a p-type substrate, a low resistivity of 20 cm is achieved with
a doping level on the order of 7.0 10
14
cm
3
, while a resistivity higher than 10
k cm implies an impurity concentration below 10
12
cm
3
. Such low impurity
levels are easily perturbed by a small contamination so that it is dicult to en-
sure a precise or even uniform resistivity. The signicant inuence of substrate
resistivity on the parasitic device capacitance in the case of high-resistivity
SOI wafers urged the need to develop adequate characterisation techniques. In
particular, the dopant concentration may also vary vertically within the wafer
substrate, so that an adequate characterisation technique should operate from
the top of the wafer not the back-side in a conguration which is similar
to the coplanar conguration of the basic MOSFET cell.
The scattering parameter calibration procedure described earlier yields as
by-products the transmission line characteristics of a coplanar waveguide fabri-
cated in the immediate vicinity of the transistors on the SOI wafer. The signi-
cant inuence of the substrate resistivity on the transmission line characteristics
suggests several means of extracting substrate resistivity values : Either using
an electro-magnetic eld simulator, or an adequate transmission line model,
the resistivity of the substrate is adjusted until a satisfactory approximation
is obtained for the evolution of the propagation constant and the character-
istic impedance Z
c
in the measurement band. Another, more straightforward
approach, is to deduce the resistivity from the time-constants governing the
frequency evolution of the distributed admittance for the waveguide. Identi-
cation of these time-constants relies on the extraction of an equivalent circuit
for Y
CPW
as described in appendix A. It is shown in section A.3.1 that the
substrate resistivity is related to the circuit parameters by :
subs
=
C
subs
G
subs

Si
(IV.1)
The estimation of the substrate resistivity using equation IV.1 has been found
to agree well with the values obtained by tting the predictions from the model
of Huynen, [IV.1], to the measured characteristics.
IV.3 Three-terminal MOSFET model
GaAs MESFETs or HEMTs are usually presented as three-terminal devices.
They are indeed fabricated on a semi-insulating substrate which is at least
IV-3
three orders of magnitude thicker than the depletion zone controlled by the
gate, so that the inuence of a potential applied to the wafer back-plane is truly
negligible. In the case of the SOI MOSFET, a low-frequency excitation applied
to the back of the wafer is transmitted integrally by the conductive silicon
substrate to the bottom interface of the buried oxide the back gate. The
SOI MOSFET then behaves as a four-terminal device, with a non-negligible
control of the back gate on the small-signal performances as can be inferred
from the device equations :
C
GbSi
C
GfSi
=
C
GbDi
C
GfDi
=
G
mbi
G
m
=
f
1
t
of
t
ob
(IV.2)
The ratio t
of
/t
ob
is typically 0.075 for the UCL technology, and can go down
to 0.011 in advanced processes as for LETI.
Drain
Front Gate
Source
C
GfDe
C
GfSe
R
Gfe
R
De
R
Se
Y
Gfa
Y
Da
Y
GfDa
C
GfDi
C
GfSi
R
GfSi
R
GfDi
C
DSe
G
Di
L
Di
Z
Da
Z
Gfa
G
m
e
m
1+
m
Figure IV.1: The 3-terminal SOI MOSFET model.
At microwave frequencies, above the dielectric relaxation frequencies, the
silicon substrate behaves rather as lossy dielectric material, so that the back
gate potential is no longer controlled by the wafer back-plane but rather capac-
itively by the source and drain diusions. The SOI MOSFET then behaves as
a three terminal device, and the common source small signal equivalent circuit
constructed from gures III.11, III.18 and III.20 can be simplied accordingly.
All intrinsic circuit elements related to the back-gate are ignored, and the sub-
strate coupling model is reduced to a single admittance connected between
the source and drain terminals. The resulting circuit topology is shown in
gure IV.1. These simplications modify of course the physical interpretation
IV-4
of some of the remaining equivalent circuit elements, but in a marginal pro-
portion. For example, in depletion at V
DS
= 0, the suppression of C
GfGbi
is
absorbed by an increase of C
GfSe
. In strong inversion at V
DS
= 0, C
GfGbi
0
so that its suppression from the equivalent circuit has no inuence at all. In
saturation, C
GbDi
is known to be very small so that its suppression has no ef-
fect. The transconductance G
mbi
is however maximal, and its removal from the
equivalent circuit will be compensated by an increase in G
Di
. Other elements
such as G
m
, C
GfSi
and C
GfDi
are almost not inuenced by the simplications.
It will be shown in the next sections that the simplied circuit still allows to
perform accurate extraction of technological parameters such as the channel
length and the series resistances.
The equivalent circuit shown in gure IV.1 relies on the implicit assumption
that the gate-line propagation eects are properly accounted for by the lumped
model. This imposes a limit on the active zone width W depending on the gate
resistivity and capacitance. Below this limit, simple scaling rules apply which
can be used to distinguish between the contributions of the various circuit
elements. The equivalent circuit topology of gure IV.1 can be translated into
the following matricial equation :
_
Y
1
= Z
+Y
1
(IV.3)
where Y
is the admittance matrix obtained directly from the measured S-

parameters. Y
is the admittance matrix comprising the shunt adjacent el-

ements. It does not depend on the active zone width W, and its expression
is :
Y

_
Y
Gfa
+ Y
GfDa
Y
GfDa
Y
GfDa
Y
Da
+ Y
GfDa
_
(IV.4)
As indicated in section III.6.4, Y
Gfa
and Y
Da
model mainly the shunt admit-
tance of the metal taper sections at the input and output of the MOSFET
structure. The corresponding equivalent circuit topology is inspired from the
developments of appendix A. It is shown in gure IV.2.
G
X3a C
X3a
C
X2a
C
X1a
Figure IV.2: Equivalent circuit for the adjacent admittances Y
Gfa
and Y
Da
.
The matrix Z
groups the contributions of all series elements. The scaling

IV-5
rules detailed below have been introduced in section III.6 :
Z

_
Z
Gfa
+ R
Se
+ R
Gfe
R
Se
R
Se
Z
Da
+ R
Se
+ R
De
_
=
_
Z
Gfa
+ R
Gf0e
0
0 Z
Da
_
+ W
_
R
Gfe
0
0 0
_
+
1
W
_
R
Se
R
Se
R
Se
R
Se
+ R
De
_
(IV.5)
The impedances Z
Gfa
and Z
Da
account for the series inductance and re-
sistance of the input and output taper sections. It is shown in appendix A
that these parameters may vary signicantly with frequency, particularly in
the case of a low resistivity substrate at frequencies around 1.0 GHz. In this
case the equivalent circuit of gure IV.3 is recommended. On a high-resistivity
substrate, this circuit may be simplied to a series inductance and resistance
in the band between the dielectric relaxation frequencies and the onset of the
skin eect. The absence of a series inductance in the source is a result of the
specic design of the MOSFET structure, as explained in section III.6.3.
L
X1a
L
X2a
L
X3a
R
X1a
R
X2a
R
X3a
Figure IV.3: Equivalent circuit for the adjacent impedances Z
Gfa
and Z
Da
.
The matrix Y
combines the shunt intrinsic and extrinsic elements, which

are all directly proportional to the active zone width, so that may write :
Y
= W Y
(IV.6a)
The general expressions for the elements of Y
are :
Y
(1, 1)
=
_
C
GfSe
+ C
GfDe
_
+
C
GfSi
1 +
GfSi
+
C
GfDi
1 +
GfDi
(IV.6b)
Y
(1, 2)
= C
GfDe

C
GfDi
1 +
GfDi
(IV.6c)
Y
(2, 1)
= C
GfDe
+
G
m
exp(
m
)
1 +
m
GfDi
1 +
GfDi
(IV.6d)
Y
(2, 2)
= C
GfDe
+
G
Di
1 +
m
+
C
GfDi
1 +
GfDi
(IV.6e)
(IV.6f)
These are non-quasi-static expressions which constitute a valid model for all
biasing conditions. Simplied circuit topologies may be considered for specic
bias ranges. In depletion, when V
DS
= 0 and V
Gf
V
Thf
, all intrinsic elements
index i vanish. The resulting Y
is purely capacitive and depends solely

IV-6
on the shunt extrinsic elements index e. In saturation, when V
Gf

V
Thf
and V
DS
> (V
Gf
V
Thf
), the gate to drain capacitance C
GfDi
becomes
negligible. Using equations (III.140) all time-constants can be related to a
single parameter :
m
=
2
15

0
(IV.7)
GfSi
=
2
15

0
(IV.8)
GfDi
=
1
10

0
(IV.9)
IV.3.1 Shunt parasitic elements
The denomination shunt parasitics groups all adjacent, index a, and extrin-
sic, indexe, elements which are connected in parallel with the intrinsic circuit.
As indicated in the previous section, the intrinsic elements tend to vanish when
the device is reverse-biased. This biasing condition is thus the most favourable
for the extraction of the shunt parasitics which are the sole parameters inuenc-
ing the device response. Accordingly, the determination of the shunt parasitics
will be based on S-parameters measurements of reverse-biased MOSFETs.
The general purpose equivalent circuit topology of gure IV.1 is adapted
to the particular biasing condition by removing all intrinsic elements, so that
matrix Y
becomes purely capacitive and depends solely on the extrinsic capac-

itances. The simplied equivalent circuit however still contains some redundant
elements which can not be distinguished from each other on the sole basis of
the frequency evolution of the device response. The adjacent shunt elements
exhibit an inuence on the scattering parameters which is very closely similar
to the inuence of the extrinsic capacitances. Relying on the scaling rules it
should however be possible to make the distinction : The extrinsic shunt ele-
ments have been shown to scale proportionally to the active zone width, W,
while the adjacent circuit elements where dened to be indepedent of W.
Raskin showed in his thesis [IV.2] that the parasitic adjacent and extrinsic
capacitances can be identied by performing a linear regression on the measured
susceptance matrix of depleted devices of varying size. His demonstration does
however not give any insight in the possibility to apply a similar procedure
to the measured conductance matrix in order to obtain the real part of the
adjacent admittances. Using some simple equations and matrix algebra, it is
possible to show that a linear regression scheme will only work properly for
the capacitances, and that for the conductances a cubic regression would be
necessary. Equation (IV.10) illustrates the dependencies on W.
Y
(W) = Y
+Y
(W) (IV.10)
where Y
Z
1
. The identication of Y
rests on the following approxima-

tion :
lim
W0
Y
(W) 0 (IV.11)
IV-7
The above expression is approximate because it neglects the inuence of a direct
capacitive coupling between the metal tapers at the input and the output of the
MOSFET structure. This coupling is truly negligible provided the active zone
width is sucient. It will however increase when W is reduced and eventually
become a dominant eect when W = 0. The approximation of equation (IV.11)
nevertheless produces meaningfull results in the case of a regression based on
suciently wide devices.
The admittance matrix Y
associated to the active zone can be expanded

as follows :
Y
=
_
Z
+Y
1
1
= Y
_
I + Re(Z
)
. .
A
+ Im(Z
)
. .
B
1
(IV.12)
Z
and Y
were dened above. Y
is known to be directly proportional to

W while the dependency of Z
is slightly more involved as can be seen in

equation (IV.5). Using simple matricial algebra, the real and imaginary part of
the inverse matrix can be computed. Expression (IV.13) implicitly accounts for
the fact that the matrices A and B are both symmetric, being themselves the
product of symmetric matrices. This expression shows that in all generality, the
Y
(i, j )
are rational functions of W. Both their numerator and the denominator
are polynomials of order higher than six.
Y
= Y
_
A B
_
AA+BB
1
(IV.13)
Important simplications are nevertheless possible. Matrix A can be expanded
as
_
I
2
L
_
and matrix B as ( R
). In the case of the MOSFETs

considered here, the biggest LC product inside A is on the order of 10
24
,
while for B the highest RC product is about 10
12
. Neglecting the contri-
butions of the
_
2
LC
_
- and (RC)-terms with respect 1.0 allows to simplify
equation (IV.13) to :
Y
_
I B
(IV.14)
This expression clearly shows that the imaginary part of Y
is very closely
proportional to W while the real part behaves more like a cubic polynomial in
W. Expression (IV.14) is accurate within 5.0 % up to 20.0 GHz.
Performing a brute force regression in W for the conductances would thus
require at least four samples MOSFETs with dierent active zone widths.
This solution is rather unattractive as it doubles the work load compared to the
extraction of the susceptances. Further more, the extraction of the adjacent
admittances over some frequency band would require a total of 24 N
freq
real coecients, while the equivalent circuit description uses 22 parameters,
independently of the number of measured frequency points, N
freq
. For these
reasons, an optimiser-based extraction method was found more appealing.
In order to reduce the number of potential optimisation parameters, some
constraints will be imposed on the general circuit topology described in sec-
tion IV.3; Particularly on the adjacent immitances, as it is known that they
IV-8
account mainly for the characteristics of the input and output metal tapers
which are very closely related to the characteristics of the coplanar waveguide
described in appendix A. The constraint on the adjacent immitances, Y
Gfa
and Y
Da
is introduced by expressing explicitly their dependence upon the dis-
tributed immitances of the CPW, as in equation (IV.15). As the metal tapers
dier from the standard CPW section, some degrees of freedom are added :
additional shunt capacitances are added at the gate and drain terminal, C
Gf0a
and C
D0a
; the substrate conductance G
subs
and the buried oxide capacitance
C
box
from the CPW model are allowed to depart from the values extracted
from the CPW characteristics.
Y
Xa
= C
X0a
+ d
Xa
Y
CPW
(IV.15)
Z
Xa
= d
Xa
Z
CPW
(IV.16)
The parameters d
Gfa
and d
Da
must be considered as eective lengths which
model the specic geometrical dependency of the taper characteristics. They
are used as optimisation parameters and their initial value is set equal to the
physical length of the tapers measured along their axis. The adjacent admit-
tance Y
GfDa
corresponds to a marginal eect the stray capacitance between
the gate and drain lines outside of the active zone so that a simple model
will suce :
Y
GfDa
= C
GfDa
(IV.17)
The extraction is performed by tting

S
(i, j )
, the equivalent circuit response,
to the measurements, S
(i, j )
, for the active zone widths in W
min
, . . . , W
max
and for the set of pulsations

min
, . . . ,
max
. The error is computed in
a quadratic fashion ensuring a convergence in the mean.
min
P
E(T) (IV.18a)
E

W
k
W
l

i, j {1, 2}

S
(i, j )
(T, W
k
,
l
) S
(i, j )
(W
k
,
l
)
2
(IV.18b)
The parameter space for the optimisation is :
T
_
p
_
C
GfSe
, C
GfDe
, C
DSe
, d
Gfa
, d
Da
, C
Gf0a
, C
D0a
, C
GfDa
,
G
subs
, C
box
, R
Gf0e
, R
Gfe
, R
De
, R
Se
R
14
[
0.1 p
(0)
p 10 p
(0)
_
(IV.18c)
This extraction scheme was applied to a set of three n-channel MOSFETs
with the following active zone widths : 6.0 m, 12.0 m and 24 m. All three
MOSFETs had a nominal gate width of 1.0 m, and consisted of 10 basic
cells connected in parallel. These transistors were located close together on the
same wafer. Twenty frequency points were used, with a higher density below
IV-9
5.0 GHz. Figure IV.4 compares the measured scattering parameters with the
curves computed using the extracted parameters.
Table IV.1 summarises the optimisation results, mentionning initial and
nal values for the optimisation parameters. The values of the xed parameters
are mentioned in the second part of the table. The residual error was R =
8.5 10
3
. In conjunction with the sensitivities listed in table IV.1 it allows to
identify the parameters which have been reliably extracted. All parameters
which have a sensitivity above 10
1
suer an uncertainty smaller than 10.0 %
on their nal value. This means that in particular, all extracted adjacent
and extrinsic parameters are known with a reasonable accuracy. The other
parameters will need to be extracted dierently.
Parameter Final Value Initial Value Units Sensitivity
C
GfDa
8.248 1.0 fF 2.0 10
+2
C
D0a
0.000 1.0 fF 1.0 10
+2
C
Gf0a
25.672 5.0 fF 9.0 10
+1
C
GfDe
2.5289 2.600 nF/m 2.0
C
GfSe
2.5723 2.600 nF/m 1.0
d
Gfa
64.26 60.0 m 2.0 10
1
d
Da
63.54 60.0 m 2.0 10
1
C
DSe
0.7834 0.200 nF/m 1.5 10
1
G
subs
5.5335 1.058 /m 8.0 10
2
R
Gfe
0.5665 0.4 M/m 6.0 10
2
C
box
2.4733 0.7662 nF/m 5.0 10
3
R
De
0.1208 0.15 m m 4.0 10
3
R
Se
0.0504 0.15 m m 1.6 10
3
R
Gf0e
0.0005 2.0 1.5 10
4
C
air
0.0241 nF/m 10
C
subs
0.1625 nF/m 10
L
met
1 390.15 nH/m 3.0 10
1
L
met
2 40.888 nH/m 2.0 10
3
R
met
1 12.056 k/m 6.0 10
4
R
met
2 1.935 k/m 5.0 10
4
L
met
3 487.59 nH/m 4.0 10
5
R
met
3 3.080 k/m 1.0 10
5
Table IV.1: Detailed results of the extraction in depletion at V
Gf
= 1.0 V
and V
DS
= 0.0 V, using the 3-terminal model.
IV-10
Re(S
11
)
0 2 4 6 8 10 12 14 16 18 20
GHz
6.0
12.0
24.0
W
m
0.75
0.25
1.0
0.5
0
0.25
0.5
0.75
1.0
Re(S
22
)
0 2 4 6 8 10 12 14 16 18 20
GHz
6.0
12.0
24.0
W
m
1.0
0.25
0
0.25
0.5
0.75
1.0
0.5
0.75
Im(S
22
)
0 2 4 6 8 10 12 14 16 18 20
GHz
6.0
12.0
24.0
W
m
1.0
0.25
0.5
0.75
0
0.25
0.5
0.75
1.0
Im(S
21
)
0 2 4 6 8 10 12 14 16 18 20
GHz
6.0
12.0
24.0
W
m
1.0
0.25
0
0.25
0.5
0.75
1.0
0.5
0.75
Im(S
11
)
0 2 4 6 8 10 12 14 16 18 20
GHz
6.0
12.0
24.0
W
m
1.0
0.25
0
0.25
0.5
0.75
1.0
0.5
0.75
Re(S
21
)
0 2 4 6 8 10 12 14 16 18 20
GHz
6.0
12.0
24.0
W
m
1.0
0.25
0
0.25
0.5
0.75
1.0
0.5
0.75
Figure IV.4: Comparison of the measured (dotted lines with rings) and the
predicted (straight lines with crosses) S-parameters after extraction of the 3-
terminal circuit model at V Gf = 1.0V. The devices are 10 (W/1.0 m)
nMOSFETs.
IV-11
IV.3.2 Channel length
L
L
ovlp[S]
L
ovlp[D]
L
poly
Figure IV.5: Cross-section of the SOI MOSFET showing the channel- and
overlap-lengths.
In conventional CMOS technology the channel length is determined by
the width of polysilicon gate strip and the amount of lateral diusion of the
source and drain dopants below the gate oxide. In short channel MOSFETs
the amount of lateral diusion is critical, and special care is taken to reduce
it, [IV.3]. The channel length has indeed a major inuence on the device
performance, and accurate determination of its value is required. Several chan-
nel length extraction techniques have been published. The rst technique
to appear in the literature was based on the channel-length dependency of
I
DS
, [IV.4, IV.5, IV.6]. Garcia Sanchez, [IV.7], and Guo, [IV.8] pointed out
that these I
DS
-based methods are inadequate for the extraction of the chan-
nel length in sub-micron devices, as they use simplied current models which
do not account for the normal eld dependency and the velocity saturation
of the inversion channel mobility. Fikry, [IV.9], tried to address these prob-
lems. But the fundamental limitation of the I
DS
-based methods still remains,
namely, they are not able to determine the absolute value of the channel length
L directly.
L = L
poly
L
ovlp[S]
L
ovlp[D]
= L
poly
L
ovlp
(IV.19)
The I
DS
-based methods determine the total overlap length L
ovlp
of the diu-
sions with respect to the polysilicon strip width L
poly
which is assumed to be
IV-12
equal to the corresponding layout dimension. However the lithography of the
gate polysilicon is a critical process step in the case of short-channel devices, as
the gate width is quite close to the smallest manufacturable line-width, so that
discrepancies may be expected between L
poly
and its nominal value. These
discrepancies will nally result in errors on the extracted channel length.
The method advocated by Garcia Sanchez, [IV.7], and Guo, [IV.8] is based
on the measurement of the intrinsic gate capacitance and allows a direct ex-
traction of the channel-length of bulk MOSFETs. It is applied here to the
SOI MOSFET. It has been shown in section III.35 that in strong inversion,
when V
Gf
> V
Thf
, the inversion charge density Q
nf
can be approximated by
C
of
(V
Gf
V
Thf
). This allows to write simple expressions for the capaci-
tors contributing to the intrinsic capacitance of the front gate in inversion at
V
DS
= 0 :
C
GfSi
C
GfDi
N
cell
W L
C
of
2
f
(IV.20)
C
GfGbi
0 (IV.21)
These expressions show that the channel length can be deduced from the
measured intrinsic gate capacitance if the oxide capacitance per unit-width
is known.
L =
f
C
GfSi
+ C
GfDi
N
cell
W C
of
for V
Gf
V
Thf
and V
DS
= 0 (IV.22)
In order to obtain the intrinsic gate capacitance, accurate identication
of the extrinsic gate capacitances is of primary importance. The bias point
at which the extrinsic capacitances are extracted must be carefully selected.
For bulk MOSFETs there is a consensus in the literature considering that
the extraction of the extrinsic gate capacitances dened as the sum of c
top
,
c
latrl
and c
ovlp
, see section III.6.2 should be performed in accumulation for
an enhancement-mode device. The accumulation layer imposes a nearly xed
surface potential underneath the gate oxide, so that the fringing capacitances
c
inner
are frozen in a similar way as in inversion. Furthermore, the accumula-
tion layer is isolated from the source and drain diusions by the reverse-biased
junctions, so that its capacitance to the gate charges exclusively through the
bulk. The gate-source and gate-drain capacitances are then exactly equal to
the extrinsic gate capacitances.
For SOI MOSFETs at high frequencies, the picture is somewhat dierent.
By applying a suciently strong reverse-bias on the gate, it is indeed possible
to create a quasi-neutral region and eventually an accumulation layer. The
carriers in the accumulation layer can however only be supplied by the leakage
current of the reverse-biased drain and source junctions, so that applying a
microwave signal on the gate will cause the redistribution of a constant charge
inside the silicon lm and induce capacitive currents in the source, drain and
back-gate. Furthermore, the back-gate behaves at microwave frequencies rather
as a oating node controlled capacitively by the source and drain than as a
grounded node. It is thus not possible to isolate the contribution of C
GfGbi
from
IV-13
those of the extrinsic gate capacitances, C
GfSe
and C
GfDe
, in the framework
of the 3-terminal model. As C
GfGbi
is zero in strong inversion and non-zero
below threshold, an error will be induced on the extracted channel length. In
order to get the best possible estimate of the gate parasitics, the shunt extrinsic
elements are extracted at the reverse-bias corresponding to the minimum total
gate capacitance, typically around 1.0 V. The relative worst case error is
expected in this case to be lower as C
bf
/C
of
where :
1
C
bf
1
C
of
+
1
C
b
+
1
C
ob
(IV.23)
For the technology at the UCL, the upper bound for the error evaluates to 6.0
%. Due to the presence of the substrate capacitances in series with C
GfGbi
=
N
cell
W LC
bf
the actual error will be signicantly smaller.
To obtain C
GfSi
and C
GfDi
in strong inversion, the circuit of gure IV.1
is tted to measurements of MOSFET devices biased at 3.0 V. In order to
simplify the extraction process, R
GfSi
, R
GfDi
and L
Di
are set to zero. From the
strict point of view of the frequency behaviour of the circuit, R
GfSi
and R
GfDi
are redundant with respect to the extrinsic resistances. As the time-constants
model of Tsividis see equations (III.143) breaks down at V
DS
= 0, no
simple relationship is available to lift the indetermination. As a result, the
extracted values for R
Gfe
, R
Se
and R
De
will be aected by the NQS eects.
This is not important, as only C
GfSi
and C
GfDi
are of interest here.
A typical extraction is presented below. The extraction was performed si-
multaneously on three devices of varying W. This is not strictly necessary for
the extraction of C
GfSi
and C
GfDi
, but serves rather the purpose of validat-
ing the scaling rules. The adjacent elements and shunt extrinsic parameters
were determined according to the procedure described in section IV.3.1. Initial
values were computed from available technological data, assuming L = L
poly
.
min
P
E(T) (IV.24a)
E

W
k
W
l

i, j {1, 2}

S
(i, j )
(T, W
k
,
l
) S
(i, j )
(W
k
,
l
)
2
(IV.24b)
T
_
p
_
C
GfSi
, C
GfDi
, G
Di
, R
Gf0e
, R
Gfe
, R
De
, R
Se
R
7
[
0.1 p
(0)
p 10 p
(0)
_
(IV.24c)
Figure IV.6 shows the adequation between the modelled and measured re-
sponses after extraction. The residual error R was 6.03 10
3
. Sensitivity values
listed in table IV.2 show that C
GfSi
and C
GfDi
were reliably extracted. These
result correspond to a channel length L of 0.612 m for a nominal gate width
L
poly
of 1.0 m.
IV-14
Re(S
22
)
GHz
W
_
m
0 2 4 6 8 10 12 14 16 18 20
6.0
12.0
24.0
0
0.25
0.50
0.75
1.00
1.00
0.75
0.50
0.25
Im(S
22
)
GHz
W
_
m
0 2 4 6 8 10 12 14 16 18 20
6.0
12.0
24.0
0
0.25
0.50
0.75
1.00
1.00
0.75
0.50
0.25
Re(S
21
)
GHz
W
_
m
0 2 4 6 8 10 12 14 16 18 20
6.0
12.0
24.0
0
0.25
0.50
0.75
1.00
1.00
0.75
0.50
0.25
Im(S
21
)
GHz
W
_
m
0 2 4 6 8 10 12 14 16 18 20
6.0
12.0
24.0
0
0.25
0.50
0.75
1.00
1.00
0.75
0.50
0.25
Re(S
11
)
GHz
W
_
m
0 2 4 6 8 10 12 14 16 18 20
6.0
12.0
24.0
0
0.25
0.50
0.75
1.00
1.00
0.75
0.50
0.25
Im(S
11
)
GHz
W
_
m
0 2 4 6 8 10 12 14 16 18 20
6.0
12.0
24.0
0
0.25
0.50
0.75
1.00
1.00
0.75
0.50
0.25
terminal circuit model in inversion. The devices are 10 (W/1.0 m) nMOS-
FETs.
IV-15
G
Di
1.7669 1.0 k/m 8.0 10
1
C
GfSi
3.23647 4.5 nF/m 2.7 10
1
C
GfDi
3.2250 4.5 nF/m 2.7 10
1
R
Se
0.08810 0.0504 m m 2.0 10
2
R
Gfe
0.538716 0.5665 M/m 2.0 10
2
R
De
0.0521 0.1208 m m 7.5 10
3
R
Gf0e
0.00053 0.0005 5.0 10
7
Table IV.2: Detailed results of the extraction in strong inversion at V
Gf
= 3.0 V
and V
DS
IV.3.3 Series parasitic elements
This designation groups the extrinsic and adjacent elements connected in se-
ries with the intrinsic part of the equivalent circuit. It has been shown in
section IV.3.1 that, in depletion, the extraction of the series extrinsic elements
was not reliable, because of the insucient sensitivity of the device response
to these parameters. In inversion it is impossible to distinguish the inuence
of the intrinsic NQS resistances R
GfSi
and R
GfDi
from that of the extrinsic
resistances. This impossibility is well known in MESFET modelling, where
the cold-FET extraction method, [IV.10] is only able to determine the sum
(R
Se
+ R
De
) from S-parameters, and requires additional information to sepa-
rate R
Se
from R
De
.
In saturation, the MOSFET becomes non-reciprocal active so that
additional equations are available with respect to the case where V
DS
= 0.
This specic feature will be exploited in the following subsections to perform
the extraction of pure series resistances.
Optimiser-based extraction
The model used for the extraction of the series resistances is the non-quasi-
static equivalent circuit depicted in gure IV.1. The shunt adjacent and ex-
trinsic elements have been determined in section IV.3.1. The series adjacent
elements predicted on the basis of the distributed CPW impedance Z
CPW
and
the taper length extracted in section IV.3.1 will be used here in order to verify
the validity of the assertions concerning the device inductances : that the series
gate and drain inductances are due essentially to the input tapers and that the
series source inductance is negligible.
In order to limit the number of optimisation variables, the expressions link-
ing the NQS intrinsic elements R
GfSi
, R
GfDi
, L
Di
and
m
to a single time-
constant
0
, (IV.7) (IV.9), are used explicitly, so that
0
is the only NQS
optimisation parameter.
IV-16
min
P
E(T) (IV.25a)
E

W
k
W
l

i, j {1, 2}

S
(i, j )
(T, W
k
,
l
) S
(i, j )
(W
k
,
l
)
2
(IV.25b)
T
_
p
_
C
GfSi
, C
GfDi
, G
m
, G
Di
,
0
, R
Gf0e
, R
Gfe
, R
De
, R
Se
R
9
[
0.1 p
(0)
p 10 p
(0)
_
(IV.25c)
Extractions at several bias points in saturation were performed in order to
verify the bias-independancy of the extracted series resistances. All extractions
were operated on three devices simultaneously, allowing to check the validity
of the scaling rules. Figure IV.7 shows the good match obtained between
the modelled and measured scattering parameters for the three MOSFETs at
V
GfS
= 2.0 V and V
DS
= 3.0 V. The residual error R was 2.5 10
2
. A second
extraction was performed on the same devices at V
GfS
= 1.0 V and V
DS
= 2.0 V,
with R = 2.6 10
2
. Table IV.3 summarises the extraction results.
Bias Pt 1 Bias Pt 2
G
m
0.6092 0.5060 0.671 k/m 2.0
C
GfSi
4.8049 4.0295 4.0 nF/m 2.0 10
1
G
Di
71.08 51.974 60.0 /m 6.0 10
2
0
13.49 15.72 6.0 ps 1.0 10
2
R
Gfe
0.5142 0.4942 0.5665 M/m 3.5 10
2
R
Se
0.1151 0.1154 0.0881 m m 1.6 10
2
R
De
0.2929 0.3077 0.0521 m m 1.3 10
2
C
GfDi
0.2438 0.1550 0.4 nF/m 2.0 10
3
R
Gf0e
0.00053 0.00053 0.00053 4.0 10
7
Table IV.3: Detailed results of the extraction in saturation using the 3-terminal
model. Bias point no. 1 is at V
GfS
= 2.0 V and V
DS
= 3.0 V. Bias point no. 2
is at V
GfS
= 1.0 V and V
DS
= 2.0 V. Sensitivities were evaluated for bias point
no. 1.
Comparing the results of the two bias points, one may see that
0
varies
by more than 15.0 %, while the extrinsic resistances change less than 5.0 %.
This allows to conclude that the gate, source and drain resistances have been
properly identied.
IV-17
Parametric impedance curves method in the quasi-static approxima-
tion
It has already been mentioned that the 3-terminal equivalent circuit can be
described by the following matricial equation :
_
Y
1
= Z
+Y
1
(IV.26)
where Y
is the admittance matrix obtained directly from the measured scat-

tering parameters; Y
is the admittance matrix describing the shunt adjacent

part of the circuit; Z
is the impedance matrix including the series extrinsic

and adjacent elements; Y
is the admittance matrix accounting for the intrinsic

and shunt extrinsic elements. Y
is assumed to be known, so that Z
can be
directly evaluated on the basis of the measurements.
It will be shown in the subsequent developments that the specic shape
of equation IV.26 can be exploited to determine the series equivalent circuit
parameters. Several restrictions must however be imposed on the 3-terminal
model described in the introduction of IV.3 : The model of the adjacent
impedances Z
Gfa
and Z
Da
must be reduced to the series inductances L
Gfa
and L
Da
. The quasi-static approximation is used for the intrinsic circuit, let-
ting
0
= 0 so that all NQS circuit parameters
m
, R
GfSi
, R
GfDi
and L
Di
vanish. It will be shown in subsection IV.3.3 how the restriction on the NQS
parameters can be lifted.
Lee et al., [IV.11], have shown that in the quasi-static approximation, the
elements of Z
have the following form :

Re(Z
ij
) = Re(Z
ij
) +
A
ij
2
+ B
for i, j
_
1, 2
_
(IV.27)
1
Im(Z
ij
) =
1
Im(Z
ij
)
E
ij
2
+ B

F
ij
2
_
2
+ B
_
for i, j
_
1, 2
_
(IV.28)
where B, the A
ij
, E
ij
and F
ij
are real and frequency independent coecients
involving only the intrinsic and shunt extrinsic elements see Raskin, [IV.2],
or Raskin and Gillon, [IV.12]. F
12
and F
22
are always zero. All series resis-
tances and inductances can thus be obtained from the asymptotic values taken
by equations IV.27 and IV.28 at innite frequency. In order to evaluate these
asymptotic values, the authors of [IV.11] use an optimiser to t the expres-
sions on the right-hand side of IV.27 and IV.28 individually to the evolutions
of measured data over the available frequency band. It is however possible to
transform the determination of the asymptotic values into simple linear regres-
sion problems.
In the case of the series resistors, this is done by considering the parametric
curves dened in a two dimensional plane by :
_
x
1
()
x
2
()
_
=
_
Re (Z
ij
())
Re (Z
kl
())
_
where i, j ,= k, l (IV.29)
IV-18
GHz

GHz
Im(S
22
)
W
_
m
6.0
12.0
24.0
0 2 4 6 8 10 12 14 16 18 20
Re(S
22
)
W
_
m
6.0
12.0
24.0
0 2 4 6 8 10 12 14 16 18 20
0
0.25
0.50
0.75
1.00
1.00
0.75
0.50
0.25
0
0.25
0.50
0.75
1.00
1.00
0.75
0.50
0.25
GHz

GHz
Re(S
11
)
W
_
m
6.0
12.0
24.0
0 2 4 6 8 10 12 14 16 18 20
Im(S
11
)
W
_
m
6.0
12.0
24.0
0 2 4 6 8 10 12 14 16 18 20
0
0.25
0.50
0.75
1.00
1.00
0.75
0.50
0.25
0
0.25
0.50
0.75
1.00
1.00
0.75
0.50
0.25
GHz

GHz
Re(S
21
)
W
_
m
6.0
12.0
24.0
0 2 4 6 8 10 12 14 16 18 20
Im(S
21
)
W
_
m
6.0
12.0
24.0
0 2 4 6 8 10 12 14 16 18 20
0
0.25
0.50
0.75
1.00
1.00
0.75
0.50
0.25
0
0.25
0.50
0.75
1.00
1.00
0.75
0.50
0.25
terminal circuit model in saturation at V
Gf
= 2.0 V and V
DS
= 3.0 V. The
devices are 10 (W/1.0 m) nMOSFETs.
IV-19
Im(Z
21
)/
pH
Im(Z
22
)/
pH
1500 1000 500 0

Regression
Measurements
x
20
= 9.0
dx
2
dx
1
= 0.2
0.2 L
Da
= 9.0
300
250
200
150
100
50
0
Regression
Measurements
Re(Z
21
)
Re(Z
11
)
x
20
= 17.7
dx
2
dx
1
= 0.2
R
Gfe
+ (1 0.2) R
Se
= 17.7
10
20
30
40
50
60
0 50 100 150 200
Figure IV.8: Parametric impedance curves for a 10 (24.0 m/1.0m) n-
MOSFET at V
GfS
= 1.0 V and V
DS
= 2.0 V .
Using equation IV.27, it is straightforward to establish that these curves must
be straight lines, and that their intercept at the origin [0, x
20
] and slope
dx
2
dx
1
is
given by :
x
20
= Re(Z
kl
)
A
kl
A
ij
Re(Z
ij
) (IV.30)
dx
2
dx
1
=
A
kl
A
ij
(IV.31)
Substituting the values of the intercept and the slope obtained from a linear
regression on the measured data points into IV.30 and IV.31 yields a linear
equation relating the series resistances. To determine all series resistances, it is
necessary to combine three linearly independent equations formed by varying
the indices i, j, k, l. Such a set of equations can only be constructed when
Z
21
and Z
12
are signicantly dierent, which requires to bias the MOS-
FETs in saturation. The most reliable results are obtained from measurements
of saturated MOSFETs and with the following pairs : [Re(Z
11
), Re(Z
21
)],
[Re(Z
12
), Re(Z
21
)], [Re(Z
22
), Re(Z
12
)]. Figure IV.8 illustrates the
quality of the linear regressions performed on data measured from 500 MHz to
40 GHz.
For the series inductances the situation is a little dierent, because of the
more complicated frequency behaviour of the right hand side in IV.28, when
j = 1. As can be seen in gure IV.8, the pair [Im(Z
22
)/, Im(Z
12
)/]
IV-20
produces one useful equation based on the following relations :
x
20
=
E
12
A
22
L
Da
(IV.32)
dx
2
dx
1
=
E
12
E
22
(IV.33)
A second equation can be obtained by considering the parametric curve dened
in the tridimensional space by :
_
_
x
1
()
x
2
()
x
3
()
_
_
=
_
_
Im(Z
21
()) /
Im(Z
12
()) /
Im(Z
11
()) /
_
_
(IV.34)
Equation IV.28 imposes that this curve is contained in a plane, of which the
intercept at the origin [0, 0, x
30
] and the slope coecients
dx
3
dx
1
and
dx
3
dx
2
can be
determined from a linear regression on the measured data.
x
30
= L
Gfa
(IV.35)
dx
3
dx
1
=
F
11
E
21
(IV.36)
dx
3
dx
2
=
E
11
E
12
E
21
F
11
E
12
F
21
(IV.37)
The main advantage of the method based on the parametric curves with
respect to the optimisation of [IV.11], is that decreasing the device size does
not compromise accuracy. Indeed, equations (IV.30), (IV.31), (IV.32), (IV.33),
(IV.35), (IV.36), (IV.37), are not inuenced by the device size, which cancels
out in the ratios
A
ij
A
kl
,
E
ij
E
kl
,
F
ij
F
kl
. The optimisation criteria used by Lee are, on the
contrary, based on equations IV.27 and IV.28 where the A
ij
, E
ij
and F
ij
terms
tend to mask the inuence of the series elements in the case of small devices.
Other important features of the present method are that it takes advantage of
the asymmetry Z
to enhance accuracy, and also that the shared frequency

dependence of the Z
ij
is correctly and coherently accounted for during the
extraction. This latter alleviates the need to discard data below a certain
frequency during the extraction of L
Gfa
, [IV.11].
Extending the parametric method to the non-quasi-static case
The results of the direct extraction scheme shown in table IV.4 are aected by
a bias dependent error due to the use of quasi-static analytical expressions as a
starting-point for the developments. The striking correspondance between the
linear regression and the measured data points in gure IV.8 is paradoxal : an
inappropriate quasi-static model leads to an adequate experimentally
veried formulation of the parametric impedance curves. The conclusion
that can be drawn from gure IV.8 is that the formalism of equations (IV.27)
and (IV.28) is applicable to the non-quasi-static case. The eect of the NQS
IV-21
Parameter W Direct Optimisation Units
6.0 2.88
R
Gfe
12.0 5.76
24.0 10.31 11.52
6.0 37.274
R
Se
12.0 18.63
24.0 9.36 9.317
6.0 49.02
R
De
12.0 24.51
24.0 12.26
Table IV.4: Comparing the results of the direct extraction scheme and the
optimisation, for n-MOSFETs biased at V
Gf
= 3.0 V and V
DS
= 0.0 V, using
the 3-terminal model.
circuit parameters simply translates into a modication of the equation coe-
cients :
Re(Z
ij
) = Re(Z
ij
) + R
ij
+
A
ij
+ A
ij
2
+ B + B
for i, j
_
1, 2
_
(IV.38)
1
Im(Z
ij
) =
1
Im(Z
ij
) + L
ij

E
ij
+ E
ij
2
+ B + B

F
ij
+ F
ij
2
_
2
+ B + B
_
for i, j
_
1, 2
_
(IV.39)
where R
ij
and L
ij
are the contribution of the NQS circuit parameters to
the asymptotic values of the Z
ij
. If they are not properly accounted for as
in the QS extraction scheme of subsection IV.3.3 these NQS contributions
induce an error on the extracted series elements values.
The NQS contributions R
ij
and L
ij
could be easily evaluated if the
admittance matrix Y
was known. Indeed, the NQS contributions could be

obtained by considering the intercept and slope of the parametric curves derived
from Z
[Y
]
1
in the same manner as explained in subsection IV.3.3 for
Z
. The problem is thus now to build correct estimates of Y
on the basis of
the results of the QS extraction scheme. In order to achieve this, simulations
have been performed to identify the intrinsic circuit parameters which could be
reasonably well extracted by the QS scheme. Impedance data corresponding to
Z
was generated using the equivalent circuit of gure IV.1 for various device
sizes and bias points, [IV.12, IV.2]. The QS extraction scheme described below
was then applied :
1. Extraction of the QS estimates of the extrinsic series elements using the
method of subsection IV.3.3. Construction of the QS estimate

Z
(0)
of
Z
.
2. De-embedding of

Z
(0)
from Z
using the QS estimate

Z
(0)
.
IV-22
Re(Z
21
)
Re(Z
12
)
Model
Regression
+
R
Gfe
+ (1 0.132) R
Se
= 2.85
0 50 100 150 200
0
10
20
30
x
20
= 2.85
dx
2
dx
1
= 0.132
Im(Z
21
)/
pH
Im(Z
22
)/
pH
Model
Regression
+
300
250
200
150
100
50
0
1500 1000
500
0
0.2 L
Da
= 0.8
x
20
= 0.8
dx
2
dx
1
= 0.18
Figure IV.9: Parametric impedance curves in the non-quasi-static case.
3. Determination of the QS estimates of the intrinsic elements from
_
Z
(0)
1
by inverting equation (IV.6) as shown by Berroth in [IV.13].
The simulations [IV.12,IV.2] showed that the QS estimates of C
GfSi
, G
m
, G
Di
and
m
were accurate, well within 5.0% of the initial circuit parameter value.
Only the estimate of R
GfSi
suered a signicant error, calling for a alternative
solution. One possibility is to use equations (IV.7) and (IV.8) to relate R
GfSi
to
m
and obtain a better estimate for the NQS resistance :
R
GfSi
(1)
=

m
(0)
C
GfSi
(0)
(IV.40)
Using the new estimate

R
GfSi
(1)
, the updated matrix

Z
(1)
is reconstructed,
and the NQS corrections R
ij
and L
ij
are evaluated by the parametric
curves method, illustrated in gure IV.9. This allows to correct the QS esti-
mates of the series elements and to initiate a new extraction cycle which results
in updated values for the intrinsic circuit elements. Figure IV.10 shows the ex-
tracted

G
m
(k+1)
-curve in function of

R
GfSi
(k)
. The correct

R
GfSi
(k)
results
is a constant G
m
value over the whole measurement band, while under- or
overestimated values result in a down- or upward bending of the curve G
m
.
This feature can be used as a criterion to guide an iterative bisection process
converging to the correct R
GfSi
value :
1. Initiate the process with the QS extraction scheme.
2. Determine the updated estimate for R
GfSi
using equation (IV.40).
IV-23
3. Select an wide interval [R
GfSi
(1)
. . . R
GfSi
(1)
] enclosing

R
GfSi
(1)
.
4. Compute

Z
(k)
using the latest

R
GfSi
(k)
; Evaluate the NQS corrections
and apply them to obtain updated estimates of the series elements. Per-
form a complete extraction cycle and determine the G
m
-curve.
5. If the G
m
-curve bends upward, then bisection step select a new
interval according to :
[R
GfSi
(k+1)
. . . R
GfSi
(k+1)
] [
R
GfSi
(k)
. . . R
GfSi
(k)
] (IV.41)
If the G
m
-curve bends downward, then select a new interval :
[R
GfSi
(k+1)
. . . R
GfSi
(K+1)
] [R
GfSi
(k)
. . .
R
GfSi
(k)
] (IV.42)
6. Select the new R
GfSi
estimate :
R
GfSi
(k+1)

R
GfSi
(k+1)
+ R
GfSi
(k+1)
2
(IV.43)
7. Loop back to point 4 above and increment k. Repeat until the G
m
-curve
is suciently at.
G
m
GHz
R
GfSi
15
16
17
18
19
20
(Q.S.) 0.0
10.0
15.0
20.0
0 10 20 30 40
Figure IV.10: Extracted G
m
curves for several R
GfSi
values.
This procedure has been found to yield consistent results with the optimiser-
based parameter extraction method described in subsection IV.3.3. It is how-
ever computationally much more ecient and better behaved in the sense that
IV-24
IV.4 Four-terminal MOSFET model
it avoids the pittfall of spurious solutions generated by local minima of the
optimisation criterion. The parametric impedance curves method is very well
suited for implementation as a fully automatic routine paving the way for
the systematic extraction of equivalent circuit parameters on a large number
of devices.
As mentioned in the introduction of section IV.3, the SOI MOSFET is inher-
ently a four-terminal device. The simplied three-terminal model introduced
in that section is only valid for high-frequency small-signal analyses. When it
comes to nonlinear broadband modelling, an elaborate model such as the one
developped in section III.6.4 is required. The purpose of the present section
is to show how the extrinsic and adjacent parameters of the elaborate model
may be extracted from small-signal measurements, and in particular, which
parameters were correctly extracted using the simplied model. The complete
small-signal equivalent circuit used in this section is presented in gure IV.11.
It is dedicated for the common-source MOSFET which is the conguration in
which nearly all measurements are done.
IV.4.1 Corrections to the shunt parasitic elements
As indicated in sections IV.3.1 and IV.3.2, the identication of the shunt para-
sitic elements is performed in depletion at the gate voltage corresponding to a
minimum of the global capacitance of the front gate, V
DS
being zero. In these
biasing conditions, the equivalent circuit of gure IV.11 can be substantially
simplied, as all intrinsic conductances and intrinsic capacitances vanish except
C
GfGbi
, which is approximately equal to N
cell
LW C
bf
. The major modi-
cation with respect to the simplied model of section IV.3.1 is the addition of
an elaborate substrate coupling model. In agreement with the denition of the
adjacent circuit elements, the extrinsic substrate coupling model accounts only
for scalable active-zone eects, so that by denition :
C
GbDe
= W C
GbDe
R
GbDe
=
R
GbDe
W
C
De
= W C
De
(IV.44)
C
GbSe
= W C
GbSe
R
GbSe
=
R
GbSe
W
C
Se
= W C
Se
(IV.45)
C
Gbe
= W C
Gbe
R
Gbe
=
R
Gbe
W
(IV.46)
This means in particular, that the adjacent circuit elements should remain
unchanged with respect to the three-terminal model.
IV-25
E
x
t
r
a
c
t
i
o
n
o
f
S
O
I
M
O
S
F
E
T
m
o
d
e
l
p
a
r
a
m
e
t
e
r
s
Drain
Gate
Source
C
GfDe
C
GfSe
R
Gfe
R
De
R
Se
Y
Gfa
Y
Da
Y
GfDa C
GfDi
C
GfSi
R
GfSi
R
GfDi
C
DSe
G
Di
L
Di
Z
Da
Z
Gfa
G
m
e
m
1+
m
C
GbDi
C
GbSi
R
GbSi
R
GbDi
C
GfGbi
G
mbi
e
mbi
1+
mbi
C
De
C
Se
C
Gbe
R
Gbe
C
GbSe
C
GbDe
R
GbDe
R
GbSe
Figure IV.11: The 4-terminal SOI MOSFET model.
I
V
-
2
6
Again, the extraction problem is formulated as an optimisation :
min
P
E(T) (IV.47a)
E

W
k
W
l

i, j {1, 2}

S
(i, j )
(T, W
k
,
l
) S
(i, j )
(W
k
,
l
)
2
(IV.47b)
where the parameter space for the optimisation is :
T
_
p
_
C
GfSe
, C
GfDe
, C
DSe
, C
GbXe
, R
GbXe
, d
Gfa
, d
Da
R
7
[
0.1 p
(0)
p 10 p
(0)
_
(IV.47c)
The eective taper lengths d
Gfa
and d
Da
are included in the set of optimisation
parameters in order to verify whether their value is aected by the type of model
used during extraction. The other adjacent circuit parameters remain xed at
the values found in section IV.3.1. The series extrinsic parameters are taken
from table IV.3. Initial values for the substrate coupling model parameters can
be obtained from available technological data using the procedure described by
Raskin in his thesis, [IV.2]. The number of potential optimisation parameters
is further reduced by imposing the symmetry of the substrate coupling model
during the optimisation :
C
GbSe
C
GbXe
C
GbDe
(IV.48)
R
GbSe
R
GbXe
R
GbDe
(IV.49)
where only R
GbXe
and C
GbXe
are considered as optimisation parameters.
This extraction procedure was applied to the same transistors as in sec-
tion IV.3.1. The residual error was R = 3.4 10
3
, about half of the value
obtained with the 3-terminal model. Figure IV.12 shows the good correspon-
dence between the modelled and measured curves. Table IV.5 gives the Detailed
results.
It is noteworthy that d
Gfa
remained virtually unchanged, while d
Da
was
modied by about 5.0 %. The modication of d
Da
may be explained by the
absence of a resistor R
DSe
in parallel with C
DSe
in the extrinsic part of the
simplied model. This absence was compensated during the extraction of sec-
tion IV.3.1 by an increase of d
Da
and a diminution of C
D0a
. It seems thus rea-
sonable to conclude that the adjacent circuit elements can be properly extracted
using the simplied equivalent circuit provided an extrinsic resistance R
DSe
is used.
IV-27
GHz

GHz
Im(S
21
)
W
0 2 4 6 8 10 12 14 16 18 20
6.0
12.0
24.0
0
0.25
0.50
0.75
1.00
1.00
0.75
0.50
0.25
Re(S
21
)
W
_
m
0 2 4 6 8 10 12 14 16 18 20
6.0
12.0
24.0
0
0.25
0.50
0.75
1.00
1.00
0.75
0.50
0.25
GHz

GHz
Im(S
11
)
W
_
m
0 2 4 6 8 10 12 14 16 18 20
6.0
12.0
24.0
0
0.25
0.50
0.75
1.00
1.00
0.75
0.50
0.25
Re(S
11
)
W
_
m
0 2 4 6 8 10 12 14 16 18 20
6.0
12.0
24.0
0
0.25
0.50
0.75
1.00
1.00
0.75
0.50
0.25
GHz

GHz
Re(S
22
)
W
_
m
0 2 4 6 8 10 12 14 16 18 20
6.0
12.0
24.0
0
0.25
0.50
0.75
1.00
1.00
0.75
0.50
0.25
Im(S
22
)
W
_
m
0 2 4 6 8 10 12 14 16 18 20
6.0
12.0
24.0
0
0.25
0.50
0.75
1.00
1.00
0.75
0.50
0.25
terminal circuit model in depletion. The devices are 10 (W/1.0 m) nMOS-
FETs.
IV-28
C
GfDe
2.3629 2.5289 nF/m 2.0 10
1
d
Gfa
64.48 64.26 m 2.0 10
1
d
Da
58.02 63.54 m 2.0 10
1
C
GfSe
2.4323 2.5723 nF/m 8.5 10
2
C
DSe
0.7734 nF/m 1.5 10
2
C
GbXe
0.1516 nF/m 3.0 10
4
R
GbXe
82.64 m m 3.5 10
4
C
Xe
0.8924 nF/m 4.5 10
4
C
GfGbi
0.45 nF/m 1.0
C
Gbe
nF/m 1.0
R
Gbe
m 1.0
Table IV.5: Detailed results of the extraction in depletion at V
Gf
= 1.0 V
and V
DS
IV.4.2 Corrections to the series parasitic elements
The extraction of the series resistances and of the intrinsic circuit parameters
for the 4-terminal model can be accomplished in essentially the same way as for
the 3-terminal model. For saturated devices, the full complexity of the model
of gure IV.11 must be used; None of the circuit elements may be discarded.
Considering that the number of intrinsic circuit elements has doubled with
respect to the 3-terminal model, one may realise that reduction of the number
of potential optimisation parameters has become even more important here. In
order to render the extraction problem tractable, a call is made upon the device
equations, which in the case of fully depleted SOI MOSFETs allow to link the
back- and front-gate circuit parameters as already shown in section IV.3 :
C
GbSi
C
GfSi
=
R
GfSi
R
GbSi
=
f
1 (IV.50)
C
GbDi
C
GfDi
=
R
GfDi
R
GbDi
=
f
1 (IV.51)
G
mbi
G
m
=
f
1 (IV.52)
This set of equations is very usefull, as it relates the weakly inuent back-
gate circuit parameters to their front-gate counterparts which have a dominant
inuence on the frequency response. Remembering the time-constant model
of Tsividis equations (III.143) , all NQSintrinsic circuit elements can be
related to a single time constant,
0
, (IV.7) (IV.9). The extraction problem
IV-29
then takes the form :
min
P
E(T) (IV.53a)
E

W
k
W
l

i, j {1, 2}

S
(i, j )
(T, W
k
,
l
) S
(i, j )
(W
k
,
l
)
2
(IV.53b)
T
_
p
_
C
GfSi
, C
GfDi
, G
m
, G
Di
,
0
, R
Gf0e
, R
Gfe
, R
De
, R
Se
R
9
[
0.1 p
(0)
p 10 p
(0)
_
(IV.53c)
Values for the adjacent and extrinsic circuit elements are taken from sec-
tion IV.4.1. The capacitance C
GfGbi
kept constant at the value L/3 C
bf
.
This extraction procedure was applied to the same transistors as in sec-
tion IV.3.1. The residual error R was 2.4 10
2
, slightly better than previously.
Table IV.6 allows to compare the extraction results with those obtained using
the simplied model, listed in the initial values column. It is remarkable that
none of the extrinsic series resistance changed signicantly. Amongst the in-
trinsic parameters, only G
Di
changed notably. The value extracted for G
Di
in
the framework of the 3-terminal model is indeed aected by the absence of a
transconductance G
mbi
in the circuit. These results conrm that the simpli-
ed equivalent circuit allows to extract correct values for the extrinsic series
resistances as well as the following intrinsic parameters : G
m
, C
GfSi
and
0
.
G
m
0.606 0.6092 k/m 1.7
C
GfSi
4.9152 4.8049 nF/m 1.5 10
1
R
Se
0.1148 0.1151 m m 3.0 10
2
G
Di
54.212 71.084 /m 2.0 10
2
R
Gfe
0.4946 0.5142 M/m 2.0 10
2
0
14.305 13.49 ps 1.0 10
2
R
De
0.2934 0.2929 m m 8.5 10
3
C
GfDi
0.3163 0.14269 nF/m 3.0 10
3
R
Gf0e
0.00053 0.00053 3.0 10
7
Table IV.6: Detailed results of the extraction in saturation at V
Gf
= 2.0 V and
V
DS
IV-30
GHz

GHz
Im(S
22
)
6.0
12.0
24.0
W
_
m
0 2 4 6 8 10 12 14 16 18 20
0
0.25
0.50
0.75
1.00
1.00
0.75
0.50
0.25
Re(S
22
)
6.0
12.0
24.0
W
_
m
0 2 4 6 8 10 12 14 16 18 20
0
0.25
0.50
0.75
1.00
1.00
0.75
0.50
0.25
GHz

GHz
Re(S
11
)
W
_
m
0 2 4 6 8 10 12 14 16 18 20
6.0
12.0
24.0
0
0.25
0.50
0.75
1.00
1.00
0.75
0.50
0.25
Im(S
11
)
6.0
12.0
24.0
W
_
m
0 2 4 6 8 10 12 14 16 18 20
0
0.25
0.50
0.75
1.00
1.00
0.75
0.50
0.25
GHz

GHz
Re(S
21
)
6.0
12.0
24.0
W
_
m
0 2 4 6 8 10 12 14 16 18 20
0
0.25
0.50
0.75
1.00
1.00
0.75
0.50
0.25
Im(S
21
)
6.0
12.0
24.0
W
_
m
0 2 4 6 8 10 12 14 16 18 20
0
0.25
0.50
0.75
1.00
1.00
0.75
0.50
0.25
terminal circuit model in saturation at V
Gf
= 2.0 V and V
DS
= 3.0 V. The
devices are 10 (W/1.0 m) nMOSFETs.
IV-31
IV.5 Intrinsic MOSFET in the linear operating
regime
The linear operating regime must be understood as the set of bias points at
which the carriers in the channel do not attain their saturation velocity. This
corresponds roughly to the following condition : V
Gf
V
Thf
> V
DS
. At low
drain voltages, one may expect that velocity saturation will only have a limited
impact on the device performance, so that an accurate knowledge of the pa-
rameters modelling this eect is not required to obtain sensible predictions of
the device responses. For moderately short channel lengths (L > 0.5 m), one
may even neglect the inuence of velocity saturation on the small-signal char-
acteristics at V
DS
= 0.0. This feature is particularly useful, as it considerably
simplies the extraction of the transport and inversion-charge parameters.
IV.5.1 Determination of the C-V curve from broadband
measurements
It has been shown in section III.5.2 that, at V
DS
= 0, an analytical small-signal
model can be obtained which rigorously accounts for the distributed channel
eects in the SOI MOSFET. The model is based on the expressions of the
admittance matrix Y
Cf
describing the distributed channel when both the front
and back gates are grounded :
Y
Cf
=
1
z
Cf
sinh(
Cf
L)
_
cosh(
Cf
L) 1
1 cosh(
Cf
L)
_
(IV.54)
Cf

1
L
_
j R
Cf
_
C
GfC
+ C
GbC
_
(IV.55)
z
Cf

_
R
Cf
j
_
C
GfC
+ C
GbC
_ (IV.56)
where R
Cf
= R
DSi
is the static resistance of the channel, while C
GfC
= C
GfSi
+
C
GfDi
and C
GbC
= C
GfSi
+ C
GfDi
are the static capacitances of the channel
to the front and back gates. The merit of expression IV.54 is thus to link
the high-frequency admittance matrix of the channel to three low-frequency
channel characteristics.
As already indicated, the back gate of the SOI MOSFET does not behave
as a grounded node at microwave frequencies, so that the more elaborate model
of equation III.154 is required in order to account for the substrate coupling
eects. The next subsection describes the extraction of the R
Cf
-, C
GfC
- and
C
GbC
-curves in the framework of the 4-terminal model using an optimiser. The
subsection thereafter proposes a analytical method allowing to extract the R
Cf
-
and C
GfC
-curves directly from measurements.
IV-32
IV.5 Intrinsic MOSFET in the linear operating regime
GHz
0 2 4 6 8 10 12 14 16 18 20
0
0.25
0.5
0.75
1.0
1.0
0.75
0.5
0.25
Re(S
22
) V
Gf
_
V
3.0
2.0
1.0
0.5
0.2
0.4
1.0
GHz
0 2 4 6 8 10 12 14 16 18 20
0
0.25
0.5
0.75
1.0
1.0
0.75
0.5
0.25
Im(S
22
) V
Gf
_
V
3.0
2.0
1.0
0.5
0.2
0.4
1.0
GHz
0 2 4 6 8 10 12 14 16 18 20
0
0.25
0.5
0.75
1.0
1.0
0.75
0.5
0.25
Im(S
11
) V
Gf
_
V
3.0
2.0
1.0
0.5
0.2
0.4
1.0
GHz
0 2 4 6 8 10 12 14 16 18 20
0
0.25
0.5
0.75
1.0
1.0
0.75
0.5
0.25
3.0
2.0
1.0
0.5
0.2
0.4
1.0
Re(S
11
) V
Gf
_
V
Figure IV.14: Comparing the measured (dotted lines with rings) and modelled
(continuous lines with crosses) S-parameters after extraction of C
GfC
and G
Cf
on a 10
_
24.0m/2.0m
_
n-MOSFET.
Optimiser driven broadband curve-tting
In order to extract the C-V curves from broadband S-parameters measurements
of the common-source MOSFET, the circuit of gure IV.11 is used. All extrinsic
and adjacent elements must have been determined a priori using the methods
described earlier. The intrinsic part, grouping all elements with index i is
however replaced by the admittance matrix Y
FET
dened in equation IV.54.
Explicit use is made of equation (IV.50) to avoid using C
GbC
as an optimisation
variable, as its inuence on device response is expected to be marginal. The
extraction is then formulated as a set of optimisation problems, one for each
IV-33
bias-point :
min
P
k
E(T
k
) (IV.57a)
E

l

i, j {1, 2}

S
(i, j )
(T
k
,
l
) S
(i, j )
(V
Gf (k)
,
l
)
2
(IV.57b)
T
k

_
p
_
C
GfC(k)
, R
Cf (k)
R
2
[ 0.1 p
(0)
p 10 p
(0)
_
(IV.57c)
V
Gf

_
V
Gf (1)
, . . . , V
Gf (n)
is the vector of applied gate biases, while C

GfC

_
C
GfC(1)
, . . . , C
GfC(n)
and R
Cf

_
R
Cf (1)
, . . . , R
Cf (n)
are the correspond-

ing vectors of extracted channel resistances and capacitances.
Figure IV.14 shows the good agreement between the model and the measure-
ment, as obtained after a typical extraction process. It is remarkable that such
a good t for the four scattering parameters is obtained over the whole measure-
ment band by adjusting only two model parameters at every bias point ! This
underlines the validity of the distributed channel model. Figure IV.16 shows
the corresponding extraction results in the form of the total gate capacitance
C
Gf
= C
GfC
+ C
GfSe
+ C
GfDe
.
Simplied analytical method
In the framework of the three terminal model, it is possible to extract C
GfC
and R
CfC
directly from the measurements of the common-source MOSFET
without any optimisation. Neglecting the back gate capacitances C
GbC
and
C
GfGb
, the matrix Y
FET
from equation IV.54 simplies to Y
Cf
. Using the 3-
terminal equivalent circuit of gure IV.1 together with its associated matricial
equation (IV.3), it is possible to De-embed the admittance matrix Y
from
the measurements. The matrix Y
accounts for both the shunt extrinsic and

intrinsic elements of the common-source MOSFET. Stripping o the extrinsic
shunt parasitics, one may write :
Y

_
C
GfSe
+ C
GfDe
C
GfDe
C
GfDe
C
DSe
+ C
GfDe
_
=
1
z
Cf
sinh(
Cf
L)
_
2
_
cosh(
Cf
L) 1
1
_
cosh(
Cf
L) 1
1
_
cosh(
Cf
L) 1
cosh(
Cf
L)
_
(IV.58)
Equation (IV.58) combined with (IV.55) and (IV.56) allows to determine R
Cf
and C
GfC
directly. Figure IV.15 compares the result of the present direct
extraction technique and the optimisation described earlier. The curves for
both C
GfC
and G
Cf
1/R
Cf
correspond very well.
IV-34
C
GfC
_
fF
2
0 2 4
G
Cf
_
m
10
0
10
20
30
40
50
60
20
0
20
40
60
80
100
120
140
160
2
0 2 4
V
Gf
_
V
V
Gf
_
V
Figure IV.15: Comparing the results of the optimisation (crosses) and the direct
extraction (rings) for a 10
_
24.0m/1.0m
_
n-MOSFET.
IV.5.2 Threshold voltage
In chapter III, the threshold voltage for moderate inversion, V
Thf (mod)
, was
dened as :
V
Thf (mod)
= V
fbf

Q
b
2C
of
if
C
of
+
f
_
V
C
+ 2
F
_
bob
C
of
_
V
Gb
V
fbb
+
Q
b
2C
ob
+
Q
ib
C
ob
_
(IV.59)
This denition is however rather theoretical and does not indicate how to pro-
ceed to obtain the threshold voltage from the measured C-V curve shown in
gure IV.16. Booth et al, [IV.14], investigated several operational denitions
and compared them to theoretical denitions such as IV.59. They indicated
that the point of steepest slope in the G
m
versus V
Gf
characteristic at low
drain voltage provided the best estimate of V
Thf (mod)
. This extremum of
dG
m
dV
Gf
corresponds in fact to the maximal increase rate of the inversion charge, and
can equally well be evaluated by selecting the corresponding point of the C
Gf
-
curve. According to Flandre, [IV.15], the front gate at-band voltage V
fbf
can
estimated as the gate voltage at which the accumulation charge starts to build
up. Combining threshold and at-band voltage measurements with the sub-
threshold slope measurements described by Colinge in [IV.16], it is possible to
determine the xed oxide charge densities N
of
and N
ob
the interface traps den-
sities N
if
, N
ib
and the depletion charge density in the lm, Q
b
. Determination
IV-35
of these quantities is important, as they are most variable of all parameters
present in expression (IV.59). Typical values are : N
of
= 3.63 10
11
cm
2
,
N
ob
= 2.45 10
11
cm
2
, N
if
= 1.67 10
11
cm
2
V
1
, N
ib
= 1.0 10
12
cm
2
V
1
.
Q
b
/q = 5.11
16
cm
3
3 2.5 2 1.5 1 0.5
0 0.5 1 1.5 2 2.5 3
100
162
225
288
350
412
475
538
600
_
fF
V
Gf
_
V
C
Gf
inversion accumulation
V
Thf
V
fbf
Figure IV.16: Extracted total gate capacitance of a 10
_
24.0m/2.0m
_
n-
MOSFET.
IV.5.3 Mobility
In the case of a small-signal excitation at V
DS
= 0, the channel conductance
can be approximated by the following expression :
G
Cf
=
1
R
Cf
N
cell
W
L
Q
nf
(IV.60)
where Q
nf
is the inversion charge density, which is assumed to be constant
along the channel. At microwave frequencies, the interface traps are not able
to respond to the applied signals, so that the only contribution to the gate-
to-channel capacitance C
GfC
is due to the inversion charge. This allows to
compute the inversion charge in function of the applied gate bias by integration
of C
GfC
, starting at a gate voltage V
Gf0
at which C
GfC
= 0 :
Q
nf
(V
Gf
) =

f
N
cell
W L
_
V
Gf
V
Gf0
C
GfC
(V )dV (IV.61)
IV-36
S
e
_
cm
2
/
_
Vs
_

0
= 580.8
cm
2
/
Vs
= 0.0287
m/V
100
200
300
400
500
600
700
0 5 10 15 20
_
V/m
Figure IV.17: Extracted mobility versus normal electric eld curve for a 10
_
24.0m/1.0m
_
n-MOSFET.
Knowing the inversion charge and the layout dimensions, it is now possi-
ble to extract the mobility from the measured channel conductance curve us-
ing IV.60. The channel mobility is known to degrade when the gate voltage
is increased because the normal electric eld presses the carriers harder onto
the gate oxide, causing more collisions and reducing their average speed. This
eect can be modelled by the simple expressions introduced in section III.3.1
and shown below :

e
=

0
1 +
S
e
(IV.62)
S
e
S
sf

Q
nf
2
Si
=
_
sf

sb
t
b
b
2
Si
_
nf
2
Si
(IV.63)
Using equation (III.29) and (III.30), the surface potentials
sf
and
sb
can
be related to the inversion charge density Q
nf
. This allows to evaluate S
e
on
the basis of the measured gate-channel capacitance C
GfC
and equation (IV.61).
The evolution of the extracted mobility is plotted on gure IV.17 in function of
the normal electric eld. The low-eld mobility
0
and the normal eld coe-
cient can be extracted by performing a linear regression on 1/(S
e
). The
results shown in the gure are in very good agreement with those published by
Sherony et al. in [IV.17]. This underlines both the validity of the distributed
channel model and the accuracy of the extracted series resistances. Overes-
timated series resistances would cause an increase of the eective mobility at
IV-37
high gate voltages corresponding to high S
e
instead of the smooth
S
1
e
decay. At low gate voltages, typically V
Gf
V
Thf
, the evaluation of the
mobility according to (IV.60) is erroneous because Q
nf
can not be considered
constant along the channel.
IV.5.4 Unied analytical model from depletion to inver-
sion
The last subsections have demonstrated that the extraction of threshold voltage
and mobility parameters from broadband S-parameters measurements is feasi-
ble, provided that the distributed channel eects are properly accounted for in
the model. Accordingly, three channel sections are used here to perform the
extraction of the empirical parameters used in the inversion charge expressions
of the unied analytical current and charge model presented in chapter III. It
has indeed been shown in section III.5.3 that three subdivisions is a good com-
promise between model complexity and accuracy of the predictions even
somewhat conservative on the accuracy. The current and charge sources of
the unied analytical model are embedded into the 4-terminal equivalent cir-
cuit, replacing the small-signal elements of the intrinsic part. All adjacent and
extrinsic elements are kept xed at their previously extracted values. The op-
timisation described below is performed over the set of measured bias points
1
lin
, for which V
DS
= 0 and V
Gf
varies from depletion to strong inversion.
Only the empirical threshold voltage parameters and the mobility coecients
are allowed to vary.
min
P
E(T) (IV.64a)
E

(V
Gf
,V
D
) V
lin
l

i, j {1, 2}

S
(i, j )
(T, V
Gf
, V
D
,
l
) S
(i, j )
(V
Gf
, V
D
,
l
)
2
(IV.64b)
T
_
p
_
0
, ,
stg
,
wk
,
wkstg
R
5
[
0.1 p
(0)
p 10 p
(0)
_
(IV.64c)
Table IV.7 summarises the results of the extraction scheme applied to a
10
_
24.0m/1.0m
_
n-MOSFET fabricated at the UCL. Figure IV.18 com-
pares the measured and modelled S-parameters after extraction. The measured
and modelled curves in strong inversion and in depletion are all in reasonable
agreement with each other. At V
Gf
= 0, however, there is a non-negligible
dierence between the two types of S
11
-curves. It is not very well clear yet
for what reason the model is not able to properly reproduce the behaviour
of the gate capacitance just below threshold. Possible explanations might be
the absence of corrections accounting for charge-sharing, the perfectible inner
fringing capacitance model, or eventually inadequate evaluation of the DIBL
coecient. Nevertheless, this discrepancy is rather marginal with respect to
the good t which prevails at the majority of bias points.
IV-38
Parameter Final Value Initial Value Units
0
559.2 580.8 cm
2
/(Vs)
0.02607 0.0287 m/V
stg
2.0803 2.0
T
wk
1.1215 1.0
T
wkstg
0.70354 0.9
Table IV.7: Detailed results of the extraction at V
DS
= 0.0 V, using the unied
analytical IQ-model with 3 sections, for a 10
_
24.0m/1.0m
_
n-MOSFET.
GHz
0 2 4 6 8 10 12 14 16 18 20
0
0.25
0.5
0.75
1.0
1.0
0.75
0.5
0.25
Im(S
11
)
3.0
0.5
0.0
0.5
GHz
0 2 4 6 8 10 12 14 16 18 20
0
0.25
0.5
0.75
1.0
1.0
0.75
0.5
0.25
Re(S
11
)
3.0
0.5
0.0
0.5
GHz
0 2 4 6 8 10 12 14 16 18 20
0
0.25
0.5
0.75
1.0
1.0
0.75
0.5
0.25
Re(S
22
)
3.0
0.5
0.0
0.5
2.0
1.0
GHz
0 2 4 6 8 10 12 14 16 18 20
0
0.25
0.5
0.75
1.0
1.0
0.75
0.5
0.25
Im(S
22
)
3.0
0.5
0.0
0.5
2.0
1.0
V
Gf
_
V
V
Gf
_
V
V
Gf
_
V
V
Gf
_
V
Figure IV.18: Comparing the measured (dotted lines with rings) and mod-
elled (continuous lines with crosses) S-parameters after extraction of the unied
model parameters for a 10
_
24.0m/1.0m
_
n-MOSFET.
IV-39
IV.6 Intrinsic MOSFET in saturation
A MOSFET is said to operate in saturation when the electric eld at the drain
side of the channel drives the carriers so hard that they attain the saturation
velocity, v
n(sat)
. It occurs in long-channel MOSFETs when the channel is
pinched o, in other words, when V
DS
> V
Gf
V
Thf
. In the case of FETs
with very short channels L < 0.2 m , carriers may attain the satura-
tion velocity in the channel even before pinch-o. This is typically the case in
MESFETs and HEMTs, where it is commonly admitted that the length of
the linear channel region is negligible with respect to the region where carriers
travel at the saturation velocity, [IV.18]. The converse is true for long-channel
MOSFETs, where the length of the saturation region is often neglected. The
SOI MOSFETs considered in this work, have eective channel lengths ranging
between 0.5 m and 1.5 m, so that none of the above simplications apply.
In normal biasing conditions, the length of the saturation region may attain
0.15 m to 0.2 m, which constitutes a non-negligible fraction of the total chan-
nel length. These considerations stress the importance of the channel length
modulation model, as well as the need to properly evaluate its parameters :
v
n(sat)
, the saturation velocity, , the critical eld coecient, and
linsat
the
empirical parameter controlling the transition from the linear regime to satu-
ration.
The extraction of these parameters is once again performed using the opti-
miser. The corresponding optimisation problem is formulated below. The set
of bias voltages considered during the optimisation, 1
sat
, extends from satu-
ration into the linear region in order to adequately characterise the transition.
min
P
E(T) (IV.65a)
E

(V
Gf
, V
D
) V
sat
l

i, j {1, 2}

S
(i, j )
(T, V
Gf
, V
D
,
l
) S
(i, j )
(V
Gf
, V
D
,
l
)
2
(IV.65b)
T
_
p
_
v
n(sat)
, ,
linsat
R
3
[ 0.1 p
(0)
p 10 p
(0)
_
(IV.65c)
The extraction results obtained in the case of a 10
_
24.0m/1.0m
_
n-
MOSFET fabricated at the UCL are listed in table IV.8. The number of param-
eters present in that table illustrates the compactness of the unied analytical
model : Few parameters need to be adjusted to nevertheless produce a sat-
isfactory agreement between the modelled and measured S-parameters curves
shown in gures IV.19 and IV.20. The former shows the evolution of the four
scattering parameters for various gate voltages while the drain voltage is kept
constant. In the latter, the gate voltage is xed and the drain bias is varied.
Figure IV.19 reveals a tendency of the model to overestimate the drain-
source conductance that becomes worse when the drain voltage is increased.
This can be noticed by looking at the low-frequency values of S
22
, close to the
IV-40
Parameter Final Value Initial Value Units
v
n(sat)
0.9153 1.0 10
5
m/(Vs)
1.3765 1.8
linsat
0.70354 4.0
Table IV.8: Detailed results of the extraction in saturation, using the unied
analytical IQ-model with 3 sections, for a 10
_
24.0m/1.0m
_
n-MOSFET.
horizontal axis of the Smith chart. This eect is also clearly present in the
lowest plot of gure IV.20. This has been interpreted as the manifestation of
self-heating eects, which are not accounted for in the model. Tenbroek et al.
showed in their paper [IV.19] that the high-frequency drain-source conductance
decreases when the temperature rises. This is may explain why the prediction
of the output conductance are systematically higher than the measurements
once the dissipated power attains a few tens of milli-Watts.
The discrepancies between the modelled and measured S
22
at the upper
end of the band are probably related to inaccuracies in the substrate coupling
model. Section IV.4.2 revealed indeed that the joint eect of the transconduc-
tance G
mbi
and of the capacitive coupling of the back gate to the diusions
strongly inuences the apparent value of the drain-source conductance.
The modelled and measured curves of forward transmission S
21
and input
reection S
11
are in very good agreement for all biases except the point
at V
Gf
= 2.0 and V
DS
= 3.0 where the self-heating during the measurements
was the worst. These results illustrate again the validity of the channel parti-
tion scheme, which is responsible for the evaluation of the NQS eects in the
unied analytical model. NQS eects indeed translate into a bias-dependent
resistance in series with the gate-source capacitance and a phase-shift of the
transconductance, as shown in section IV.3.3. The close t of S
21
and S
11
at
all bias points suggests that both phenomena are properly predicted by the
three sections model.
IV-41
S
21
S
12
S
11
S
22
V
Gf
= 2.0 V
V
D
= 2.0 V
S
21
S
12
S
11
S
22
V
Gf
= 3.0 V
V
D
= 2.0 V
S
21
S
12
S
11
S
22
V
Gf
= 1.0 V
V
D
= 2.0 V
_
24.0m/1.0m
_
n-MOSFET.
IV-42
S
21
S
12
S
11
S
22
V
Gf
= 2.0 V
V
D
= 2.0 V
S
21
S
12
S
11
S
22
V
Gf
= 2.0 V
V
D
= 1.0 V
S
21
S
12
S
11
S
22
V
Gf
= 2.0 V
V
D
= 3.0 V
_
24.0m/1.0m
_
n-MOSFET.
IV-43
IV.7 Conclusion
A comprehensive extraction procedure has been developed along this chap-
ter, allowing, on the y, to validate all of the newly proposed models. The
NQS small-signal equivalent circuit was completely determined, and reliable
identication of all dominant parasitic elements was demonstrated. The most
important parameters of the unied analytical current and charge model were
extracted from on-wafer scattering parameters measurements performed at mi-
crowave frequencies. Extracted values for physical parameters were found to
be in good agreement with results published in the literature. Adequate values
for the few empirical parameters were readily obtained. Important original
contributions included in this chapter were :
1. A direct extraction scheme for the small-signal NQS equivalent circuit.
2. A direct extraction scheme for the gate-to-channel capacitance and the
channel conductance from broadband measurements on MOSFETs at
V
DS
= 0.
Experience has shown that direct extraction schemes are invaluable tools com-
pared to optimiser-driven methods. They are much more computationally ef-
cient, may work unsupervised and are easily implemented as automatic rou-
tines. The original direct extraction schemes proposed in this chapter are thus
very well suited for statistical modelling, opening up the possibility to extract
the equivalent circuit on a large population of devices.
The numerous comparisons of measured and predicted data allowed to verify
that, in particular :
1. The series resistances can be indierently extracted in the framework of
the 3- or of the 4-terminal model.
2. The proposed scaling rules for the small-signal model are valid in all
possible bias conditions, provided that the active zone width is neither
too long or too short.
3. Three subdivisions suce to properly account for the NQS eects using
the unied analytical current and charge model.
The strengths and weaknesses of the unied analytical current and charge
model were briey discussed. Weaknesses are the absence of self-heating eects
and an unresolved problem in the evaluation of the gate capacitance just below
threshold. The major strong point is the very limited number of parameters
that must be adjusted in order to produce reasonable predictions in all bias
conditions up to 20 GHz.
References
[IV.1] I. Huynen, J.-P. Raskin, and D. Vanhoenacker, An ecient varia-
tional characterisation of multilayered planar lines combining thin and
low resistivity layers, IEEE Trans. on Microwave Theory and Tech-
niques, Submitted.
IV-44
REFERENCES
[IV.2] J.-P. Raskin, Modeling, Characterization and Optimization of MOS-
[IV.3] J. Chen, Development of Metallization Processes on Thin-Film SOI
for Low-Voltage, Low-Power Microwave and High-Temperature Appli-
cations. PhD thesis, Universite catholique de Louvain, Dec. 1997.
[IV.4] J. J. Barnes, K. Shimohigashi, and R. W. Dutton, Short-channel
mosfets in the punchthrough current mode, IEEE Trans. on Electron
[IV.5] K. L. Peng and M. A. Afromowitz, An improved method to deter-
mine MOSFET channel length, IEEE Electron Device Letters, vol. 3,
pp. 360362, Dec. 1982.
[IV.6] J. Whiteld, A modication on an improved method to determine
the MOSFET channel length, IEEE Electron Device Letters, vol. 6,
pp. 109110, Mar. 1985.
[IV.7] F. J. Garcia Sanchez, A. Ortiz-Conde, M. Garcia Numez, and R. L.
Anderson, Extracting the series resistance and eective channel
length of short-channel MOSFETs at liquid nitrogen temperature,
Solid State Electronics, vol. 37, p. 1943, 1994.
[IV.8] J.-C. Gua, S. Shao-Shiun Chung, and C. Ching-Hsiang Hsu, A new
approach to determine the eective channel length and the drain-and-
source series resistance of miniaturized MOSFETs, IEEE Trans. on
Electron Devices, vol. 41, pp. 18111817, Oct. 1994.
[IV.9] W. Fikry, G. Ghibaudo, H. H., C. S., and D. M., A new method
to extract deep submicron MOSFET parameters, in probably ECS
Abstracts, undetermined date.
[IV.10] G. Dambrine, F. Heliodore, and E. Playez, A new method for de-
termining the FET small-signal equivalent circuit, IEEE Trans. on
Microwave Theory and Techniques, vol. 36, pp. 11511159, July 1988.
[IV.11] S. Lee, H. K. Yu, C. S. Kim, J. G. Koo, and K. S. Nam, A novel
approach to extracting small-signal model parameters of silicon MOS-
FETs, IEEE Microwave and Guided Waves Letters, vol. 7, pp. 7577,
Mar. 1997.
[IV.12] J.-P. Raskin, R. Gillon, J. Chen, D. Vanhoenacker, and J.-P. Colinge,
Accurate SOI MOSFET characterization at microwave frequencies
for device performance optimisation and analogue modelling, IEEE
Trans. on Electron Devices, May 1998. Accepted for publication.
[IV.13] M. Berroth and R. Bosch, Broad-band determination of the FET
small-signal equivalent circuit, IEEE Trans. on Microwave Theory
and Techniques, vol. 38, pp. 891895, July 1990.
IV-45
[IV.14] R. V. Booth, M. H. White, H.-S. Wong, and T. Krutsick, The eect
of channel implants on MOS transistor characterization, IEEE Trans.
on Electron Devices, 1987.
[IV.15] D. Flandre, Etude de Faisabilite dune technologie CMOS sur Isolant
(SOI) dans le Domaine des Circuits Digitaux. PhD thesis, Universite
catholique de Louvain, Laboratoire d Hyperfrequences, 1990.
[IV.16] J.-P. Colinge, Silicon-on-Insulator Technology : Materials to VLSI.
Boston: Kluwer Academic Publ., 1991.
[IV.17] M. J. Sherony, L. T. Su, J. E. Chung, and D. A. Antoniadis, SOI
MOSFET eective channel mobility, IEEE Trans. on Electron De-
vices, vol. 41, pp. 276278, Feb. 1994.
[IV.18] J. H. Golio, Microwave MESFETs and HEMTs. Artec House, 1991.
[IV.19] B. M. Tenbroek, M. S. L. Lee, W. Redman-White, R. J. T. Bunyan,
and M. J. Uren, Self-heating eects in SOI MOSFETs and their
measurement by small signal conductance techniques, IEEE Trans.
on Electron Devices, vol. 43, pp. 22402248, Dec. 1996.
IV-46
Chapter V
Microwave MOSFET
downconversion mixers
V.1 Introduction
There is presently a considerable research eort in the micro-electronic and
microwave community towards the development of fully integrated transceivers
for mobile communications. Much work is being done around CMOS technol-
ogy as it is low-cost and should allow to address the mass-market at lower
prices. The high-frequency parts of the system are the object of the an in-
tense attention as technology evolved upwards from the radio-frequency range
to the microwave range. Design solutions for the mixer stages have evolved
substantially in order to adapt to the specic requirements of microwave op-
eration. Using the SOI MOSFET model developed in the previous chapter,
the feasibility of microwave integrated mixers is investigated. Starting with
a description of the basic building blocks to develop a thorough understand-
ing of their operation, the chapter proceeds with a comparison of the major
types of balanced mixer cells to nally select the resistive ring structureure and
construct a complete down-conversion stage.
Section V.2 introduces the two major types of mixers : Active and passive
mixers. Single device mixers are analysed in order to identify specic
features for each type.
Doubly balanced structures are presented in section V.3 as an ecient
means to enhance the performance of integrated mixers. Measured char-
acteristics of chopping and resistive SOI MOSFET mixers are compared
V-1
Microwave MOSFET downconversion mixers
with existing bulk implemetations showing the denite advantage of SOI
in terms of low-voltage microwave performances.
Section V.4 starts with a comparison of several down-converter architec-
tures, showing the evolution towards single-chip integration. Solutions
for the implementation of a low-IF receiver in SOI CMOS are presented.
The concept of device mismatch is used several times in the text below.
The intended meaning is the one commonly admitted by IC design engineers :
a disparity in the characteristics of nominally identical devices. This might be
somewhat confusing for microwave engineers who use the term mismatch in
relation with the concept of impedance matching or tuning for optimal power
transfer or noise characteristics.
V.2 Single FET mixers
According to Maas, [V.1], and Philippe, [V.2], two major types of FET mixers
can be identied having each specic advantages and drawbacks :
1. Active mixers, also named transconductance mixers, where the mixing
transistors support a substantial DC bias current;
2. Passive mixers where the bias current is zero and where an eventual DC
current results only from self-mixing products.
In order to identify the properties of the active and passive operation modes
for mixers, simplied structures will be considered. A single FET is the basic
building block for mixers. Understanding its characteristics yields an immedi-
ate insight into the strength and weaknesses of more elaborate mixing cells.
Such elaborate cells attempt to enhance mixer performance by combining the
responses of identical devices in such a way that unwanted mixing products
cancel out mutually. A meaningful comparison of balanced designs must in-
clude an evaluation of their respective sensitivity to imperfect device matching
discrepancies in the behaviour of nominally identical devices. The most
straightforward manner to estimate the sensitivity to device matching is prob-
ably to estimate the unwanted mixing products by simulating the basic building
block. The most important the unwanted products, the more stringent the re-
quirement on matching will be. Simulation of the complete balanced structure
does not reveal this information to the designer, unless some statistical investi-
gation is made by introducing articial discrepancies between devices. This is
however much more computationally intensive than the simulation of the basic
building block. Furthermore, simpler circuits are naturally easier to interpret.
The following subsections concentrate thus on simplied single FET mixers.
Simulation results are presented based on the SOI MOSFET model developed
in chapter III with the parameters extracted in chapter IV.
V-2
V.2.1 Active mixers
The operating principle of active mixers is that the transconductance of the
device is pumped by a large LO signal to achieve parametric conversion of the
RF signal to the intermediate frequency.
I
DS
(t) = I
DS(DC)
+ G
m
(t) V
RF
(t) (V.1)
In a conventional down-converter, the fundamental-frequency component of
the transconductance is used for mixing. Maximising this frequency compo-
nent of the transconductance optimises the gain, noise gure and minimises
intermodulation distortion. The fundamental LO-frequency transconductance
component is maximised when the transconductance waveform is a rectangular
pulse train having a 50 % duty-cycle.
IF Filter
LO/RF Diplexer
LO
RF
IF
Source
Drain
Gate
Figure V.1: The gate-driven transconductance mixer. The diplexer combines
the LO and RF signals providing impedance matching and mutual isolation to
the generators. The IF lter suppresses the strong LO component present in
the drain current.
Pumping of the transconductance G
m
can be achieved by applying a large
LO signal in the following ways :
1. LO at the gate terminal of the device in saturation. This is, according
to Maas, [V.1], the most favourable case, capable of the highest conver-
sion gain. The gate is biased close to the threshold voltage so that the
transconductance waveform approximates a half-sinusoidal pulse train,
which is as close to the optimum waveform as one can achieve in prac-
tice.
2. LO at the source of the device in saturation, with the gate biased at the
threshold voltage. The presence of a load impedance the LO generator
impedance in the source of the transistor reduces the fraction of the
RF signal exciting the transistor, lowering the conversion gain.
3. LO applied at the drain of the transistor operating in triode regime. The
gate is biased well above threshold in order to keep the transistor at all
times in the triode regime, independently of the LO signal. The triode
regime transconductance being smaller than in saturation, the conversion
gain is naturally smaller.
V-3
In all three cases the IF signal is collected at the drain. The RF signal
is generally injected in the gate as this allows to obtain a power-conversion
gain. Maas, [V.1], proposed the following expression for the conversion gain of
case 1 :
A
conv

P
L(IF)
P
G(RF)
Re(Z
L(IF)
) Re(Z
G(RF)
)
G
m
(max)
2
8
1 +
(RF)
C
GfSi
_
Z
G(RF)
+ R
Gfe
+ R
Se
+ R
GfSi
_
2
(V.2)
where P
L(IF)
is the power delivered to the IF load; P
G(RF)
is the power available
from the RF source; Z
G(RF)
and Z
L(IF)
are the impedances loading the input
of the mixer at RF and its output at IF, respectively. G
m
(max)
is the peak
transconductance and the other parameters are circuit parameters dened in
chapter III. The eect of the parasitic gate capacitances C
GfSe
and C
GfDe
has
been neglected.
Equation (V.2) implies that the conversion gain of the gate-driven active
mixer can be made arbitrarily large by selecting a high value for R
L(IF)

Re(Z
L(IF)
). Limitations to the achievable conversion gain stem mainly from
the fact that a high value for R
L(IF)
will generate amplier-mode gain at the IF
frequency. Any out-of-band or noise signal present at the IF frequency on the
RF node will be amplied and superimposed on the wanted IF signals. Practical
implementations target a conversion gain around 0 dB, to avoid sacricing to
much of the noise gure due to amplier-mode gain, [V.1].
Maintaining the transistor in saturation, or at least applying a substantial
bias voltage on the drain has several eects. The elevation of temperature
inside the device due to DC power dissipation is responsible for the high level
of diusion noise. Velocity saturation and channel-length modulation eects are
responsible for the high harmonic content of the drain current. On the other
hand, the presence of a strong DC longitudinal electric eld in the channel
limits the inuence of NQS eects on the conversion gain. Carriers are indeed
swept at maximum speed through the channel, allowing fast changes in the
inversion charge density to occur in response to the LO stimulus.
Using equation (V.2) the inuence of NQS eects on the conversion gain of
gate-driven single MOSFET mixers can be investigated. In a given technology,
using the minimal available channel length, it is always possible to design a
mixer with a specied conversion gain A
conv(max)
for a determined LO level,
provided the RF and LO frequencies are suciently low. It therefore suces to
choose a sucient total device width, yielding the proper value of G
m
(max)
.
Using the scaling rules, the evolution of the conversion gain in function of the
RF frequency can be expressed by :
A
conv
(
(RF)
) A
conv(max)

1 +
(RF)
_
_
8 A
conv(max)
R
L(IF)
/R
G(RF)
1
Ti
+
Gfe
+
Se
+
GfSi
_
2
(V.3a)
V-4
LO Frequency Conversion Gain 3
rd
Harmonic
P
L(IF)
P
G(RF)
P
L(H
3
)
P
2
G(LO)
P
G(RF)
GHz dB dB
2.0 17.1 29.1
4.0 18.0 25.6
8.0 20.0 31.0
12.0 22.8 37.5
16.0 25.8 42.2
Table V.1: Detailed results of harmonic balance simulations of the single device
transconductance mixer. The IF frequency is 10.0 MHz. The LO drive is a
1.4 V peak-to-peak sinusoid. The mixer loads are 50.0 resistors. The gate is
biased at 0.3 V, the drain at 2.0 V. The transistor is a 10 (24.0 m/1.0 m)
nMOSFET.
where the following denitions apply :
Ti

G
m
C
GfSi
(V.3b)
Gfe
C
GfSi
R
Gfe
(V.3c)
Se
C
GfSi
R
Se
(V.3d)
The RF and IF load impedances were assumed to be real :
Z
F(RF)
= R
G(RF)
and Z
L(IF)
= R
L(IF)
(V.3e)
Ti
corresponds to the intrinsic current-gain cut-o frequency of the transistor.
Gfe
is xed by the layout design and is kept to a minimum as the C
GfSi
R
Gfe
product controls the attenuation of the gate signal along the gate nger see
section III.6.3.
Gfe
is thus virtually independent of the total device width
and hence of A
conv(max)
.
Se
is depends solely on the bias conditions and the
technological parameters, not on the device width or the specied A
conv(max)
.
GfSi
is the NQS charging delay of the gate-source capacitance.
Harmonic balance simulations were performed to assess the validity of equa-
tion (V.3). The NQS analytical current and charge model with 3 channel
sections was used to simulate a single device transconductance mixer with
the LO drive applied to the gate and loaded by 50 resistors. The MOS-
FET was the 10 (24.0 m/1.0 m) n-channel device considered in the ex-
tractions of chapter IV. The simulation results summarised in table V.1. Us-
ing A
conv(max)
= 16.0 dBm in equation (V.3), yields a 6.0 dB-frequency of
12.0 GHz, which agrees well with the data of table V.1.
V-5
IF Filter
LO Matching
LO
RF
IF
Source
Drain
Gate
RF Filter
Figure V.2: The resistive mixer.
V.2.2 Passive mixers
Passive mixers, often called resistive mixers, use the variation of the channel
conductance to perform the parametric conversion of the RF signal to the IF
frequency. The MOSFET is biased in strong inversion at V
DS
= 0, and the LO
is applied to the gate. The bias conditions are chosen so that operation in the
linear triode regime is ensured at all times, independently of the RF and
LO signals. The RF signal is applied to one end of the channel and IF currents
are ltered indierently from the same or the opposite end.
I
DS
(t) = G
Di
(t) V
RF
(t) (V.4)
The primary advantage of the resistive mixer is its very low-levels of in-
termodulation distortion. Velocity saturation and channel length modulation
which are the primary source of distortion in active mixers do not appear in
resistive mixers. The absence of DC current implies that resistive mixers ex-
hibit very low noise levels : As very little power is dissipated inside the device
the channel is nearly at room temperature so that the level of diusion noise
is low; Furthermore shot noise is also minimal in these conditions.
On the contrary to the active mixer, where the intrinsic gate-drain ca-
pacitance is nearly zero, in the resistive mixer, the intrinsic source and drain
capacitances C
GfSi
and C
GfDi
are equal. This means that, when the LO fre-
quency is suciently high, an important LO leakage will occur across the C
GfDi
capacitance. Balanced structures remedy to this problem, by creating virtual
grounds at the source and drain with respect to the dierential LO signals. A
double balanced resistive structure is presented in subsection V.3.2 below.
Another potential problem of the resistive mixer is the absence of a strong
longitudinal electric eld in the channel. This means that the velocity of carriers
is limited, so that one may fear a degradation of the conversion gain due to
NQS eects. Harmonic balance simulations have been performed on a SOI n-
MOSFET with a nominal channel length of 1.0 m and a total width of 240 m.
The transistor was biased with 2.0 V at the gate. The loads of the mixer were
50 resistors. The results are summarised in table V.2. They show that the
V-6
LO Frequency Conversion Gain 3
rd
Harmonic
P
L(IF)
P
G(RF)
P
L(H
3
)
P
2
G(LO)
P
G(RF)
GHz dB dB
2.0 32.2 48.0
4.0 33.0 52.8
8.0 34.8 68.2
12.0 37.0 57.6
16.0 38.9 52.6
Table V.2: Detailed results of harmonic balance simulations of the single
device resistive mixer. The IF frequency is 10.0 MHz. The LO drive is a
1.4 V peak-to-peak sinusoid. The gate is biased at 2.0 V. The transistor is a
10 (24.0 m/1.0 m) nMOSFET.
conversion gain decreases at a rate of 8.0 dB/ decade which is not excessively
high and even compares very well with the results of the active mixer. One
may thus conclude that NQS eect do not degrade the conversion gain of the
passive mixer more than they do in the case of the active mixer.
The conversion gain of the resistive mixer is 15 dB lower than the conversion
gain of the transconductance mixer based on the same transistor and loaded
similarly. The level of third harmonic lies in the case of the resistive mixer 20 dB
below the level reached in the transconductance mixer. It can be seen from the
evolution of the level of the third harmonic in function of LO frequency that
the resistive mixer is subject to stronger capacitive harmonic distortion than
the transconductance mixer. The dip in the third harmonic around 46 GHz
is due to a compensation between conductive and capacitive distortion. Above
these frequencies capacitive distortion dominates.
V.2.3 The MOSFET switch
A single-MOSFET switch can be used as a mixer. Its operation principle is
that the RF current is sampled at the LO frequency, generating a IF signal on
some load. Such a mixer is a form of compromise between the active and the
passive mixer, widely used in balanced active mixer congurations.
The gate of the MOSFET is biased around the threshold voltage as in the
case of the active mixer. A suciently strong LO signal is applied to the gate
so that the transistor is switched on and o during a LO cycle. The transistor
must be designed large enough to ensure linear operation when it is turned on
and to minimise its on-state resistance. A non-zero DC bias voltage is usually
applied to the drain in order to enhance the switching speed an minimise the
switching transient. The RF current is then fed in source and the IF signal is
collected at the drain.
Neglecting the inuence of the drain-gate capacitance at the IF frequency,
V-7
the relationship between the RF current and the IF voltage can be expressed
according to Rofougaran, [V.3], as :
V
L(IF)
=
1
Z
L(IF)
1 +
RF
C
GfSi
_
R
DSi
+ Z
L(IF)
_I
G(RF)
(V.5)
As will be shown in section V.3.1 below, pratical implementations of this mixer
use a transconductance stage to feed the RF current to the switch.
The chopping mixer presented here share several advantages and drawbacks
of active mixers. Its conversion gain can be adjusted at will by choosing proper
values for Z
L(IF)
. The chopping mixer does not suer from amplier mode gain
at the IF frequency, as any IF signal fed by the current source is transformed by
the switch into a signal at RF frequency on the IF node. The chopping mixer
does well suer from the high noise and distortion levels of active switches.
V.3 Balanced mixers
In order to enhance the performance of single device mixers, and particularly to
attenuate detrimental eects, multiple identical devices can be used in balanced
congurations fed by dierential signals. These arrangements force unwanted
mixing products to cancel out mutually while preserving the useful signal.
Using dierential signals on symmetrical structures, virtual grounds are created
which allow to enhance the isolation between the LO and the IF terminals.
Figure V.3: The printed circuit board for the characterisation of the packaged
mixer chips. On the top the dierential LO and RF signals. At bottom the
dierential IF signals.
V-8
V.3 Balanced mixers
Generation of dierential signals is a key problem in the successful imple-
mentation of integrated balanced mixers. Several solutions exist :
1. Passive generation of the dierential signal using coupled planar induc-
tors organised as a transformer with the secondary winding grounded at
midpoint.
2. Active generation using transistors, typically in an input amplier.
3. O-chip generation of the dierential signals, using baluns or 180 deg
hybrid junctions.
This latter alternative has been applied for all mixer implementations in the
present work. The reasons were that, at the time of design, inductors of suf-
cient quality were not available and very little was known about integrated
CMOS microwave ampliers. As the present chapter focusses on the character-
istics of the mixing cells themselves, it was found more convenient to use high
quality hybrid junctions for all measurements, so that all mixers would be fed
by clean dierential signals.
V.3.1 The Gilbert cell
This cell is named after B. Gilbert who proposed a balanced topology for bipolar
tansistor mixers where a common emitter pre-distortion stage was used to
conpensate for the distortion of the actual balanced mixing stage, [V.4]. His
design exploits specic features of the exponential transfer function of bipolar
transistors. The distortion compensation feature does not apply to FETs in
general, but balanced FET cells share the topology of the Gilbert cells proper
and are widely designated as Gilbert cells.
V
IF+
V
IF
V
LO
V
LO+
V
LO+
V
RF+
V
RF
Transconductance stage
Switches Switches
V
DD
V
DD
IF loads
Figure V.4: A balanced active MOSFET mixer : the Gilbert cell
V-9
Several authors reported using switching MOSFET Gilbert cells for mo-
bile communications applications, [V.5,V.6]. Very few solutions using balanced
transconductance MOSFET mixers have been proposed, [V.7,V.8]. Crols, [V.9],
indicated that transconductance MOSFET mixers have in general a limited
linearity which highly depend on device-uniformity matching and that
high-frequency operation can only be achieved at the cost of high current con-
sumption.
Figure V.5: Silicon die of the chopping mixer cell. The RF terminals are the
upper two pads on the right. The LO terminals are the second and third from
the right at the bottom. The IF terminals are on the left-hand side, at the top.
The other bond pads are for DC biasing.
The feasability of SOI CMOS chopping mixers has been investigated. The
architecture proposed by Rofougaran, [V.3], was adapted to the SOI CMOS
technology of the UCL. The mixer cell topology was exactly the one depicted
in gure V.4. An output buer stage was added to allow stand-alone operation
in the 50 measurement environment. The cell was designed to have a 0 dB
conversion gain at 10 dBm LO drive. For a LO and IF frequencies of 1.8 GHz
and 5.0 MHz, respectively, SPICE simulations predicted a 55 mV amplitude of
output IF signal for a 10 dBm RF excitation. Measurement of the packaged
mixers in these conditions revealed a 56 mV amplitude of the IF signal. The
supply voltage was in both cases 4.0 V.
Power Supply IIP3
V dBm
(RF)
2.0 +25.4
2.5 +24.9
3.0 +16.5
3.5 +17.6
3.5 +17.9
Table V.3: Results of IIP3 measurements. The LO level was 10 dBmat 1.8 GHz.
The IF frequency was 5.0 MHz. The third order intermodulation intercept point
IIP3 is characterised in terms of the RF power at the input.
The main purpose of the implementation was to verify the intermodulation
properties of the SOI CMOS chopping mixer. The intermodulation of two
V-10
V.3 Balanced mixers
neighbouring RF signals was characterised by measurement of the third order
intermodulation intercept point IIP3 at the IF frequency. The measurements
were repeated at various supply voltage levels.
The intermodulation results listed in table V.3 are encouraging. The in-
put power levels corresponding to the third order intercept point are at least
10 dBm higher than the results published by Rofougaran in [V.3] for a 3.0V
power supply and a LO frequency of 1.0 GHz. The value given by Rofougaran
combines however the intermodulation of the mixer and the low-noise ampli-
er. These measurement results again conrm that an SOI technology enables
CMOS designs to function at higher frequencies ...
V.3.2 The resistive ring
V
IF+
V
IF
V
LO
V
LO+
V
RF+
V
RF
Figure V.6: A balanced resitive mixer : the ring.
Song, [V.7], and Crols, [V.9], proposed to use balanced resistive bulk MOS-
FET mixers to overcome the limitations of active mixers at high-frequencies.
Crols mentioned very low distortion, low noise and zero power consumption as
the major advantages of resistive ring mixers. The use of the double balanced
structure shown in gure, allows to cancel the eect of common-mode DC bi-
asing signals as well as the nonlinear dependence of G
Di
on the drain voltage.
Crols pointed out that mismatches in the device characteristics have little eect
as long as the LO is applied to the gates. Mismatches let indeed a quadratic
term function of the gate signal appear at the IF terminals. If the RF was
applied to the gate, several parasitic signals would appear in the baseband due
to the quadratic detection. The squared LO signal results however only in a
DC component which will not interfere with the baseband signals.
Crols achieved high-frequency performance with resistive rings by using
minimal transistor sizes for the MOSFETs and a high value for V
Gf
V
Thf
.
This allowed to have a reasonably low channel resistance at the cost of little
V-11
capacitance, maximising the bandwidth. Using minimal sizes is however not
favourable from the point of view of uniformity of device characteristics. It
is indeed better to use larger devices and to perform a space averaging of the
characteristics by combining separate active regions to obtain the desired total
width. The simulations performed in section V.2.2 showed that the frequency
variation of the conversion gain of a resistive mixer based on a SOI n-MOSFET
with a 1.0 m nominal channel length were even slightly better than for the
active mixer. NQS eects are not too severe and one could depart from minimal
transistor sizes to lower the V
Gf
V
Thf
and render the design more robust to
process variations.
Figure V.7: Silicon die of the resistive mixer cell. On the left, the LO terminals;
On the top, the dierential IF (left) and RF (right) terminals.
Resistive ring structures were designed to operate in the 50 measurement
environment, in order to allow characterisation of their intermodulation per-
formance and to conrm their ability to function at high-frequencies. Resistive
mixers fabricated at Electronique Marin were measured at 1.8GHz with a
LO drive of +10 dBm. The maximum conversion was obtained at a gate bias
around 1.0 V and was 29.0 dB, relatively close in fact to the predictions from
computer simulations mentioned in subsection V.2.2. The simulations are how-
ever intended for the UCL technology which uses silicides for the lowering of
series resistances on the contrary to the technology at Electronique Marin.
DC gate bias IIP3
V dBm
(RF)
1.0 +40.1
1.5 +35.1
2.0 +41.2
Table V.4: Results of IIP3 measurements. The LO level was 10 dBmat 1.8 GHz.
The IF frequency was 5.0 MHz. The third order intermodulation intercept point
IIP3 is characterised in terms of the RF power at the input.
The results summarised in table V.4 are in good agreement with what is
commonly expected for resistive mixers in the literature, [V.1,V.9]. The conver-
V-12
V.4 A low-IF down-conversion architecture
sion gain was not found to vary importantly over the measurement bandwidth,
from 1.0 GHz to 2.0 GHz, conrming that SOI resistive mixing cells have a good
potential for microwave applications. The exceptional linearity of the resistive
cell is a distinctive advantage for the implementation of receivers in mobile
communication systems. In the mobile environment, multi-path propagation
or atmospheric perturbations can cause substantial signal fading, requiring the
receiver to have a large dynamic range. A high linearity of the mixer is impor-
tant with this respect.
Crols performed an extensive comparison of existing down-conversion architec-
tures in his thesis, [V.10]. The existing solutions, the conventional IF receiver
and the zero-IF are analysed and an alternative solution is proposed, the low-IF
architecture, which can be fully integrated on a single chip.
In the conventional IF receiver a microwave preselection lter is used to
avoid folding unwanted signals back on to the desired one during the
down conversion to IF. The IF frequency is dictated by the bandwidth
of the preselection lter. Typical values are 10 to several hundred MHz.
The rejection of the signal at the image frequency is performed at IF were
narrow lters can be realised in o-chip technology. The signal is then
nally converted to the baseband and detected. This system architecture
requires thus at least three chips : a microwave chip, a IF lter chip and
the IF and baseband chip.
In the zero-IF solution, [V.5], the RF signal is down-converted directly
to origin of the frequency axis, using a quadrature conversion scheme. In
this scheme the baseband signal is represented by a pair of signals, the
in-phase signal, I and the quadrature signal, Q. The wanted signal can
then be reconstructed by summing the I and Q signals. Substracting the
signals would yield the image. A simple low-pass lter is used to perform
the channel selection after the down-conversion. This architecture can
be fully integrated on a single chip but it is highly sensitive to parasitic
baseband signals like DC oset voltages, second order distortion products
and self-mixing products, [V.11].
In the low-IF solution, [V.10], the RF signal is translated directly to a
low IF frequency using the quadrature down-conversion scheme. Low-
frequency signal processing most likely digital processing can then
be used to retrieve the wanted signal from the I and Q representation.
This architecture resolves the problem of sensitivity to parasitic DC sig-
nals. Its overall performance is however dependent up on the accuracy of
the phase relationships between the quadrature LO and RF signals. The
quadrature generation circuits are thus key components of the design.
According to Crols, [V.11], phase errors must lie below 0.5
.
V-13
The architecture of the low-IF solution is presented in gure V.8. This so-
lution has been chosen for implementation in the UCL technology as a demon-
strator. It allows proper evaluation of the downconverter on its own, on the
contrary to the zero-IF solution which must be coupled to baseband signal
processing in order to cancel the unwanted DC parasitic responses.
The two most important sub-assemblies have been implemented separately
to test their individual performance : The basic IF cell, consisting of a single
mixer, the low-pass lter and the IF amplier, and the passive quadrature
generation lter.
RF
LO
Q
LO
I
LO
I
RF
Q
RF
I
IF
Q
IF
IF Amplier
IF Amplier
90
90
Mixers
Low-pass Filter
Low-pass Filter
+
+
+
Figure V.8: The low-IF downconverter architecture
V-14
V.4.1 Basic IF cell
A basic IF cell has been designed for stand-alone operation. The design uses
the resistive ring mixer, based on minimal size n-MOSFETs having a channel
length of 1.0 m and a total width of 6.0 m.
Special care was taken for the implementation of the capacitor C
LP
respon-
sible for the ltering of the unwanted high frequency mixing products. The
resonance frequency of C
LP
must signicantly higher than the rst harmonic
of the LO frequency. Furthermore, the parasitic series resistance must be kept
very low, typically below a few .
The amplier is an operational transconductance amplier designed ac-
cording to the method of [V.12] by J.-P. Eggermont. It was implemented in
a fully dierential topology with active common-mode suppression. The feed-
back around the OTA was designed to ensure a 10 MHz IF bandwidth and an
overall conversion gain for the cell of 20 dB at a 10 dBm LO drive.
RF
LO
IF
Resistive Ring C
LP
R
F
C
F
OTA
Figure V.9: The IF test-cell design
Measurements of the mixer cell at 1.8 GHz under a LO drive of 12 dBm and
a DC power supply of 4.0 V revealed a conversion gain of only 7.0 dB. A further
analysis showed that the common-mode suppression feedback was interfering
with the dierential mode because of a mismatch in the feedback resistors.
V.4.2 Quadrature generation
Crols proposed in [V.10] an enhanced version of the traditional R-C quadrature
generator. It is the passive polyphase lter shown in gure V.10. All resistor
have the same resistance R and all capacitors the same capacitance C. The
lter rejects in-phase signals presented to the input and let quadrature signals
pass through with a 6.0 dB attenuation. It can be congured as a quadrature
generator simply by grounding the input quadrature terminals, Q
i+
and Q
i
.
The center frequency is given simply by f
c
= RC/(2).
The main advantage of the polyphase lter is that it is less sensitive to
process variations and that it allows to obtain an accurate 90
phase dierence
over a wide band : a 0.3
variation in a 100 MHz band around 1.8 GHz.

V-15
I
o+
I
o
Q
o
Q
o+
Q
i+
Q
i
I
i+
I
i
R
C
Figure V.10: The passive polyphase quadrature generator lter.
The practical implementation of the structure was hampered by the low re-
sistivity of the polysilicon layer used to make resistors at the UCL. The parasitic
capacitance of the 500 resistors used in the design attained a very important
fraction of the value required for C. A new layout design was developped wich
allowed to incorporate the parasitic capacitances of the resistors into the the
useful capacitance. The quadrature generator were fabricated but have not
been characterised yet.
I
o+
I
o
Q
o
Q
o+
Q
i+
Q
i
Ground
Polysilicon Resistors
Metal-Polysilicon Capacitors
Figure V.11: The layout of the passive quadrature generator.
V-16
V.5 Conclusion
V.4.3 Evaluation chip
The complete evaluation chip was fabricated, but the chips have not been
encapsulated yet, so that no measurements are available at present.
Figure V.12: Silicon die of the quadrature down-conversion mixer, with from
left to right : the LO and IF quadrature generators, the mixers block, the two
low-pass lters (capacitors), feedback resistors, the two IF-ampliers
V.5 Conclusion
The feasability of microwave SOI MOSFET mixers has been tested and demon-
strated. Resistive SOI MOSFET mixers were shown to enjoy the low-distortion
and large dynamic range which is typical of resistive ring mixers. Harmonic
balance simulation performed with the newly developped analytical current
and charge model revealed that NQS eect do not signicantly degrade the
conversion gain of resistive mixers fabricated in a 1.0 m SOI CMOS technol-
ogy at least not to prohibit the use of resistive rings with LO frequencies
as high as 10 GHz. This is probably the most outstanding original result pre-
sented in this chapter. A complete downconverter has been fabricated and
more measurement results are still to come.
V-17
References
[V.1] L. E. Larson, ed., RF and Microwave Circuit Design for Wireless Com-
munications, ch. Mixers for Wireless applications. London: Artech
House, 1996.
[V.2] R. Goyal, ed., High-frequency Analog Integrated Circuit Design,
ch. Mixers. New York: John Wiley & Sons, 1995.
[V.3] A. Rofougaran, J. Y.-C. Chang, M. Rofougaran, and A. A. Abidi, A 1
GHz CMOS RF front-end IC for a direct conversion wireless receiver,
IEEE J. of Solid-State Circuits, vol. 31, pp. 880889, July 1996.
[V.4] B. Gilbert, A high-performance monolithic multiplier using active
feedback, IEEE J. of Solid-State Circuits, vol. 9, pp. 364373, Dec.
1974.
[V.5] A. A. Abidi, Direct-conversion radio transceivers for digital communi-
cations, IEEE J. of Solid-State Circuits, vol. 30, pp. 13091410, Dec.
1995.
[V.6] A. N. Karanicolas, A 2.7 V 900 MHz CMOS LNA and mixer, in 1996
IEEE Int. Solid-State Circuits Conference, Digest of Technical Papers,
Feb. 1996.
[V.7] B.-S. Song, CMOS RF circuits for data communications applications,
IEEE J. of Solid-State Circuits, vol. 21, pp. 310317, Apr. 1986.
[V.8] H.-J. Song and C.-K. Kim, A MOS four-quadrant analog multiplier
using simple two-input squaring circuits source followers, IEEE J. of
Solid-State Circuits, vol. 25, pp. 841848, Mar. 1990.
[V.9] J. Crols and M. S. J. Steyaert, A 1.5 GHz highly linear cmos downcon-
version mixer, IEEE J. of Solid-State Circuits, vol. 30, pp. 736741,
July 1995.
[V.10] J. Crols, Full integration of wireless transceveir systems. PhD thesis,
Katholieke Universiteit Leuven, Leuven, Belgium, 1996.
[V.11] J. Crols and M. S. J. Steyaert, A single-chip 900 MHz CMOS receiver
front-end with a high performance low-IF topology, IEEE J. of Solid-
State Circuits, vol. 30, pp. 14831492, Dec. 1995.
[V.12] F. Silveira, D. Flandre, and P. G. Jespers, A g
m
/I
D
based method-
ology for the design of CMOS analog circuits and its applications to
the synthesis of a silicon-on-insulator micropower OTA, IEEE J. of
Solid-State Circuits, vol. 31, pp. 13141318, Sept. 1996.
V-18
Conclusion
This work presented a comprehensive and innovative approach to the modelling
of SOI MOSFETs at microwave frequencies.
An accurate small-signal characterisation procedure was setup on the basis
of scattering parameters measurements. In-situ calibration was introduced as
an ecient de-embedding technique, allowing to circumvent the limitations of
the widely used immittance correction technique. The importance of proper
determination of the reference impedance of S-parameters on-wafer calibra-
tions was revealed, and two original determination methods were proposed :
The load measurement method, which proceeds by comparison of the DC and
RF characteristics of a resistor, and the calibration comparison method, which
extracts information about the impedance transform from the T-matrices re-
lating two successive calibrations. The load measurement method was applied
for validation purposes to the determination of the characteristic impedance of
a coplanar waveguide section : The results turned out to agree very well with
both computer simulations and experimental determinations of the character-
istic impedance, evaluated in the quasi-TEM approximation. In practice, the
application of the calibration comparison method proved to be more compli-
cated than that of the load measurement, so that the latter method has been
preferred. Combined with the rigorous TRL calibration technique, the new
reference impedance determination method contributed to achieve reliable on-
wafer measurements of admittance and impedance parameters up to 40 GHz,
with simple calibration structures implemented in a standard 1.0 m CMOS
process.
A large signal current and charge model was developed for the SOI n-channel
MOSFET with the specic needs of analogue microwave circuit design in mind.
Special attention was devoted to channel propagation delays, to short channel
eects and to the dispersive behaviour of the interface traps. Multiple channel
sections were introduced to simulate channel propagation delays. It was shown
that, in the case of 1.0 m SOI MOSFETs, three channel sections are sucient
to account properly for these non-quasi-static eects up to 40 GHz. A semi-
analytical model of the saturation region has been used to evaluate the eective
1
Conclusion
channel length shortening in saturation. Drain-induced barrier lowering, the
second signicant short-channel eect aecting UCL SOI MOSFETs, has been
modelled by a threshold voltage correction. These enhancements allowed to ex-
tend the validity of the charge-sheet model to submicrometer devices. Specic
state variables controlled by a rst order dierential equation were introduced
in order to mimmic the dispersive behaviour of the interface traps, enabling the
unied treatment of DC and RF characteristics. To ensure the continuity of
all bias-dependent characteristics across several operating regimes, the model
relies on two innitely derivable interpolation functions : one for the prediction
of the inversion charge from depletion to strong inversion, a second for the tran-
sition from the linear regime into saturation. The curent and charge model was
coded in C and integrated into the OSA software for harmonic balance circuit-
simulation and optimisation. The implementation proved suciently ecient
to allow on-line small-signal simulation and optimisation. Two-tone harmonic
balance simulations using fteen discrete frequencies were conducted o-line,
and lasted typically less than one hour on a Sun SPARK station.
Dedicated small-signal models for the intrinsic SOI MOS device were also
presented : An adaptation to SOI of the high-frequency small-signal model
proposed by Tsividis for bulk MOSFETs, and an original distributed channel
model for SOI MOSFETs at V
DS
= 0. Finally, an elaborate small-signal equiv-
alent circuit model was devised for parasitic eects such as substrate coupling,
capacitive gate-diusions coupling, series resistances and residual interconnec-
tion lengths at the input and output of the device. This extrinsic small-signal
model constitutes an indispensable complement to the intrinic models either
the analytical current and charge model or the dedicated small-signal models
for the prediction of the microwave behaviour of the MOSFET.
The proposed models were confronted to measurements. Several new S-
parameters based extraction techniques were developed, allowing to identify
model parameters in a way which proved coherent with established physical
interpretations. This was specically the case for the series resistances, the
parasitic gate capacitances, the threshold voltage, the channel length and the
transport model parameters. The available extraction techniques were com-
bined in a comprehensive procedure allowing the progressive identication of
the majority of model parameters; Only a few well-controlled technological pa-
rameters were assumed to be known a-priori. At the beginning of the extraction
procedure, a simplied three-terminal small-signal model of the MOSFET is
used. Starting with the determination of adjacent and extrinsic parasitic cir-
cuit elements, the extraction proceeds inward with the identication of the
series parasitics. Then the complete four-terminal model is introduced and the
substrate coupling parameters are identied. Finally, the current and charge
model is substituted to the intrinsic part of the small-signal equivalent cir-
cuit, and its internal parameters are identied : inversion-charge parameters,
transport model and saturation model parameters. All extractions involved in
this procedure were formulated as optimisation problems. In order to extract
each parameter with minimal uncertainty, biasing conditions for the extrac-
tions were carefully selected for an optimal sensitivity of the measurements to
the parameter in question.
2
Two original direct extraction schemes were proposed : one for the identi-
cation of the non-quasi-static small-signal equivalent circuit in saturation and
another one for the determination of the channel capacitance and conductance
from broadband S-parameters measurements. These direct extraction methods
enjoy a number of distinctive advantages with respect to their optimiser-driven
counterparts : Initial values are not required, spurious solutions comparable
to local minima in the case of optimisation do not exist. Furthermore, direct
extraction schemes are computationally ecient and can be easily implemented
as automatic routines.
The extensive comparisons of model predictions with measurements pro-
vided condence in the validity of the modelling approach. The analytical
current and charge model was then used to analyse the performance of mi-
crowave mixer designs. The feasibility of resistive SOI MOSFET mixers at
2.0 GHz was established and conrmed by measurements performed on basic
mixing cells. Simulations even showed that the conversion gain of resistive mix-
ers fabricated in a 1.0 m SOI technology did not degrade signicantly above
2.0 GHz, even up to 10 GHz. This conclusion seems to depart from the widely
admitted opinion that NQS eects would force to use deep sub-micron channel
lengths to implement mixers in MOS technologies above a few GHz. The anal-
ysis performed here showed on the contrary that some margin is available to
choose larger channel length allowing to enhance the robustness of the circuit
to process variations typically, a very critical aspect of analogue designs.
This latter result is a good illustration of the benets resulting from the
modelling approach elaborated during this doctorate research. The key features
of this approach are :
1. An accurate de-embedding method, based on rigorous calibration tech-
niques.
2. Physical modelling.
3. Reliable identication of parameters using direct extraction schemes or
selective optimisation.
3
Appendix A
Coplanar waveguides
on SOI
A.1 Introduction
Coplanar waveguides are a key-component for the on-wafer characterisation
of SOI structures. Being truly planar, they are the natural choice for low-
cost fabrication processes. CPWs avoid the complication of precise thickness
control and of through-hole etching which are both mandatory for a micro-strip
technology. CPWs have furthermore the distinctive advantage to be scalable
provided the substrate thickness is sucient. The CPW topology allows the
realisation of simple and ecient transitions to coaxial waveguides, a feature
that fostered the development of on-wafer probes.
The practical realisation of CPWs suers however of several draw-backs.
The ideal CPW structure is unbounded, on the contrary to the micro-strip
structure which occupies a half-plane. In particular, an ideal CPW should
be self-supporting while a MS may rest on a ground-plane or heat-sink. To
adapt the CPW to conventional packaging or handling technologies, a metallic
back-plane may be used. The resulting structure is over-moded, in the sense
that several propagation modes coexist : the wanted coplanar mode and the
unwanted micro-strip-like mode, which may convert to a surface wave, causing
leakage. Another disadvantage of the CPW structure stems from its symmetry.
The CPW can be analysed as a coupled slots system, in which the desired
mode is the odd mode. As soon as the symmetry is perturbed dierent
loads on each slot a mode conversion will occur transferring power from
the odd mode to the unwanted even mode. Solutions used to tackle the mode
conversion problems are presented in section A.2.
A-1
Coplanar waveguides on SOI
(a) (b)
(c) (d)
OX
OY
OZ
Figure A.1: Electric eld lines for the propagation modes of the CPW struc-
ture : (a) CPW mode; (b) Parasitic slot mode; (c) Parasitic MS mode; (d)
Surface wave, propagating along OX. (ac) propagate along OZ.
CPW sections have been used intensively in the present work as basic struc-
tures for the calibration of the vector network analyser. The calibration pro-
cedure described earlier yields both the propagation constant and the char-
acteristic impedance Z
c
of the CPWs as by-products. These parameters fully
characterise the behaviour of the measured CPW structures and contain useful
information about the supporting substrate. A macroscopic model has been de-
veloped which properly accounts for the frequency evolution of the transmission
line characteristics. This model eventually allows to relate these characteristics
to physical parameters and to perform extractions. The model is presented in
section A.3 and the extraction procedure in section A.4.
A.2 Parasitic mode suppression
The parasitic modes described in the introduction may inuence the perfor-
mance of a CPW section in essentially two ways :
1. Leakage, which is the continuous conversion of power from the CPW-
mode to a parasitic mode. When the phase velocities of the modes dier,
the parasitic mode diverges from the axis of the CPW, so that a substan-
tial fraction of the power is lost.
2. Conversion at discontinuities. Conversion to surface waves causes losses
and eventually unwanted coupling between otherwise isolated circuits.
Conversion to parasitic modes of the CPW structure leads to a racing
condition where destructive and constructive interferences modify the
frequency response at the other end of the line.
Both phenomena may be quite harmful for the calibration process. Surface-
waves radiated from a discontinuity or leaking from a section of line will travel
A-2
A.2 Parasitic mode suppression
on the SOI substrate until l they are reected by an obstacle. The reected
signal may then interfere with the wanted signal. This interference will de-
pend upon the surroundings of the measured structure, rendering the basic as-
sumption of consistent error boxes inapplicable. In the presence of signicant
interference from parasitic modes of the CPW structure, the TRL approach
described earlier breaks down : It is indeed based on the diagonal shape of the
22 transmission matrix in the case of a waveguide propagating a single mode.
Jackson published a study of the mode conversion at discontinuities in
conductor-backed CPWs, [A.1]. The author showed that the CPW open struc-
ture can cause very signicant conversion losses : Up to 20% of the incident
power converted to the parasitic micro-strip mode. The CPW short was shown
to behave much better : Less than 0.4% conversion to the micro-strip mode.
Jackson pointed out that these conversion losses could be signicantly reduced
by inserting a low-dielectric-constant material between the original substrate
and the ground plane. Liu and Itoh, [A.2], showed that insertion of a low-
dielectric constant spacer between the substrate and the ground plane can
even suppress leakage, if the thickness of the spacer is sucient.
SOI Wafer
PTFE Spacer
Metal Ring
PTFE Material
Solder Pad
Figure A.2: Teon spacer for the suppression of parasitic modes.
When measuring either passive or active devices on SOI, the DC potential
applied to the wafer back-plane must be controlled. This potential not only
inuences the threshold voltage of MOSFETs, but also the depth of the deple-
tion region under the buried oxide. Insertion of a dielectric spacer in between
the SOI wafer and the supporting metal chuck must be somehow reconciled
with the necessity to set the back-plane potential. The solution adopted is
shown in the gure. A 0.5 mm thick Duroid spacer is used, with a metal ring
allowing to contact the bottom of the SOI wafer. The spacer material is PTFE
with a relative dielectric constant of 2.33.
A-3
A.3 Macroscopic model for CPWs on SOI
The macroscopic model is based on the analogy between the waveguide the-
ory outlined in a previous chapter and conventional transmission line theory.
Brews, [A.3] proposed to dene a distributed equivalent circuit for the waveg-
uide using equations from transmission line theory :
Z
= Z
c
(A.1)
Y
= /Z
c
(A.2)
Marks, [A.4], derived the following explicit expressions of Z
and Y
in terms
of the modal elds directly from the Maxwells equations :
C

Im(Y
=
1
V
c
2
_
_
S

e
t
2
dS
_
S

h
z
2
dS
_
(A.3)
L

Im(Z
=
1
I
c
2
_
_
S

h
t
2
dS
_
S

e
z
2
dS
_
(A.4)
G
Re(Y
) =

V
c
2
_
_
S

e
t
2
dS +
_
S

h
z
2
dS
_
(A.5)
R
Re(Z
) =

I
c
2
_
_
S

h
t
2
dS +
_
S

e
z
2
dS
_
(A.6)
where + and + . 5 is the waveguide cross-section, extending up
to the point where all elds vanish. These expressions are fairly general : They
apply both to open or closed structures, consisting of eventually lossy materials.
Metal conductivity is not accounted for explicitly but instead absorbed in .
The parameters C
, L
, G
and R
depend on the same normalisation that

determines the magnitude of the characteristic impedance Z
c
. Marks states
in [A.4] that, for instance, when V
c
is chosen to be the voltage between two
active conductors in a lossless TEM line, then C
and L
are the conventional

capacitance and inductance per unit-length. Furthermore, certain combina-
tions of these parameters, notably G
/ ( C
), R
/ ( L
), (R
), (R
),
(L
) and (L
) are normalisation independent. This latter feature is of

particular importance, as it opens the possibility to extract physical parame-
ters directly from adequate combinations of the distributed transmission line
parameters.
The formal denitions of C
, L
, G
and R
in equations (A.3) to (A.6)

do not imply that these parameters are independent of frequency. In the case
of SOI CPWs all of the distributed line parameters vary substantially in the
band from 40.0 MHz to 40.0 GHz. It is the purpose of the next subsections to
develop physically based equivalent circuit topologies which properly account
for the frequency behaviour of Z
and Y
.
A.3.1 Distributed shunt admittance
The eld distribution of the fundamental CPW mode is quasi-TEM which
is known to be a particular case of the TM modes, [A.5]. This amounts to
A-4
say that the longitudinal magnetic eld component h
z
is zero, so that the
evaluation of Y
= G
+ C
according to equations (A.3) and (A.5) reduces

to the contribution of the quasi-static term the

e
t
integral.
Si
Si O
2
C
subs
R
subs
C
box
C
air
W
cntr
W
slt
W
gnd
t
d
t
met
t
box
t
subs
Figure A.3: Cross-section of a SOI CPW structure showing electric eld lines.
A glance at the electric eld distribution in the SOI CPW structure shown
in gure A.3.1 reveals that electric eld lines can be split into three categories :
1. Field lines crossing the eld oxide and penetrating into the air region on
top of the wafer.
2. Field lines contained exclusively in the oxide region enclosing the conduc-
tors.
3. Field lines crossing the buried oxide and penetrating into the silicon sub-
strate.
R
subs
C
subs
C
box
C
air
Figure A.4: Equivalent circuit model for the distributed admittance of a CPW
on SOI.
Neglecting the dielectric losses which may exist in the Si O
2
layer, the con-
tribution of the eld lines in the oxide and in the air to the lineic admittance
may be modelled as a capacitor C
air
. The contribution of the electric eld lines
A-5
penetrating into the substrate is modelled as the series connection of a capac-
itor C
box
for the buried oxide layer with C
subs
and R
subs
for the underlying
silicon.
10
7
10
8
10
9
10
10
10
11
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Frequency [Hz]
C
_
fF/m
1.0
10
7
10
8
10
9
10
10
10
11
0
2
4
6
8
10
Frequency [GHz]
G
_
/m
Figure A.5: Comparison of the measured (dotted line) and modelled (contin-
uous line) distributed admittance curves after parameter extraction on a SOI
CPW.
Values for the capacitances may be approximated using formulas available
for the canonical CPW topology : C
0
is the capacitance of the CPW structure
in the absence of any dielectric material. C
box
is evaluated using the parallel
plate approximation. For the evaluation of C
subs
the thickness of the oxide
layers is set to zero in order to fall back to a standard CPW topology.
C
0
=C
CPW
_
W
cntr
, W
slt
, W
gnd
[ t
d
0, t
box
0, t
subs
0
_
(A.7)
C
air
=C
CPW
_
W
cntr
, W
slt
, W
gnd
(t
d
+ t
box
), t
met
[ t
subs
0
_
1/2 C
0
(A.8)
C
box
=

Si0
2
t
box
W
cntr
W
gnd
W
cntr
+ W
gnd
(A.9)
C
subs
=C
CPW
_
W
cntr
, W
slt
, W
gnd
, t
subs
[ t
d
0, t
box
0
_
1/2 C
0
(A.10)
where C
CPW
() is the functional corresponding to the evaluation of the dis-
tributed capacitance of the canonical CPW see gure A.1 (a). R
subs
can be
deduced from C
subs
and the substrate resistivity using the following equation :
A-6
C
subs
R
subs
=
C
subs
G
subs
=

Si
subs
(A.11)
A.3.2 Distributed series impedance
Here too, the contributions of various regions to Z
= R
+ L
are estimated
on the basis of equations (A.4) and (A.6). As indicated earlier, the CPW
mode is of the TM-type, so that contributions from both

h
t
and e
z
must be
taken into account. For the distributed resistance the magnetic are totally
negligible ( 0) so that only contributions from conductive regions count
dielectric losses in the oxide are very small and will also be neglected. These
considerations allow to write :
R
=
1
I
c
2
_
_
S
met
e
z
2
dS +
_
S
subs
e
z
2
dS
_
R
[S
met
]
+ R
[S
subs
]
(A.12)
where 5
met
is the metal cross-section and 5
subs
is the substrate region. This
equation reveals that the frequency evolution of R
is determined by at least
by two independent phenomena : The skin eect in the metallisation and the
dielectric transitions of the SOI structure. These two eects will also inuence
L
, but the dependency is not as obvious :

L
=
1
I
c
2
_
_
S
met
_

h
t
e
z
2
_
dS +
_
S
c
met
_

h
t
e
z
2
_
dS
_
L
[S
met
]
+ L
[S
c
met
]
(A.13)
where 5
c
met
= 5 5
met
.
The skin eect is related to the nite penetration of electric and magnetic
elds into metallic material at high frequencies. In the case of plane metallic
conductors, an analytical treatment is feasible starting from Maxwells equa-
tions, [A.5, A.6]. Ramo et al. derived in their book [A.6] an expression for the
internal impedance of a metal sheet of innite extent :
z
met
=
1 +

met
cotanh(
1 +
met
t
met
) (A.14)
met
=

(A.15)
z
met
is an impedance per square that must be divided by an eective width to
obtain a value of the conductor impedance accounting for the current crowding
A-7
at the edges of the slots :
Z
[S
met
]
=
z
met
W
e
(A.16)
W
e
= 16
_
W
cntr
+ 2 W
slt
_
K(s)
_
1 s
2
_
_
2
s
_
+ log(
4 W
slt
t
met
1 s
1 + s
)
_
+ 2
_
+ log(
4 (W
cntr
+ 2W
slt
)
t
met
1 s
1 + s
)
__
(A.17)
where s is the normalised slot width : s W
slt
/(W
cntr
+2W
slt
). The expression
for the eective width was deduced from the current densities obtained by
conformal mapping in the case of ground conductors of innite extent, [A.7].
At low frequencies equation A.14 can be approximated by a series expansion
so that (A.16) simplies to :
Z
[S
met
]

1 +

met
W
e
_
1
(1 + ) t
met
/
met
+
(1 + )
2
t
met
/
met
3
O((t
met
/
met
)
2
)
_
=
1
t
met
W
e

+
t
met
3 W
e

3
2
. . .
(A.18)
In the case of a 1.0 m thick sheet of aluminium this approximation is accurate
up to 6.0 GHz within 5.0%. At this frequency the skin depth is on the order of
the metal thickness. Above this frequency the internal metal resistance starts
to increase, while the internal inductance decreases.
At the time of writing no simplied technique has been established to eval-
uate Z
[S
c
met
]
accurately. The contribution of e
z
is the main diculty. The

h
t
term corresponds indeed to a quasi-static evaluation of the distributed induc-
tance, so that equation (A.13) allows to write :
Z
[S
c
met
]
L
CPW
(A.19)
where L
CPW
is the lineic inductance value obtained for the canonical CPW
structure, considering a loss-less silicon substrate and no skin eect.
Comparing the measured evolution of L
() with the predictions for L
[S
met
]
()
suggests that the skin eect in the metal is not solely responsible for the fre-
quency evolution of L
. The skin eect model predicts a frequency of 6.0

GHz for the onset of frequency variations, while the measured curves clearly
show variations occurring before 1.0 GHz. These frequency values correspond
approximately to the dielectric transition frequencies of the substrate. Fur-
thermore, the maximal predicted internal inductance value is almost one order
of magnitude too small to account for the measured changes in L
. Finally,
comparing the frequency evolution of the measured resistance and inductance
A-8
0.4
0.45
0.5
0.55
L
_
pH/m
0.6
10
7
10
8
10
9
10
10
10
11
Frequency [Hz]
2
3
4
5
6
7
R
m/m
10
7
10
8
10
9
10
10
10
11
Frequency [Hz]
Figure A.6: Comparison of the measured (dotted line) and modelled (contin-
uous line) distributed impedance curves after parameter extraction on a SOI
CPW.
curves additional evidence of the substrate inuence is obtained :
R
(6.0 GHz)
[S
met
]
L
(6.0 GHz)

[S
met
]
L
CPW

subs
Si
(A.20)
where the indicates estimations based on the skin eect model described
in the present section; The (6.0 GHz) subscripts indicate measured values
at 6.0 GHz.
L
met1
L
met2
L
met3
R
met1
R
met2
R
met3
Figure A.7: Equivalent circuit model for the distributed impedance of a CPW
on SOI.
Based on the insight gained from the preceding analysis, the empirical model
of gure A.3.2 is proposed. It allows at least to t the measured data satisfac-
torily. Considering the circuit response at high frequency and assuming that
the variation of inductance is due solely to the skin eect, one easily nds that
L
met1
= Z
[S
c
met
]
.
A-9
A.4 Parameter extraction for the circuit mod-
els
The previous section introduced the equivalent circuit models for the dis-
tributed immitances discussing physical aspects and proposing a method to
estimate the parameters. The present section briey describes the procedure
which has been developed to extract circuit parameter values. It is an opti-
misation procedure which adjusts the parameter values to ensure a close t
between the model response and the measured curves. The optimisation strat-
egy proposed by Bandler et al, in [A.8] is used in combination with initial
values obtained from the developments of section A.3. The main feature of the
optimisation strategy of Bandler et al. is that it is well behaved, avoiding to
introduce random errors on parameters with marginal inuence. To dieren-
tiate model responses from measurements or estimated values from actual
eventually unknown values, the former will be indicated with .
A.4.1 Distributed shunt admittance circuit parameters
Initial values for the capacitances are from the expressions in section A.3.1.
As the substrate resistivity is usually unknown a rst estimate for the R
subs
is
obtained from :
subs
(0)
= Re(Y
())
for at the upper end of the band
(A.21)
The circuit response is then tted to the measured Y
curve by minimising the

following error criterion, where T is the parameter space and is the set of
measured frequencies :
min
P
(T,
k
) Y
(
k
)
2
(A.22a)
T p = [C
air
, C
box
, C
subs
, R
subs
, ] R
4
[
0.1 p
(0)
p 10 p
(0)
(A.22b)

min
, . . . ,
max
(A.22c)
The result is shown in gure A.3.1.
A.4.2 Distributed shunt impedance circuit parameters
The procedure used here is slightly dierent. As no expressions are available
to obtain initial values for the circuit elements, except for L
met1
, a step-wise
procedure is adopted. The optimisation framework is described by :
min
P
(T,
k
) Z
(
k
)
2
(A.23)
A-10
A.5 Conclusion
1. A simplifed circuit consisting solely of L
met1
and R
met1
is considered.
Optimisation is performed at the highest measurement frequency :
T p = [L
met1
, R
met1
] R
2
[ 0.1 p
(0)
p 10 p
(0)

max
2. Elements L
met2
and R
met2
are added, and optimisation is performed in
the band starting at a corner frequency located just beyond the sharp
drop of the inductance curve, at the beginning of the at region. The
values obtained for L
met1
and R
met1
are used as initial estimates for
L
met2
and R
met2
.
T p = [L
met1
, L
met2
, R
met1
, R
met2
, ] R
4
[
0.1 p
(0)
p 10 p
(0)

c
, . . . ,
max
3. Finally whole band is considered an all parameters are adjusted. The

values obtained for L
met2
and R
met2
are used as initial estimates for
L
met3
and R
met3
.
T p = [L
met1
, L
met2
, L
met3
, R
met1
, R
met2
, R
met3
] R
6
[
0.1 p
(0)
p 10 p
(0)

min
, . . . ,
max
The result is shown in gure A.3.2.

A.5 Conclusion
This appendix provided an in-depth treatment of coplanar waveguides on SOI
substrates. A physical justication has been found for the frequency evolution
of the measured distributed immitance curves. A macroscopic model has been
developed in the form of equivalent circuits. Simple expressions have been
derived for all distributed admittance parameters, while an original analysis
has been made indicating the dominant role of substrate parameters on the
frequency evolution of the distributed impedance. This should foster the de-
velopment of expressions for the corresponding circuit parameters. Finally, a
successful parameter extraction procedure has been presented, validating the
model topology.
The results of this appendix demonstrate the relevance of the waveguide
circuit topology from [A.4] in general, and the accuracy of the calibration pro-
cedure developed in the present work.
References
[A.1] R. W. Jackson, Mode conversion at discontinuities in nite-width
conductor-backed coplanar waveguide, IEEE Trans. on Microwave
Theory and Techniques, vol. 37, pp. 15821589, Oct. 1989.
A-11
[A.2] Y. Liu and T. Itoh, Leakage phenomena in multilayered conductor-
backed coplanar waveguides, IEEE Microwave and Guided Waves Let-
ters, vol. 3, pp. 426427, Nov. 1993.
[A.3] J. R. Brews, Transmission line models for lossy waveguide interconnec-
tions on VLSI, IEEE Trans. on Electron Devices, vol. 33, pp. 1356
1365, Oct. 1986.
[A.4] R. B. Marks and D. F. Williams, A general waveguide circuit theory,
J. Res. of the Natl Inst. Stand. and Technol., vol. 97, pp. 533562, Sep
Oct 1992.
[A.5] A. Vander Vorst and D. Vanhoenacker, Bases de lingenierie micro-onde.
Bruxelles: De Boeck Universite, 1996.
[A.6] S. Ramo, J. R. Whinnery, and T. Van Duzer, Fields and Waves in
Communications Electronics. New York, London, Sidney: John Wiley
& Sons, 1965.
[A.7] R. K. Homann, Handbook of Microwave Integrated Circuits. Norwood,
MA: Artech House, 1987.
[A.8] J. Bandler and Q.-J. Zhang, An automatic decomposition approach to
optimization of large microwave systems, IEEE Trans. on Microwave
Theory and Techniques, vol. 35, pp. 12311239, Dec. 1987.
A-12
Appendix B
Optimiser-driven
parameter extraction
The parameter extraction problem is often formulated as an optimisation where
model parameters [p
1
, . . . , p
n
] are adjusted until the modelled responses

H
i
(x
k
)
coincides with the measured samples H
i
(x
k
). The x
k
being the sampling points.
The distance between the modelled and measured responses is evaluated using
an appropriate norm :
1. The L
1
-norm is the sum of the absolute values of the error vectors com-
ponents. It
L
1
_
H()

H()
_
i, k
H
i
(x
k
)
H
i
(x
k
)
(B.1)
2. The L
2
-norm is the typical Euclidean norm. It ensures a convergence in
the mean which is a desirable feature in the presence of noise.
L
2
_
H()

H()
_
i, k
H
i
(x
k
)
H
i
(x
k
)
2
(B.2)
3. The Huber-norm, L
Hu
, introduced by Bandler et al. in [B.1], is a com-
promise between L
1
and L
2
. It treats the components of the error vector
according to L
1
above a certain threshold and according to L
2
below.
This ensures a certain immunity to catastrophic errors while maintaining
an adequate behaviour in the presence of noise. The threshold must be
adjusted in function of the noise-level.
B-1
Optimiser-driven parameter extraction
The formulation of the typical extraction problem is then :
min
P
E(T) (B.3a)
E L
2
_
H(T, )

H(T, )
_
(B.3b)
where E is the error criterion and T is the parameter space. In order to avoid
divergence to unrealistic parameter values, the parameter space is restricted to
a range extending one decade above and below the initial value p
(0)
. Unrealistic
divergence of parameters values appears either when the model is inappropriate,
or, more often, when trying to adjust weakly inuent parameters in the presence
of noise. Specifying bounds enhances the detection of these pathologic cases.
T
_
p
_
p
1
, . . . , p
n
R
n
[ 0.1 p
(0)
p 10 p
(0)
_
(B.4)
In order to obtain meaningful results with an optimiser-based extraction
scheme, it is important to suppress any redundancy amongst the optimisation
parameters as well as to avoid adjusting weakly inuent parameters or at
least avoid to place condence in the nal values of such parameters. Through-
out this chapter the optimisation strategy proposed by Bandler in [B.2] is used.
It is based on the elaboration of a sensitivity dictionary which allows to iden-
tify the most inuent parameters and eventually to split the global optimisation
into subproblems when some responses are controlled by independent groups of
parameters. For each subproblem, the optimisation is performed by adjusting
only the most inuent parameters. Once a local optimum is reached, these pa-
rameters are kept constant and some of the remaining less inuent parameters
are chosen to be adjusted during the next optimisation run. This process is
continued until all parameters have been adjusted, so that a fairly good ap-
proximation to the global solution is attained. Then a nal optimisation is
performed and all parameters are allowed to vary. The main advantages of this
optimisation strategy are : that the optimisation is well-behaved, avoiding to
introduce random errors on parameters with marginal inuence; that compu-
tation time is reduced because the intermediate optimisation problems involve
less variables.
After the completion of the optimisation process it is always interesting to
be able to estimate the uncertainties aecting the extracted values. During the
optimisation, the error criterion E rarely converges to 0, but rather to some
nite value R, the residual error. This residue proceeds from two types of
measurement errors :
1. Random uctuations around the mean value of the curves. This type of
error produces a residue in the evaluation of the quadratic error criterion
but does not aect the extracted parameters values. This is a specic
feature of quadratic error norms.
2. Errors which introduce an oset in the mean value of the curves. This
type produces a residue and tweaks the extracted parameters values.
The uncertainty margin U
P
for an extracted parameter P may be estimated
on the basis of the fraction of the total residue which corresponds to the second
B-2
REFERENCES
type of errors, R
M
:
U
P

P

P
=
R
M
S
P
(B.5)
where P stands for the exact value of the parameter while

P is its estimate.
S
P
is the sensitivity of the error norm E to a variation in parameter P :
S
P

E(P + P) E(P)
P/P
(B.6)
However, only the global residue R is available, not its fraction R
M
, so that it
is only possible to specify an upper bound on the uncertainty for the extracted
parameters values :
U
P

R
S
P
(B.7)
References
[B.1] J. W. Bandler, S. H. Chen, R. M. Biernacki, L. Gao, K. Madsen, and
H. Yu, Huber optimisation of circuits : A robust approach, IEEE
Trans. on Microwave Theory and Techniques, vol. 41, pp. 22792287,
Dec. 1993.
[B.2] J. Bandler and Q.-J. Zhang, An automatic decomposition approach to
optimization of large microwave systems, IEEE Trans. on Microwave
Theory and Techniques, vol. 35, pp. 12311239, Dec. 1987.
B-3

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Modelling and Characterisation

of the SOI MOSFET for MMIC Applications

-continuous fully-depleted SOI MOSFET model for analog ap-

Electronique, de Technologie et dInstrumentation

0.5 m Bulk MOSFET

C, at which temperature the implanted

. This latter is the backward propagating mode.

in terms of the modal elds

, the quantity b vanishes. In other words when the generator

together with their known true characteristics,

) is equal to 1. This property may be used to

forces to have identical reference impedances at both

forces the reference impedance to be equal to the charac-

are the physical line lengths measured from end to end, L

theoretically from the waveguide dimensions using

is non-negligible. Furthermore, due to the layered structre of the SOI

varies importantly in the measurement band. An

Figure II.4: Comparing Z

to the carrier velocity and is,

Figure III.13: The distributed eects in the channel at V

-0.5 0 0.5 1 1.5

-continuous fully-depleted SOI MOSFET model for analog

-continuous MOSFET model including subthreshold conduction,

is the admittance matrix obtained directly from the measured S-

is the admittance matrix comprising the shunt adjacent el-

groups the contributions of all series elements. The scaling

combines the shunt intrinsic and extrinsic elements, which

is purely capacitive and depends solely

becomes purely capacitive and depends solely on the extrinsic capac-

rests on the following approxima-

associated to the active zone can be expanded

were dened above. Y

is known to be directly proportional to

is slightly more involved as can be seen in

). In the case of the MOSFETs

and for the set of pulsations

is the admittance matrix obtained directly from the measured scat-

is the admittance matrix describing the shunt adjacent

is the impedance matrix including the series extrinsic

is the admittance matrix accounting for the intrinsic

is assumed to be known, so that Z

have the following form :

1500 1000 500 0

to enhance accuracy, and also that the shared frequency

was known. Indeed, the NQS contributions could be

. The problem is thus now to build correct estimates of Y

using the QS estimate

is the vector of applied gate biases, while C

are the correspond-

accounts for both the shunt extrinsic and

variation in a 100 MHz band around 1.8 GHz.

depend on the same normalisation that

are the conventional

) are normalisation independent. This latter feature is of

in equations (A.3) to (A.6)

according to equations (A.3) and (A.5) reduces

, but the dependency is not as obvious :

() with the predictions for L

. The skin eect model predicts a frequency of 6.0

curve by minimising the

3. Finally whole band is considered an all parameters are adjusted. The

The result is shown in gure A.3.2.

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