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Department of Computer Science and Engineering C23 Computer Organization and Design 3:0

Preamble: This is a course offered in second semester for the students of Computer Science and Engineering. This course is preceded by the course Basics of Electrical and Electronic Engineering in the first semester to students of all branches. This course has two credits dedicated to electronics emphasizing the central role of signal processing. It sensitizes the students to issues of processing signals in digital and analog forms, beyond which students have no exposure to digital logic or function design of digital systems. This is the only course that is concerned with what a computer is at logic and organization level. There is no other course either in digital systems or in computer architecture and design offered to the students of Computer Science and Engineering. It aims to make the student familiar with digital logic and functional design of arithmetic and logic unit that is capable of performing floating point arithmetic operations. The CPU and the organization of memory are explored by tracing the execution of assembly language instructions in a simple hypothetical and a real 32 bit processor. Data needs to be transferred between I/O devices and CPU and between computers. Different processor architectures are needed to meet different performance requirements. Program outcomes addressed a. An ability to apply knowledge mathematics, and science of engineering, information technology,

c. An ability to design a system or component, or process to meet stated specifications f. An ability to communicate effectively in English in both oral and written forms h. An ability to engage in life-long learning Competencies 1. Design simple combinational and sequential digital functions. 2. Perform simple arithmetic operations using registers. 3. Present ASM charts for different arithmetic operations including integer and floating point multiplications and divisions. 4. Design a simple computer at functional level for a given set of specifications. 5. Design an instruction set of a simple computer capable of performing a specified set of operations. 6. Design the structure of registers of a CPU capable of executing a set of specified instructions. 7. Design a memory system for a given set of specifications. 8. Specify architectures using pipelining and paralleling features to improve the performance of computers. 1

Department of Computer Science and Engineering Assessment Pattern Blooms Category 1 2 3 4 5 6 Remember Understand Apply Analyze Evaluate Create Test 1 10 30 40 10 0 10 Test 2 10 10 40 10 10 20 Test 3/Endsemester examination 10 20 40 10 10 20

Course Level Learning Objectives Remember 1. What are the different layers in a computer system? 2. What is an operating system? 3. What are the six major principles which are used by a computer architect? 4. What is MIPS rating of a computer? How is it computed? 5. What is an instruction mix? How is it determined? 6. Name some commonly used synthetic benchmarks? 7. Is Pentium processor a RISC or CISC processor? 8. Is Pentium processor a superscalar or superpipelined? 9. List the advantages and disadvantage of shared memory parallel computers using a bus for sharing memory and an interconnection network for sharing memory? 10. List some representative applications in which MISD processing will be very effective? Understand 1. What is the reason we view a computer system as consisting of several layers? 2. What is the difference between machine language and assembly language 3. What do you understand by the term upward compatibility? important? 4. How many parity bits are required for a double error correcting code for ASCII characters? 5. IBM 370 has no indirect addressing. Explain how one would get the effect of indirect addressing on this machine? 6. Explain in detail the advantages of PC being an addressable register in the CPU? 2 Why is it

Department of Computer Science and Engineering 7. In some computers there are instructions to LOAD specified registers from memory and to STORE a register into memory. In the case of Pentium this is achieved with the MOVE instruction. What are the advantages and disadvantages of these? 8. Explain clearly, as a designer when will you recommend the virtual memory system? 9. Explain how would you use LRU policy in virtual memory system? In what way does it differ from that used in a cache memory? 10. What is difference between instruction mix and statement mix? 11. Is MIPS a meaningful measure of CPU performance? If not, what are its drawbacks? 12. Describe how a floating point add/subtract instruction can be pipelined with a 4stage pipeline. Assume normalized floating point representation in cache? 13. What is the difference between branch prediction buffer and branch target buffer used to reduce delay due to control dependency? 14. How can software methods be used to reduce delay due to branches? conditions should be satisfied for software method to succeed? 15. What is the difference between a loosely coupled and a tightly coupled parallel computer? Give one example of each of this parallel computer architecture? 16. What are the advantages and disadvantages of COW when compared with a message passing parallel computer? Apply 1. Convert the decimal number 92.00625 into a binary number? 2. Convert the binary number 1101.001101 into decimal and octal forms? 3. Obtain an algorithm to find all allowable weights for a weighted BCD code? Assume that all weights are positive integers. 4. Using the postulates of Boolean algebra prove that x.y + x/.z +y.z = x.y + x/.z 5. Multiply the binary numbers 1010 x 0111 using any algorithm you know? Show all steps in calculation 6. Give a combinational circuit to multiply two numbers each of which is 3 bits long and has 1 bit sign? The output should have the right sign and magnitude. 7. Give a combinational circuit using PAL to realize a 4-bit carry look ahead adder? 8. Give an ASM chart for an integer divider for 4-bit operands and express it in HDL? 9. Write assembly codes for floating point multiply and divide. language equivalent. 3 Write machine What

Department of Computer Science and Engineering 10. Assume a memory cycle time of 250 ns, addition time of 90 ns and gate delay of 5 ns. Make a table giving the time required to calculate the effective address in each of the different addressing modes? time for other operation (if you need it). 11. Write a program to compute the dot product of two vectors? 12. A string S is called a palindrome if it reads the same from left to right and from right to left. Using the stack, write a program to test if a given string S is a palindrome or not? 13. A computer has a main memory of 1GB and virtual address is 64bits long. The page size is 4 KB. Give the lay out of TLB you would design? Give the page table layout. How many entries will you have in the page table and why would they be needed? Give the length in bits of each entry? 14. A computer system has a memory hierarchy consisting of a cache memory, main memory and a disk. In a set of bench marks it is found that cache hit ratio is 98%, TLB hit ratio is 90% and page table hit ratio is 95%. Given the access timer of cache is 25 nsec that of main memory is 100 nsec and that of TLB is 5 nsec, estimate the performance degradation with no cache. If TLB is also absent how much will performance degrade? 15. Draw a priority logic and encoder for an interrupt with six interrupt sources? 16. A DMA interface receives 8-bit bytes from a peripheral, packs them in 48-bit word and stores the word in memory. Draw a block diagram of the DM registers and obtain a sequence of micro operations of the DMA? 17. Is DMA given higher priority to access the main memory of a computer compared to CPU? If so why? 18. Assume that the percentage of unconditional branches is 30%, conditional branches 18% and immediate instructions 8% in programs executed in a CPU with 5 pipelined stages. Compute the average clock cycles required per instruction? 19. A vector machine has a 6-stage pipelined arithmetic unit and a 10 ns clock. The time required to interpret and start executing a vector instruction is 60 ns. What should be length of vectors to obtain 95% efficiency on vector processing? 20. A shared memory parallel computer has 128 PEs and shares a main memory of 1 GB using an interconnection network. The cache block size is 64 B. What is the size of the directory used to ensure cache coherence? reducing the directory size? Discuss method s of Assume any reasonable estimate of

Department of Computer Science and Engineering Analyze 1. A byte addressed machine has 256 MB memory. It has 160 instructions and 16 general purpose registers. What is the instruction format if an instruction and 3 GPRs can be addressed? What is the word length of the machine? Is the word size sufficient to represent floating point numbers? If yes, pick appropriate number of bits for the mantissa and exponent. choice. 2. Write a program for SMAC to count the number of zeros in a given 32 bit word. Do you find the instruction set to be adequate? Comment. Trace your program and show that it is correct. 3. Some CPUs include two sets of registers of identical registers for fast switching. In what situations are such duplicate sets very useful? 4. In what ways do the two features macros and subroutines resemble each other and in what ways do they differ from each other? 5. Distinguish between traps and external interrupts? What are the major differences in handling these in a computer system? Evaluate 1. Obtain a single bus micro-engine for SMAC2. Compare this with SMAC1 microengine? 2. Compare and contrast the register structures of SMAC 2 with that of Pentium? 3. Compare different policies available to update cache memory when there is a read or write miss? 4. Make a comparative chart comparing the hardware and software features of programmed data transfer, interrupt based data transfer and DMA data transfer? Create 1. Design a 4-bit shift-right and shift-left serial-in and serial-out shift register? 2. Design a logic circuit which will accept a seven-bit ASCII code for a character and energize one of 128 solenoids to activate a type-bar corresponding to the appropriate character? 3. A computer has 48 bit word length. It has 32 registers. There are 30 instructions which use 3 registers for operands and thee others address main memory. Design at least two possible instruction formats for this computer? In each case give the range of directly addressable memory locations. Justify your

Department of Computer Science and Engineering Concept Map

Lecture Schedule No. 1 1.1 1.2 2 2.1 2.2 2.2.1 2.2.2 2.3 2.3.1 2.3.2 2.4 Topic Processing of Information in Digital form Alphanumeric Data Number Systems Digital Systems Alphanumeric Data Representation Combinational Logic Boolean Algebra Combinational Functions Synchronous Sequential Logic Moore / Melay Machines Memory Elements Registers 1 1 1 2 2 1 1 1 No. of Lectures

Department of Computer Science and Engineering 2.5 2.6 3 3.1 3.1.1 3.1.2 3.2 3.2.1 3.2.2 3.3 3.4 3.4.1 3.4.2 3.5 3.5.1 3.5.2 4. 4.1 4.2 4.3 4.4 5. 5.1 5.2 5.3 6. Counters Shift Registers Processing Unit General Purpose Architecture Control Unit ALU Control Unit Hardwired Control Micro programmed Control Instructions and Instruction Types Instruction Set RISC CISC Special Purpose Architectures DSP Microcontrollers Memory RAM Cache Memories Registers Secondary Memory Interconnection BUS Serial LAN Input / Output Organization 1 1 1 1 1 2 2 1 1 1 1 2 1 1 1 1 1

Department of Computer Science and Engineering 6.1 6.2 6.3 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 Syllabus Processing of Information in Digital form: Alphanumeric Data, Number Systems Digital Systems: Alphanumeric Data Representation, Combinational Logic: Boolean Algebra, Combinational Functions; Synchronous Sequential Logic: Moore / Melay Machines, Memory Elements; Registers, Counters, Shift Registers; Processing Unit: General Purpose Architecture: Control Unit, ALU; Control Unit: Hardwired Control, Micro programmed Control; Instructions and Instruction Types: Instruction Set, RISC, CISC; Special Purpose Architectures: DSP, Microcontrollers; Memory: RAM, Cache Memories, Registers, Secondary Memory Interconnection: Interconnections BUS, Serial, LAN; Input / Output Organization: Program Controlled IO, Interrupts, I/O Processors, Programming: Machine and Assembly Language Programs; Advanced Processor Architecture: RISC, Pipelining, Super Scalar Processors, VLIW, Parallel and Vector Processors Text Book 1. V. Rajaraman and T. Radhakrishnan: Computer Organization and Architecture, Prentice Hall of India, 2007 Program Controlled IO Interrupts I/O Processors Programs Data Machine Assembly Language Programs Advanced Processor Architecture RISC Pipelining Super Scalar Processors VLIW Parallel and Vector Processors 1 1 3 1 1 1