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Assignment 5

The document outlines an assignment for ECE 317 focusing on the design and analysis of 6T SRAM and DRAM cells using CMOS processes. It includes specific questions regarding the performance metrics, design constraints, and operational characteristics of SRAM cells, as well as calculations related to capacitance and signal integrity in DRAM cells. The assignment references a textbook for theoretical support and requires sketches and explanations for certain operations.

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30 views1 page

Assignment 5

The document outlines an assignment for ECE 317 focusing on the design and analysis of 6T SRAM and DRAM cells using CMOS processes. It includes specific questions regarding the performance metrics, design constraints, and operational characteristics of SRAM cells, as well as calculations related to capacitance and signal integrity in DRAM cells. The assignment references a textbook for theoretical support and requires sketches and explanations for certain operations.

Uploaded by

ahmed.120230134
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd

ECE 317 - Electronic Devices Assignment 5 - Memories page 1 of 1

(Reference: Microelectronic Circuits – Sedra/Smith, 7th Edition, Chapter 16)

Q 1. A 6T SRAM cell is fabricated in a 0.13-µm CMOS process for which VDD = 1.2 V, Vt = 0.4 V, and
µn Cox = 500 µA/V2 . The inverters utilize (W/L)n = 1. Each of the bit lines has a 2-pF capacitance
to ground. The sense amplifier requires a minimum input of 0.2 V for reliable and fast operation.

(a) Find the upper bound on W/L for each of the access transistors such that VQ and VQ do not change
by more than Vt volts during the read operation.

(b) Find the delay time ∆t encountered in the read operation if the cell design utilizes minimum-size access
transistors.

(c) Find the delay time ∆t if the design utilizes the maximum allowable size for the access transistors.
Q 2. Consider the operation of writing a 1 into a 6T SRAM cell that is originally storing a 0. Sketch the
relevant part of the circuit and explain the operation. Without performing a detailed analysis, show
that the analysis would lead to results identical to those obtained in the text for the write-0 operation.

Q 3. For a 6T SRAM cell fabricated in a 0.13-µm CMOS process, find the maximum permitted value of
(W/L)p in terms of (W/L)a of the access transistors. Assume VDD = 1.2 V, Vtn = |Vtp | = 0.4 V, and
µn = 4µp .

Q 4. For a 6T SRAM cell fabricated in a 0.25-µm CMOS process, find the maximum permitted value of
(W/L)p in terms of (W/L)a of the access transistors. Assume VDD = 2.5 V, Vtn = |Vtp | = 0.5 V, and
µn = 4µp .

Q 5. Design a minimum-size 6T SRAM cell in a 0.13-µm CMOS process for which VDD = 1.2 V and
Vtn = |Vtp | = 0.4 V. All transistors are to have equal channel length L = 0.13 µm. Assume that the
minimum allowed width is 0.13 µm. Verify that the minimum-size cell meets the constraints given in
Eqs. (5.1) and (5.2).

(W/L)a 1
≤ 2 (5.1)
(W/L)n VDD − Vtn
1− −1
Vtn
"  2 #
(W/L)p µn VDD − Vtn
≤ 1− 1− (5.2)
(W/L)a µp Vtn

Q 6. For a particular DRAM design, the cell capacitance is CS = 35 fF and VDD = 1.2 V. Each cell
represents a capacitive load on the bit line of 0.8 fF. Assume a 20-fF capacitance for the sense
amplifier and other circuitry attached to the bit line.

(a) What is the maximum number of cells that can be attached to a bit line while ensuring a minimum
bit-line signal of 25 mV?

(b) How many bits of row addressing can be used?


(c) If the sense-amplifier gain is increased by a factor of 4, how many word-line address bits can be
accommodated?

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