3rd Year Computer & Systems Engineering Dept.

Computer Organization (II) Course

Tutorial #01 (Chapter 5 : Internal Memory)

Problem #01

Problem #02

A 128M×8 DRAM is organized into a cell array that has 4096 rows. The DRAM

follows a distributed refreshment approach. Instead of refreshing the whole cell

array at once in a single refresh cycle, the array is refreshed incrementally in

multiple small refresh cycles where only two rows get to be refreshed each cycle.

(a) Suppose each memory cell can retain its data for up to 64 ms (without being

refreshed). What should be the maximum time elapsed from the beginning of any

refresh cycle to the next?

 • Number of refresh cycles each 64ms = (4096 rows) / (2 rows per cycle) =

2048 cycle

• Maximum time between refresh cycles = (64 ms) / 2048 = 31.25 µs

(b) If it takes 0.25 µs to refresh one row, what percentage of the DRAM time is

spent in refreshment?

Time elapsed during each refresh cycle = (2 rows) * (0.25 µs per row) = 0.5 µs

% of time spent in refreshment = (0.5 µs) / (31.25 µs) * 100% = 1.6%

Problem # 03

A 256K×4 read-only memory is to be implemented using 128K×1 ROM chips

(with no chip-select (CS) lines) and 2×1 multiplexers.

(a) How many ROM chips and multiplexers are required to implement this

memory?

Number of ROM chips = (256K * 4) / (128K * 1) = 8

Number of multiplexers = 4 (one multiplexer for each output data line)

(b) Draw a block diagram of the memory to show how the ROM chips should be

connected together with the multiplexers and how the input address lines and the

output data lines are routed.

(c) Calculate the overall access time of the memory given that the access time of

each ROM chip is

10ns and the propagation delay of each multiplexer is 2ns.

Overall access time = ROM access time + multiplexer propagation delay = 10 ns +

2 ns = 12 ns
Problem #4

You are given the shown DRAM module. All address, control and data lines are

shown.
1) What is the size of this memory module?
2) What is the role of the refresh controller?
3) How can you use it to build a 1 GB memory?
Show a complete diagram with labels.
Assume that WRITE and READ signals are
issued in logic 1 on bus.

Solution:
1) Size = 214x214 x 8 bit = 256MB.

2) Refresh controller is responsible for refreshing the capacitors of the memory.

3) To build a 1GB memory: we use four 256MB modules.

Solution
Solution
Problem #05

A 128K×8 bit memory is to be implemented using memory chips of size 32K×1

bit.
(a) How many chips are required to implement this memory?
(b) Suppose the implemented memory has a chip select line (CS). Draw a simple
block diagram to illustrate how the implemented memory can be connected to a
bus that supports an address space of 16M byte, given that the memory is assigned
a range of addresses ending at B9FFFF (hexadecimal).

Solution

Problem #06
Problem #07

Problem #08
Problem #09

Solution