Task Scheduler with Time Management
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Ahmed Razi UllahTask Scheduler with Time Management
Uploaded by
Ahmed Razi UllahTASK SCHEDULER
MADE BY:
Muhammad Omais (leader)
Ahmed Raziullah
PROJECT ABSTRACT
• The Task scheduler will allow user to specify the time allocated for each task
(maximum of 3).
• It also allows user to indicate through a push button if a task is completed before
time completion.
• If a task is completed before time, the remaining time of the task will be added to the
time allocated for next task. If the task is not completed, the counter will
automatically start the time for next task i.e start deducting time from next task.
• The counter will reset to 0 when time for third task gets over.
BLOCK DIAGRAM
STATE DIAGRAM
1.NUMERIC PAD
2.DECMAL TO BCD
ENCODER (74147)
3.ENABLING AND
DISABLING
REGISTORS
•Using 3 to 8 Decoder
(74238)
•Counter
•Showing Output on the
screen to confirm the input
•At a time only one display
will be on
• Counter is designed such
that it will detect whether any
button is pressed or not.
4.STORING IN
REGISTERS
•Using 74LS95 ic Shift Register
•When the Mode input is high we
will be dealing in parallel transfer
of data
•R2 is initially enabled before
entering any data in the register
•When the button is pressed on
the numpad it will be disabled
and that negative edge will help
store the data that we require
STATE TABLE
Present state Input Next state Output
Qa Qb x Qa* Qb* y
0 0 0 0 1 0
0 0 1 0 1 1
0 1 0 1 0 0
0 1 1 1 0 1
1 0 0 1 1 0
1 0 1 1 1 1
1 1 0 1 1 0
1 1 1 0 0 0
EXCITATION TABLE
Present state Input Next state Output Input Variable
Qa Qb x Qa* Qb* y Ta Tb
0 0 0 0 1 0 0 1
0 0 1 0 1 1 0 1
0 1 0 1 0 0 1 1
0 1 1 1 0 1 1 1
1 0 0 1 1 0 0 1
1 0 1 1 1 1 0 1
1 1 0 1 1 0 0 0
1 1 1 0 0 0 1 1
Ta=(Qa`Qb+Qbx)(x)
Tb=(Qa`+Qb`+x)
Y=(Qa`+Qb`)x
STATE
GENERATOR
•Below is the circuit which gives high when
the counters are giving zero output.
•The first task is ignited by a start button
•The remaining task are switched with the
help of the counter IC’s output and a MUX
•The counter ic will change its output either
the counter is giving zero output (task is
completed) or by a button on the left corner
which will shift the counter into next state.
This is a 4-to-1-line dual MUX which is converting its state based on the output of the state generator
It is receiving inputs from the registers as well as the BCD adders and its outputs are directly going into the
counters inputs to display task time.
The inputs of the counter are directly connected to the output of the MUX
They have a common reset which is controlled by the state generator.
The right most ic is the LSB of seconds and the left most is the MSB of the minutes.
The clock is given only to the LSB of seconds and as it reaches to zero it will give a
negative edge signal to its left ic and in this way the signal will slowly reach to the
MSB of the minutes.
The output of the counters are directly connected to the display and BCD adder.
These are BCD adders for task 2 and task
3 respectively register REG2 consists of
the time stored for task 2 minutes LSB
while the other inputs of the 4-bit binary
adder are the outputs of the counter’s
minutes LSB so that it adds time as it gets
decreased in task 1 the carry is sent to the
left and the time is being saved in register
REGM4 its enable is also directly
connected to the state generator. On its left
the binary adder has inputs from the MSB
of minutes from the counter and from
register REG1 which contains the data
stored in the minutes MSB for the task 2.
They both add and the data is stored in
register REGM3 whose enable is also
connected to the state generator. The
outputs of both registers REGM3 and
REGM4 are given to MUX to be selected
at the right time by the state generator.
