BUS

(continuation)
CHARLES G. JUARIZO
RECALL:

 NOISE IMMUNITY REQUIREMENTS:

‘1’ : VOH > VIH
‘0’ : VOL < VIL

DC LOADING REQUIREMENTS:

‘1’ : IOH > 𝐼𝐼𝐻
‘0’ : IOL > 𝐼𝐼𝐿
BUS BUFFERING TECHNIQUES
 TYPE 1 BUS: One Transmitter, Many Receivers
e.g address bus

Common Problem: DC Loading

Z-80

A0

From p.655

IOH = 250𝜇𝐴 16 RAM 3 TTL

IOL = 1.8𝑚𝐴 IIH = 10𝜇𝐴 IIH = 40𝜇𝐴
IIL = 10𝜇𝐴 IIL = 1.6𝑚𝐴
 BUS BUFFERING TECHNIQUES

Z-80
LOGIC 1: IOH = 250𝜇𝐴 𝑐𝑎𝑝
𝐼𝐼𝐻 = 16 10𝜇𝐴 + 3(40𝜇𝐴)
𝐼𝐼𝐻 = 280𝜇𝐴 (𝑟𝑒𝑞𝑢𝑖𝑟𝑒𝑑)
A0
𝐼𝑂𝐻 ≥ 𝐼𝐼𝐻 (not satisfied)

From p.655
LOGIC 0: IOL = 1.8m𝐴
𝐼𝐼𝐿 = 16 10𝜇𝐴 + 3(1.6𝑚𝐴) IOH = 250𝜇𝐴 16 RAM 3 TTL
𝐼𝐼𝐿 = 4.96𝑚𝐴 IOL = 1.8𝑚𝐴 IIH = 10𝜇𝐴 IIH = 40𝜇𝐴
IIL = 10𝜇𝐴 IIL = 1.6𝑚𝐴
𝐼𝑂𝐿 ≥ 𝐼𝐼𝐿 (not satisfied)
BUS BUFFERING TECHNIQUES

Solution: High-Current Buffers

- should be inserted between the transmitter and the receivers

‘1’ ‘1’: high IOH

‘0’ ‘0’: low IOL

 BUS BUFFERING TECHNIQUES
Z-80

High
one xmtr – one rcvr current
buffer
receivers
one xmtr – many rcvr
Buffer Requirements:
𝐼𝑂𝐻 ≥ 280𝜇𝐴 Typical Buffer Ratings (from p. 151)
𝐼𝑂𝐿 ≥ 4.96𝑚𝐴
𝐼𝑂𝐻 = 15𝑚𝐴 Very high output driving
𝐼𝐼𝐻 ≤ 250𝜇𝐴 74LS240/241/244
𝐼𝑂𝐿 = 24𝑚𝐴 capabilities
𝐼𝐼𝐿 ≤ 1.8𝑚𝐴
𝐼𝐼𝐻 = 20𝜇𝐴
normal
𝐼𝐼𝐿 = 0.2𝑚𝐴
BUS BUFFERING TECHNIQUES
 TYPE II BUS: Many Transmitter, One Receiver
e.g. control inputs (𝑊𝐴𝐼𝑇, 𝐵𝑈𝑆𝑅𝑄)

Common Problem: BUS Contention

 BUS Contention – condition when the content of the bus can not be predicted
because some transmitter are sending 1’s while others are sending 0’s.

Z-80

𝑊𝐴𝐼𝑇
0 1 1 1

slow memory/IO devices

BUS BUFFERING TECHNIQUES
 BUS logic
- The bus should contain a ‘1’ only if all the transmitter sends a logic ‘1’
- The bus should contain a ‘0’ when at least one transmitter send a logic ‘0’.

SOLUTION:
Insert a open-collector buffer between each transmitter and the bus.

Ileak
‘1’ High Z

‘0’ VOL
IOL
BUS BUFFERING TECHNIQUES
5V

Z-80
Pull-up R
resistor

𝑊𝐴𝐼𝑇
Ileak

buffers
Xmtr have open-collector output stage,
0 this means they can pull down to a
1 0 logic ‘0’ by saturating the their output
transistors but they required an
transmitter external pull-up resistor to force a
logic ‘1’ on the bus.
Design of a TYPE II BUS
- The proper operation of a type II 5V
bus is dependent on choosing the
value of the pull-up resistor R.
Z-80
IR
LOGIC 1: 𝑅 ↑, 𝑉𝑅 ↑, 𝑉𝑥 ↓ R
IIH
𝑊𝐴𝐼𝑇
Ileak I I Vx

buffers

transmitter
Design of a TYPE II BUS
Let Vx = bus voltage
o Vx > VIH (noise immunity reqmnt)
o 5 – VR > VIH
 5 – IRR > VIH

 IR = 𝐼𝑙𝑒𝑎𝑘 + 𝐼𝐼𝐻 (dc loading reqmnt)

5 – ( 𝐼𝑙𝑒𝑎𝑘 + 𝐼𝐼𝐻)𝑅 > 𝑉𝐼𝐻

5𝑉 − 𝑉𝐼𝐻 Max. value of R,

>𝑅 Rmax
𝐼𝑙𝑒𝑎𝑘 + 𝐼𝐼𝐻
Design of a TYPE II BUS
5V
LOGIC 0: WORSE CASE

Z-80
IR
R
IR + IIL
IIL
𝑊𝐴𝐼𝑇
Vx=VOL

buffers

0 1 1

transmitter
Design of a TYPE II BUS
 Vx < VIL (noise immunity reqmnt)
VOL < VIL

 IOL > IR + IIL (dc loading reqmnt)

𝑉𝑅
IOL > + 𝐼𝐼𝐿
𝑅
5−𝑉𝑂𝐿
IOL > + 𝐼𝐼𝐿
𝑅
5 − 𝑉𝑂𝐿 Min value of R,
𝑅> Rmin
𝐼𝑂𝐿 − 𝐼𝐼𝐿

𝑅𝑚𝑖𝑛 < 𝑅 < 𝑅𝑚𝑎𝑥

Design of a TYPE II BUS
 TTL –CMOS
‘1’ : VOH = 2.4V VIH = 3.5V
VOL = 0.4V VIL = 1.5V

5V

TTL CMOS
Vx 1µA
10µA

5 − 𝑉𝐼𝐻𝑐𝑚𝑜𝑠 5 − 𝑉𝑂𝐿
>𝑅 <𝑅
𝐼𝑙𝑒𝑎𝑘 + 𝐼𝐼𝐻 𝐼𝑂𝐿 − 𝐼𝐼𝐿
Design of a TYPE II BUS
 For open-collector Determine the range of values of R:
buffer
5𝑉 − 3.5𝑉
VOL = 0.2V 10𝜇𝐴 + 1𝜇𝐴
>𝑅

IOL = 1.8mA
136𝑘Ω > 𝑅
Ileak = 10µA
5𝑉 − 0.2𝑉
<𝑅
1.8𝑚𝐴 − 1𝜇𝐴

2.66𝑘Ω < 𝑅

Range: 2.66𝑘Ω < 𝑅 < 136𝑘Ω

Assume: 𝑅 = 4.7𝑘Ω
Design of a TYPE II BUS
 What is the NI if 𝑅 = 4.7𝑘Ω
 NI(1) = Vx – VIH
= Vx – 3.5V
But , Vx = 5 – VR
= 5 – IRR
= 5 – (11µA)(4.7kΩ)
Vx = 4.95V
NI(1) = 1.45V
 NI(0) = VIL – VOL
= 1.5V – 0.2V
 How many addl CMOS rcvr can be connected to the BUS if
R = 4.7k-ohms

5V

Logic 0
DC:
Vx
TTL CMOS IOL > IR + 𝐼𝐼𝐿
1µA
10µA 1.8mA>
5−0.2
+ 1µA + n(1µA)
Vx > 3.5V 4.7𝑘

5 – IRR > 3.5

5-[10µA+1µA+n(1µA)]4.7k CMOS n > 777
>3.5

5−3.5−11𝜇𝐴(4.7𝑘)
=n
1𝜇𝐴 (4.7𝑘)
Therefore: only308 add’l CMOS rcvrs
n = 308
 How many add’l xmtr can be connected to the BUS if
R = 4.7k-ohms

5V For Logic ‘1’

‘1’ R Vx > 3.5V

ILEAK IIH 5V-IR(4.7k) > 3.5V
CMOS
Vx DC: IR=1µA+10µA + n(10µA)

VIH = 3.5V 5 – [11µA + n(10µA)](4.7k) > 3.5V

‘1’
n 30 > n
 How many add’l xmtr can be connected to the BUS if
R = 4.7k-ohms

5V For Logic ‘0’

‘0’ R
IOL IIL DC: IOL > IR + IIL
CMOS
5𝑉 −0.2𝑉
VOL = 0.2V 1.8mA > + 1µA
4.7𝑘

1.8mA > 1.02mA

‘0’
n No limit for ‘n’

Therefore: only 30 Add’l xmtr

TYPE III BUS. Many Xmtrs, many rcvrs
(bidirectional)
E
e.g. DATA BUS

COMMON PROBLEM : BUS CONTENTION

FLOW CONTROL
SOLUTION: use bidirectional tristate
X X
If E = 1
output = high Z
If E = 0 E
output = input
For bidirectional:
one of E=0, and E=1, it
will transmit
 CPU
A2
A1
A2=0 A2=0 A0
A1=0 A1=0
A0=0
A0=0 𝑅𝐷 𝑊𝑅
𝑊𝑅 = 0 𝑅𝐷 = 0 0 1

ADDRESS ADDRESS
001 000

TRANSCEIVER devices capable of xmting and rcving

 An address is assigned to each devices. The CPU
indicates which device it waits to do data transfer
by sending one address. The CPU also indicated if
the device should transmit or receive by sending the
control signals 𝑊𝑅 and 𝑅𝐷.
For the proper operation of the bus, logic circuits
are designed to control the bidirectional tristate
buffer.
Ex. E1 should be active when the address sent by the CPU is
000 and the CPU sends the data (𝑊𝑅 = 0)

A2=0
E1=0
A0=0
𝑊𝑅 = 0

A type III BUS is reduced to a one xmtr-one rcvr by means of the buffer
E2 should be active when the address sent by the CPU is 000
and the CPU waits to read the data (𝑅𝐷 = 0)

A2=0
E2=0
A0=0
𝑅𝐷 = 0
E3 should be active when the address sent by the CPU is 001
and the CPU waits to read the data (𝑅𝐷 = 0)

A2=0
E2=0
A0=1
𝑅𝐷 = 0