CHAPTER -4

OP-AMP
• Main aim of the design of operational amplifier is to amplify the difference between
the two input signal (inverting and non inverting input) with very high gain.
V0  AOL V   V   - Ideal Case
AOL   - Ideal

• Practically, when it design using two BJT or FET, it will not give zero output for an
same input V+ and V- . It amplifies the common mode voltage also
V0  Ad Vd  ACVC - practical

Where
Vd - differential mode voltage = V+ - V-
V V
VC - Common mode voltage =
2
Ad – differential mode gain
AC – Common mode gain
Open loop Differential mode gain (Ad = AOL) is not infinite and common mode gain is
not zero practically.

• For an op-amp, Common mode rejection ratio defines the quality of an op-amp.
A
CMRR  d
AC
CMRR in dB = 20 log  Ad   20 log( AC )
CMRR in dB = Ad in dB - Ac in dB
If common mode gain (Ac) is very close to zero (CMRR is very close to infinite), the
op-amp close to ideal.
If CMRR is very low, the op-amp quality is very poor.

• The input terminal of an op-amp is directly connected with the base terminal of BJT or
gate terminal of FET. So the current flow through the terminal is considered as zero
ideally. But practical case some current will flow to the base of BJT or gate of FET,
this current is called as bias current.

• Bias current is the average current flow to the input terminals of an op-amp
  1
I  IB
IB  B
2
Where
IB+ - current flow to non- inverting terminal (base or gate of transistor 1)
IB- - current flow to inverting terminal (base or gate of transistor 2)
• Offset current is the difference between the two current
 1
I OS  I B  I B

• The input offset voltage (VOS) is a parameter defining the differential DC voltage required
between the inputs of an amplifier to make the output zero, when the inputs are same.

Characteristics of Ideal op-amp

• The input terminal of an op-amp is directly connected with the base terminal of BJT
or gate terminal of FET. So the current flow through the terminal is considered as
zero.

• If the input current is zero, that means input impedance is infinite.

Vin Vin
Z in   
I in 0

• Maximum amplified value by an op-amp in the positive side is VCC = +12V and in
the negative side is VDD = -12V.
Current flow through the input terminal zero
Input impedance Infinite
Output impedance zero
Open loop differential gain infinite
Open loop common mode gain zero
Common mode rejection ratio infinite
Slew rate infinite
Note: next chapter you will study about common mode gain, CMRR and Slewrate.
1.3 Open loop ideal Op-amp
• If the op-amp circuit output voltage does not feedback with the input, the type of op-
amp circuit is called as open loop op-amp circuit.

Example 1:
Determine the output voltage for the given op-amp circuit.

p
We know that

V1  V2
I1 
R

• We know that output voltage for an ideal op-amp is

V0  Ad V   V   and open loop gain Ad = infinite
• We have to find V+ and V- for the output voltage calculation. Current flow through
the input terminal is zero for ideal case.

2 V 
I   0A; V   2V
R1

3 V 
I   0A ; V   3V
R2

• V0  Ad (V   V  )
V0  (3  2)   . Maximum amplified value by an amplifier is VCC = +12V
V0 = 12V
Note:

• The circuit is called as comparator because

If V  V  ; Vo  12V
If V  V  ; Vo  12V
 By measuring the output voltage we can say which one of the input terminal is
much higher than others.

Example 2:
` Find the output voltage for the given ideal OP-AMP

• Open loop op-amp circuit, because output is not connected with the input. So, we can find
V  and V  directly.
• If input terminal has more than one branch, Assume current direction and apply KCL for the
calculation of V  and V  .

2 V  2 V 
I1   ;
R1 2  103
V 0 V
I3   ;
R3 1  103
2 V  2 V 
I2   ;
R2 1  103

V 0 V
I4   ;
R4 2  103
 By KCL

I1  I 3 ; I2  I4

2 V  V 2 V  V
 ; 
2  103 1  103 1  103 2  103

2  V   2V  4  2V   V  ;

2 4
V   0.6666 Volt V   1.333 Volt
3 3

• V0  Ad (V   V  )

V0  (1.333  0.666)   . Maximum amplified value by an amplifier is VCC = +12V

V0 = 12V

1.4 Op-amp with feedback for an ideal op-amp

• To use the op-amp as amplifier, output should feedback with the negative input
terminal i.e feedback effect on negative terminal should be higher than positive
terminal for the amplification

Common procedure to find the output voltage for the feedback op-amp amplifier
circuit:

Step 1:

• Calculate the V+ for the given circuit because if we know the V+ and V-, we can find
the output voltage V0 by using the op-amp output equation. Consider a given circuit

In a + terminal more than one branches are present, so assume current direction and
apply KCL to find V+
 V4  V  V 0 V
I2  ; I6  
R2 R6 R6
Apply KCL
I2  I6
V4  V  V 

R2 R6
V4 V  V   R  R6 
   V   2 
R2 R6 R2  R2 R6 
V4  R2 R6   R6 
V     V4  
R2  R2  R6   R 2  R6 
Step 2:
Find V- .
unknown Vo is feedback with the - (inverting) terminal. So we cannot find V- like as
open loop system so we have to go for different way.
We know that

Vo  Ad (V   V  ) for ideal case and Ad is infinite for ideal

V0
 V  V   0; V  V 


 R6 
V   V   V4   ………………(1)
 R2  R6 
Step 3:
Find current flow through in each branch of inverting terminal junction and apply
KCL to find V0.

V3  V  V2  V 
I1  ; I3  ;
R1 R3
 V1  V  V   Vo
I4  ; If  ;
R4 R5

By KCL
I1  I 3  I 4  I f

V3  V  V2  V  V1  V  V   Vo
  
R1 R3 R4 R5

V3 V  V2 V  V1 V  V  V0
       ……………..(2)
R1 R1 R3 R3 R4 R4 R5 R5

Substitute equation (1) in (2)

V0  V3 V2 V1   1 1 1 1 
     V      
R5  R1 R3 R4   R1 R3 R4 R5 

 V V V  V R  1 1 1 1  
Vo  R5   3  2  1   4 6     

  R1 R3 R4  R2  R6  1
R R3 R 4 R5 

Example 1
In the circuit shown below the op-amps are ideal. Then vout in volts is (2013-IN)

-2V
1kΩ 1kΩ
vv22 +15V
+15V
v

+ Vout
1kΩ -15V
-15V

+1 V 1kΩ
1kΩ

A) 4 B) 6 C) 8 D) 10
Solution:
For Op-amp 1

• V   V   1V and I   I   0 A
• Apply KCL at V+ node
 2  1 1  V01

1  103 1 103
 V01  4V .

For op-amp 2
• V   V   4V

• Apply KCL at V  node

4  0 V0ut  4

1  103 1  103
V0ut  8V

Example 2
For the OP-AMP circuit shown in the figure, V0 is

2kΩ

1V 1kΩ V0
+
1kΩ

1kΩ

A) -2 V B) -1 V C) -0.5 V D) 0.5 V

Solution:
• By voltage division rule
1
V   1   0.5V
2
 
V  V  0.5V
• Apply KCL at V- Node
1  0.5 0.5  V0

1  103 2  103

V0  0.5V

Example 3
Consider the Op-Amp circuit shown in the figure
 R1

R1
Vi
V0
+
R

The transfer function V0(s) / Vi(s) is

1  sRC 1  sRC 1 1
A) 1  sRC B) 1  sRC C) 1  sRC D) 1  sRC

Solution:

• Capacitive reactance XC = 1/Sc

• By voltage division rule
1
 sC  V  1
V  Vi 
RsC  1
i
R 1
sC
• By circuit current law at node V-
Vi  V  V   V o

R1 R1
Vi  2V   Vo
 Vi 
Vi  2   V0
 RsC  1 
 RsC  1  2 
Vi    V0
 RsC  1 
V0 1  RsC

Vi 1  RsC

4.1 Gain calculation in OP-AMP which has finite open loop gain.
Consideration of op-amp which gas finite loop gain but in all other aspects it is ideal.
• For the practical op-amp, open loop gain is not infinite. So
V0  AOL V   V  
V0
V  V  
AOL

Example
An opamp has a finite open loop voltage gain of 100. Its input offset voltage Vios (=
+5mV) is modeled as shown in the circuit below. The amplifier is ideal in all other
respects. Vinput is 25 mV.
 The output voltage (in millivolts is) -------------- GATE-16-EC-SET3
Solution:

•  
V   Vinput  5  103  30 mV
 V  3  V0
• V  V  
V0
 
 30  10 3   0  
AOL  100  100

• Apply KCL at V node.
0  V  V   V0

1  103 15  103
 15V   V   V0
 3  V0 
V0  16V   16  
 100 
101V0  48
V0  0.475V  475 mV

4.2 From the relation between CMRR, Ad, and AC

Example 1

A Differential amplifier shown below has a differential mode gain of 100 and a
CMRR of 40db. If V1 = 0.55 V and V2 = 0.45 V , the output VO is GATE-08-IN
U1
V1
V0
V2

A) 10 V B) 10.5 V C) 11 V D) 15 V

Solution:

• V0  Ad Vd  ACVC
Ad = 100;
A 
CMRR  20 log d   40
 Ac 
 Ad
 100
Ac
Ac = 1

Vd = V1 – V2 = 0.1

0.55  0.45
VC   0.5
2

V0 = 10.5V

4.3 From the relation between offset current and bias current

Example 4
For the op-amp shown in the figure, the bias currents are Ib1 = 450 nA and Ib2 =350
nA. The values of the input bias current (IB ) and the input offset current (If ) are:
GATE -14-IN

A) I B  800nA, I f  50nA B) I B  800nA, I f  100nA

C) I B  400nA, I f  50nA D) I B  400nA, I f  100nA

Solution:

• Input bias current

I I
I B  b1 b 2
2
450  350
IB   400 nA
2
• Offset current
I OS  I b1  I b 2
I OS  450  350  100 nA
Do it yourself
1. In the circuit given below, the opamp is ideal. The output voltage V 0 in volt is ____
GATE-IN-2016

Hint: Apply the voltage division to find V 1.

Ans: -1V
2. Given that the op-amp is ideal, the output voltage VO is

2R

+10 V
R

V0
+

2 V -10 V

A) 4 V B) 6V C) 7.5 V D) 12.12 V
Ans: B) 6V

3. Assuming the OP-AMP to be ideal. The voltage gain of the amplifier shown below is

 R2  R3  R // R3   R  R3 
A) B) C)   2  D)   2 
R1 R1  R1   R1 
 Ans

4. Consider the Op-amp circuit shown in figure below, value of R1 is GATE -2007-IN
100kΩ
20kΩ
0.2 V
0.6 V
R1 -7 V

R2

A) 5KΩ B) 10 KΩ C) 15 KΩ D) 20 KΩ

5. The value of IL for the circuit GATE-2016-IN

6. The output voltage shown in the figure, in volt is close to GATE-IN-2017

A) -20V B) -15V C) -5V D) 0V

Ans: B) -15V

7. A resistance temperature detector (RTD) is connected to a circuit as shown in the

figure. Assume the op-amp to be ideal. If V0 = +2.0V, then the value of x is -------
GATE-IN -17
 Ans: 0.19 to 0.21
8. The junction semiconductor temperature sensor shown in the figure is used to measure
the temperature of hot air. The output voltage V 0 is 2.1V. The current output of the
sensor is given by I =T in µA where T is the temperature in K. Assuming the op-amp
to be ideal, the temperature of the hot air in  C is approximately -----------
GATE-17-IN

1.7 Output calculation for practical op-amp with considering the offset voltage and bias current:

Considering offset voltage

Note: if the offset voltage is given, add the offset voltage at the non -inverting terminal and find the
output voltage like as ideal case. Justification for the addition of offset voltage in the non – inverting
terminal is given below. If the justification is not understandable, directly go to the problem with
remember that offset voltage should be added in the non-inverting terminal.

• Ideally, in open loop configuration output voltage is zero when both the inputs are same but
practically there is some output voltage due to unmatched transistor in the op-amp.
 V0  Ad V2  V1  . When V1 = V2, output voltage is zero in ideal but in practical it has some
value. Let us take the output voltage X. (Ideal case V O = 0 but in practical case VO = X)
In practical case
V0  Ad V2  V1   X

V2  V1   X
= input offset voltage
Ad

Convert the ideal op-amp into practical op-amp

• If we add the input offset voltage in the non- inverting terminal of op-amp, the ideal op-amp
will become practical

Now
X
V   V2  ; V   V1
Ad

 
 
V0  Ad V   V   Ad V2 
X
 V1  Now when V1 = V2
 Ad 
VO  X (When V1 = V2)

So to consider the output offset voltage, we have to add the input offset voltage at the non -
inverting terminal of ideal op-amp.
Example 1:

Consider a given circuit which has the offset voltage of 10mV, determine the output voltage for the
given circuit.

Solution:

• Add (consider) the offset voltage in the non -inverting terminal.

 • V   10mV (Now, Calculation of output voltage is same as that of ideal case)
• Differential mode gain is not given so Ad   Now V   V   10mV .
• Apply KCL at the inverting terminal to find the output voltage
3  V  1  V  V   V0
 
1 1 3

V   V0
4  2V  
3

V0  7V   12

V0  11.93V

1.8 Output voltage calculation with considering bias current and offset current

• An ideal op-amp has no current flow at the inputs. The world is not ideal. In the real world,
tiny amounts of current actually do flow into both the non-inverting and inverting inputs of
your component. The difference between the current flow through the inverting and non
inverting terminal is called as input offset current

Input offset current = I b 2  I b1

• The average between the inverting and non inverting current is called as Input bias current.
I b 2  I b1
Bias current =
2
Example 1: (Without feedback)

For the op-amp shown in the figure, the bias currents are Ib1 = 450 nA and Ib2 =350
nA. The values of the input bias current (IB ) and the input offset current (If ) are:
 GATE -14-IN

Solution:

• Offset current = I b 2  I b1  450  350  100nA

I b 2  I b1 450  350
• Bias current =   400nA
2 2
Example 2: (With feedback)

Consider the op-amp circuit with offset current is 20µA and bias current is 160µA.

i) Determine the output voltage for the given circuit

ii) Determine the error by the bias current and offset current

Solution:

Output voltage calculation:

Step1: Find Current flow through the inverting and non – inverting terminal and V  .

From the given

Offset current = I b 2  I b1  20A

I b 2  I b1
Bias current =  160A
2
By solving the above equation
Current flow through the non inverting terminal is I b 2  170A and current flow through
the inverting terminal is I b1  150A

Apply KCL at the + terminal junction to find V 

 6 V  V   0
  I b2 (Consider the current flow through the Non inverting terminal)
20 10

6 V  V   0
  170  10 6 
20 10

V   1.9989Volt

Step 2:

V   V   1.9989Volt (Minimum 4 bit representation)

Step 3:

Apply KCL with considering bias current to calculate the output voltage

2  V  V   Vo
  I b1
10 30

2  V  V   Vo
  150  106 
10 30

2  1.9989 1.9989  Vo
10

30

 150  106 
VO  2.0001Volt

1.9 Calculation of error by the bias current and offset current:

• Calculate the output voltage with considering the input effect of bias current and offset
current only so deactivate all other input source effect (By making short the input voltage
source and open the current source) .

Step 1:

Calculate V  by applying KCL at the junction of non – inverting terminal with considering
the bias current

0 V  V   0
  I b2 (Consider the current flow through the Non inverting terminal)
20 10
 V  V 
  170  10 6 
20 10

V   0.00113Volt

Step 2;

V   V   0.00113Volt

Step 3:

Calculate the output by applying KCL at the inverting terminal with considering the bias
current

0  V  V   Vo
  I b1
10 30

0.00113  0.00113 Vo
10

30

 150  106 

VO  0.00003Volt  30V

Error by the bias current and offset current is 30µVolt.

4.4 Error of bias current compensation using a resistor

• A resistor (RX) is added in the non -inverting terminal to eliminate the DC output
error by bias current.
• The value of RX will make the output voltage as zero when the bias current only
considered in the ideal op-amp (other supply voltage are zero)

• Vin = 0 because output by bias current only needed.

• By super position theorem

V0 by IB+ + V0 by IB- = V0 = 0 (Rx makes V0 is equal to zero.)

V0 by IB+
 • Open the current source IB-

• V   I B RX
 
0   I B RX

 
 I B R X  V0
Rin Rf
 I R 
I R   R  Rin 
V01   R f  B X  B X   I B  RX  f
 R 
 R 
 in Rf   in 

V0 by IB-

• Open the current source IB+

• V 0
0  V0 
 IB  0
Rf

V02  I B R f
V01  V02  V0  0
  R f  Rin 
I B R X    I B  R f
 Rin 
 
IB  IB

R f Rin
RX   R f // Rin
R f  Rin

Example
In the circuit given below, each input terminal of the opamp draws a bias current of
10 nA. The effect due to these input bias currents on the output voltage V 0 will be zero, if
the value of R chosen in kilo-ohm is _______. GATE-16-IN

Solution:
• Consider the both terminal bias current are same. So
• For an inverting amplifier
R f Rin 60  103  30  103
RX    20K
R f  Rin 90  103
4.5 CMRR, Ad and AC calculation for a closed loop op-amp circuit
• We know that
 V  V2 
V0  Ad (V1  V2 )  Ac  1 
 2 
 A   A 
V0   Ad  c V1   Ad  c V2
 2   2 
• Find the outout of the closed loop op-amp in the above form. So we can get
 A   A 
 Ad  c  and  Ad  c  value .
 2   2 
• From the above calculation, can find Ad and AC
A
• CMRR  d
Ac

Example

An ideal opamp is used to realize a difference amplifier circuit given below having a
gain of 10. If x = 0.025, the CMRR of the circuit in dB is _______. GATE-16-IN

Solution:

 97.5 
• V   V2     0.905V2
 107.75 
• Apply KCL
V1  V  V   V0

9.75 102.5
102.5V1  102.5V   9.75V   9.75V0
102.5V1  112.25V   9.75V0
V0  10.51V1  10.419V2
 A   A 
By comparing with the equation V0   Ad  c V1   Ad  c V2
 2   2 
A  A 
Ad  C  10.51 ;  Ad  c   10.419
2  2 
• From the equation, Ad = 10.4645, Ac = -0.091
 Ad 10.4645
• CMRR    114.9945
Ac 0.091
A 
• CMRR in dB  20 log d   41.2 dB
 Ac 

4.8 Identify the type of filter for the given OP-AMP circuit
• Find the output magnitude for low frequency (DC) signals
1 1
f = 0; X L  L  2  f L  0 ; X C   
C 2  f C
Short the inductance and open the capacitance.
If the output voltage is zero, means It will not allow the low frequency signal.
So it may be high pass filter or Band pass filter.

If the output voltage is non -zero, means it will allow the low frequency signal. So it
may be low pass filter or Band reject filter

• Find the output magnitude for high frequency signal.

f   ; X L   and X C  0 that means inductor act as open and capacitor act as
open.
If the output voltage is zero, means it will not allow high frequency signal. So it may
be low pass filter or Band reject filter. Otherwise it may be high pass filter or Band
pass filter.

• By calculating magnitude at low and high frequency, can say the type of filter.

Example
The circuit shown in the figure is GATE-14-IN
 R

R1

Vi Vout

A) An all pass filter B) a band pass filter C) a high pass filter

D) a low pass filter

Solution:

• at low frequency (f = 0), capacitor act as open.

R
Now Vout  Vi  .
R1
• At high frequency ( f  ) , capacitor act as short.
V   V   Vi
Vi  V0
0
R
Vi  V0

The circuit has magnitude at low and high frequency. So it is an all pass filter

4.9 Cut-off frequency calculation in op-amp circuit

• Cut -off frequency for both the low pass and high pass filter is
 3dB 
Real part 1
 
1
1   s 
Imaginary part  RC

Example
 For the given low-pass circuit shown in the figure, the cut-off frequency in Hz will be
___________. GATE -14-IN

Solution:
1 1
f 3dB    15.39 Hz
2 RC 2  22  10  0.47  10 6
3

4.10 Op-amp with diode

• Find the open circuit voltage across the diode. If the voltage is more than 0.6, replace
the diode by a resistor with voltage drop 0.7V. otherwise replace the diode with open.
• For the Zener diode, if the open circuit voltage is more than Zener voltage, replace
the Zener by a battery with Zener voltage otherwise open the Zener.

Example 1
In the circuit given below, the diodes D1 and D2 have a forward voltage drop of 0.6
V. The opamp used is ideal. The magnitude of the negative peak value of the output
Vo in volt is ________. GATE -IN-16

Solution:
• Assume both the diodes are open
• During positive half cycle – it will act as comparator
 V01  Vsat
VAK1  Positive ; D1 = ON
VAK 2  Negative ; D2 = OFF
Replace the diode D1 by a resistor with 0.6 Voltage drop
Replace the diode D2 by open
V0  1.6 sin(3000t )
• During negative half cycle
V01  Vsat
VAK1  negative ; D1 = OFF
VAK 2  Positive ; D2 =ON
Replace the D1 by open and D2 by a resistor with 0.6 V drop
V0 = 0V;
• Negative peak value of output is 1.6V

Example2 :
Determine the output voltage waveform for the following circuit. Input for the given
circuit is sinusoidal.

Solution:
During Positive Half cycle of the input:

• Open the diode to find the open circuit voltage across the diode
(VAK = VA -VK) (To know the status of the diode).
V A1  Vin ; VA2  Vsup ply  12V ( If the op-amp supply is +12V and -12V)

VK1  VA2  12V VK 2  0V

Voltage across the diode

V AK 1  V A1  VK 1  Vin  (12)  0.7 (Diode 1 will act as forward bias or short)

VAK 2  VA2  VK 2  12  (0)  0.7 (Diode 2 will act as reverse bias or open)

Now the equivalent circuit becomes

Vo = 0 Volt.
During Negative Half cycle (Vin = Negative)
• Open the diode to know the status of diode at negative input
V A1  Vin ; VA2  Vsup ply  12V ( If the op-amp supply is +12V and -12V)

VK1  VA2  12V VK 2  0V

Voltage across the diode

V AK 1  V A1  VK 1  Vin  (12)  0.7 (Diode 1 will act as reverse bias or open)

VAK 2  VA2  VK 2  12  (0)  0.7 (Diode 2 will act as forward bias or short)

The circuit is inverting amplifier

R 
Vo  Vin  2   Vin
 R1 
Input

Output
4.11 Slew rate calculation
Consider the voltage follower circuit. If the input voltage is 2V, then the output
voltage of an op-amp is 2V. for ideal op-amp, if the input voltage changes from 0-2V,
then the output voltage changes to 2V very quickly. (i.e) no time taken for the voltage
changes to the desired (2V). but in practical cases, some time takes to the desired
value.

Slew rate is the ability of the op-amp to produce the maximum output changes per
unit time.
dV0
slew rate 
dt max
• For ideal case, maximum output changes occur at zero time. So slew rate
dV0
slew rate  
0 max
But practical op-amp, 1 s , 2  s time takes to changes the maximum output.

Relation between slew rate, input magnitude and frequency:

Consider the voltage follower circuit with input Vin  Vm sin t . output for the circuit
is V0  Vm sin t .

dV0
slew rate 
dt max


d
Vm sin t  / max
dt

 Vm  cost / max

= Vm 

slew rate  2  f Vm

• If we use the op-amp which has slew rate  2Vm , the output voltage will not
distort.
Example1
The operational amplifier shown in the circuit below has a slew rate of 0.8 Volts/  s .
The input signal is 0.25 sin t  . The maximum frequency of input in kHz for which
there is no distortion in the output is (2013-IN)
 A) 23.84 B) 25.0 C) 50.0 D) 46.60
Solution :

R2
Vo  Vi 
R1

470
V0  0.25 sin t   5.341sin t
22

Slew rate = 2  Vm f

Slew rate = 2  5.341 f

0.8
f   23.838 KHz
10  2    5.341
6