Dissertation Part I Presentation

Yield Optimization in VLSI Circuits using

Power Gating
in
Partial Fulfillment of Degree of Master of Technology (M. Tech.) Semester III
by
Swati S. Kumar
(2012PUSETMVLX01587)
(Session 2013-14)

Under supervision of
Mr. Gaurav Soni
Assistant Professor







Department of Computer Engineering
School of Engineering & Technology
Poornima University
IS-2027 to 2031, Ramchandrapura, Sitapura Extension, Jaipur-303905 (Raj.)

2/27/2014 1
Contents
Introduction / Motivation
Literature Review
Details of Review: Which include summary table of
number of research papers in each category.
Issue wise: Solution Approaches & Results: Just
Comparison
Strengths and Weaknesses: Final outcome of review in brief
Problem Statement & Objectives
Design Specifications: With proposed selected hardware /
software / platform / tool / Methodology
Experimentations carried out & results
Conclusion
References
6/6/2014 Yield Optimization In VLSI Circuits 2
Introduction / Motivation (1/2)
Continuous technology
scaling and increasing
clock frequency =
increasing POWER
Increasing demand of
Portable devices
Leakage power
increases
exponentially


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Fig 1: Increase in leakage power with shrinking CMOS
technologies
Introduction (1/2)
Leakage Power Reduction Techniques
o MTCMOS
o DTCMOS
o Sleep Transistors
o Power Gating
6/6/2014 Yield Optimization In VLSI Circuits 4
Literature Review
40 papers were reviewed to optimize the yield in VLSI
circuits

Review Process Stages Adopted :
Stage 0: Get the Feel
Stage 1: Get Big Picture
Stage 2: Get the Details
Stage 3: Evaluate the Details
Stage 3 +: Synthesize the Details.



6/6/2014 Yield Optimization In VLSI Circuits 5
Literature Review
Literature review of Yield Optimization in VLSI
Circuits paper is categorized into following issues:
a) Power Optimization
b) Delay Optimization

6/6/2014 Yield Optimization In VLSI Circuits 6
Issue Wise Solution Approaches
6/6/2014 Yield Optimization in VLSI Circuits 7
S. No. Authors Year Approach Results
1 K.R.N
Karthik et al
[2]
2013 The optimal reverse body bias voltage is
generated from the leakage circuit and
calculated the sub-threshold current.
Reduction of leakage
power in both active
and stand-by mode.
2
Ruchika
Mittal
et al[4]
2013 High threshold voltage devices are inserted in
series to low threshold voltage circuitry
Reduced leakage
power is obtained.
3
Raghuvir
singh
et al[21]
2011 Driver interconnect load system were used. 25% line variation
was reduced.
4
M. Geetha
Priya
et al[14]
2012 DTMOS (dual threshold MOS) Easy fabrication with
minimal circuit is
obtained.
Issue 1 : Power Optimization in VLSI Circuits
6/6/2014 Yield Optimization In VLSI Circuits 8
S. No. Authors Year Approach Results
5.
Rajani H.P. et al[11] 2012 Novel sleep transistors used for
peripheral circuits based on state
retention technique.
Power reduction achieved
by X3.5 factor
6
Dr. K Srinivasa Rao
et al.[18]
2011 Multi threshold metal oxide
semiconductor was used.
Reduced leakage power
was obtained.
7.
Rashmi Bahal et al

2012 7TSRAM cell in deep submicron
regime were used.
Good estimation of total
leakage in the logic
circuits.
8
M. Madhavi Latha
et al[9]
Galeorstack technique was used.
Reduction in leakage
power with no increase in
delay.

10
M. Janaki Rani
et al[15]
2012 Self adjustable voltage
technique.
Reduced level of power
dissipation compared to
the other conventional
techniques.
6/6/2014 Yield Optimization In VLSI Circuits 9
S. No. Authors Year Approach Results
Delay Optimization In VLSI circuits
S. No. Authors Year Approach Results
11
Gyan prakash et
al[5]
2012 10TSRAM containing 10
transistors were used with
stacking effect.
66% yield improvement is
achieved.
12
Etian N. Shauley
et.al[10]
2012 Two techniques were involved.
First technique was replacing
NMOS path with PMOS.
Second technique used dynamic
voltage scaling.
26%, 50% reduction in gate
current and 37%, 57% leakage
power reduction by first and
second techniques respectively.
13
Alireza Khorospur
et.al[19]
2011 Generalized extreme value
distribution in the presence of
process variation.
Maximum 99% percentile
points with average errors of
2.0% were obtained.
14
Archana Nagda
et.al[13]
2012 A Single circuit implementation
of various techniques done in
accordance to incur minimum
delay.
Significant reduction in leakage
power is obtained.
15
De Shiaun Chiou
et.al[10]
2010 Temporal correlation algorithm 25% size reduction as well as
good leakage power reduction.
6/6/2014 Yield Optimization In VLSI Circuits 10
S. No. Authors Year Approach Results
1
Mihir chaudhary
et al[12]
2010 Dominant critical gating done by
ranking the gates in decreasing order.
Full chip optimization with 57%
and 32% improvement in time
yield.
2
Amit Agarwal et
al[30]
2005 Process tolerant architecture in cache
memory is used.
Yield is improved by 94%.
3
Xiang Lu et.al[29] 2004 Parametric delay evaluation based on
LUT and delay formulas.
Accuracy in path delay as
function of multiple interconnect
was obtained
4
Smruti R. Srangi
et al[7]
2008 VARIUS technique based on the
framework to model timing error
caused by process variation.
Accurate estimation of timing
error is obtained for pipeline
stages.
5
Shida Zhong et
al[20]
2011 Analysis of resistive bridge defect
delay behavior is done.
Improved the yield by more than
12% average with good timing
optimization to finish largest case.
ISSUE 2: Delay Optimization in VLSI Circuits
Strengths and Weaknesses
Strengths
Modifying and using the conventional techniques like forced
stack techniques, lector techniques etc. on the single chip has
lead to the better optimization of power and delay.
Mostly techniques of power reduction used standard verification
tools like Cadence, SPICE for which provided efficient
comparative study between conventional techniques and
proposed one.
Techniques like state retention techniques can be utilized in any
situation which doesnt demand good voltage level.
Transistor stack techniques, sleep transistors are basic techniques
that were used in most of the researches to reduce the leakage
power reduction.

6/6/2014 Yield Optimization In VLSI Circuits 11
Strengths

Compensated circuit for input-output buffer works at hundreds
of MHz and also provided reduction to noise.
Stacking Power Gating reduced leakage power as well as
ground bound noise.
MTCMOS, DTCMOS techniques emerged use of multi V
th
as
an effective and easiest way to reduce the power dissipation
with easy implementation.
In nano technologies, process tolerant cache architecture
provides the advantage to handle large number of fault without
reducing the cache size.
Dual Gating achieves 86% of short circuit power and 99% of
leakage power reduction.
6/6/2014 Yield Optimization In VLSI Circuits 12
Weaknesses
All the proposed leakage reduction techniques like MTCMOS,
leakage monitoring circuit etc. lead to the trade-off between
area and delay.
Techniques like MTCMOS had suffered from the fabrication
complexity problem.
In case of worst delay, leakage reduction techniques like DIL
and DTCMOS exhibits great increase in power dissipation and
area with loss of efficiency.
While maintaining the clock frequency distribution in WID
(With in Die), adaptive body bias lead to increase in leakage
power. Clock frequency had increased by using the CMOS
leakage reduction techniques but it lost the objective of slowing
down the power for 65nm technology.
Delay evaluation technique involved the implementation
complexity

6/6/2014 Yield Optimization In VLSI Circuits 13
Problem Statement & Objectives
To optimize the yield in the circuit after the
technology mapping phase.
without increase in leakage power
Without increase in delay
6/6/2014 Yield Optimization In VLSI Circuits 14
Design Specifications
6/6/2014 Yield Optimization In VLSI Circuits 15
CMOS
inverter with
Low Vth
CMOS inverter
with Power
gating
Generate net list Generate net list
Save net list in .sp and library file in
.pm extension
Save net list in .sp and library file in
.pm extension
Simulate by H-Spice Simulate by H-Spice
A B
6/6/2014 Yield Optimization In VLSI Circuits 16
A B
Analyze result with .lis file and view
the waveform in CosmosScope
Analyze result with .lis file and view
the waveform in CosmosScope
Compare result for average power with waveform in
CosmosScope
Optimized
CMOS inverter
Fig. 2 : Architectural Design Flow
Proposed Technique
6/6/2014 Yield Optimization In VLSI Circuits 17
Power Gating Technique

Switch the power OFF to the FU when not needed
Achieved by using a suitably sized header or footer transistor
Popular technique to reduce FU power
Fig 3: Power Gating Technique
Hardware and Software
6/6/2014 Yield Optimization In VLSI Circuits 18
Hardware
o CMOS inverter

Software's Used
H-Spice
CosmoScope
S-Edit



Fig 4 : Basic CMOS Inverter
Experimentations Carried out & Results
Objectives
To understand the power gating technique.
To study the different type of methodology in power
gating used by the researcher.
To study various type of variations in power gating.
To simulate the VLSI circuits in the HSPICE.

The final objective selected for experiment is
To optimize the yield of the CMOS inverter with
Power Gating technique using H-SPICE.

6/6/2014 Yield Optimization In VLSI Circuits 19
6/6/2014 Yield Optimization In VLSI Circuits 20
Experimental Results
Power dissipation without using Power Gating
o Average power= 8.3680E-10


Power Dissipation using Power Gating
o Average power =2.6921E-13
6/6/2014 Yield Optimization In VLSI Circuits 21
Simulation Graph 1 : Power Characteristic of
CMOS Inverter without using Power Gating
6/6/2014 Yield Optimization In VLSI Circuits 22
Simulation Graph 2: Power Characteristic of
CMOS Inverter using Power Gating
Conclusion
Technology scaling has given rise to increase in
power consumption and delay of the digital integrated
circuits.
Power Gating is an effective technique to reduce the
leakage power of the CMOS technology scaled
circuits.
Yield optimization has been achieved with significant
leakage reduction .
6/6/2014 Yield Optimization In VLSI Circuits 23
References
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Yield Optimization In VLSI Circuits 24
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6/6/2014 Yield Optimization In VLSI Circuits 25
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