POWER NETWORK

ANALYSIS


ABHISHEK JAIN
MT-13151
MOTIVATION
Performance degradation in using common power supply


WORK TO BE CARRIED OUT
1) Characterizing the supply noise:
2) How to define output error
3) How to do analysis
a) For a given supply noise error we are getting
b) For a given error what supply noise can be tolerated
WORK DONE SO FAR
Literature survey on characterizing supply noise
Since supply noise is not a periodic signal Fourier transform tool
needs to be expertise. Fourier series along with Fourier transform is
studied for understanding noise
Major concern is the method of defining supply noise or to give a
supply noise to the Sensor IP
Need to justify certain set of minimum and necessary parameters that
are required to define supply noise

POWER SUPPLY NOISE ANALYSIS
Includes IR drop and I noise and use of decoupling capacitor to keep
power supply within specification, provided signal integrity and reduce
EMI noise
Worst case IR drop and worst case I noise do not occur at same time
Needed to calculate maximum IR drop and worst case I noise and
then adding worst case together
On chip coupling capacitance is required to compensate for the
excessive voltage drop V
PACKAGE IMPEDANCE FREQUENCY
RESPONSE
PACKAGE LEVEL POWER BUS MODEL




To analyze the on-chip power supply voltage drop, we need to model the
resistance, capacitance, and inductance of each power bus segment.
Resistance = R/width, is determined by each layer's sheet resistance R,
and the width of the power bus.
total capacitance for the power bus consists of three components:
the area capacitance, the fringe capacitance, and the line-to-line
capacitance
The modeling of wire inductance however, is more complicated and
cannot be represented by simple formula and mutual inductance is
also considered if the power buses are in close proximity to each
other
In order to reduce the complexity for full-chip analysis, a hierarchical
approach is used to build the on-chip power bus model
SWITCHING CIRCUIT MODEL


Replace the nonlinear devices and capacitive loads in the switching
circuit model with the piecewise linear current sources such as
triangular and trapezoidal current waveform
These waveforms can be derived by calculating the total average
current and peak current using procedure listed :
1.Simulate circuits without loading to obtain internal Iave and Ipeak
2. Calculate the total output capacitance Cout from all output nets.
3. Iave(total) = Iave(internal)+Cout*Vdd*f, where Vdd is the power
supply voltage and f is the frequency
4. Ipeak(totaal) = Ipeak (internal ) * n, where n is an empirical ratio
between the peak current with loading and the peak current without
loading.
5. Calculate the total power P = 1/2Vdd(Iave(internal) + Cout * Vdd * f *
SF).
If Iavg is less than or equal to one half of Ipeak, a triangular current
waveform is characterized
If the average current Iavg is greater than 1/2 Ipeak , the circuit can be
represented by a trapezoidal current waveform

DECOUPLING CAPACITOR MODEL
1. Nwell capacitor
2. Circuit capacitance
3. Thin oxide capacitance
NOISE ESTIMATION FOR SOI CIRCUITS
SOI circuits offer better performance due to reduced parasitic
capacitance, enhanced channel mobility and higher current density
Degradation of power supply voltages may cause circuit instability
and device latch-up, due to SOIs floating substrate structure
To estimate the switching noise for an SOI chip, we replace the
functional blocks of an existing bulk CMOS chip with the
corresponding SOI circuits.
BULK CMOS VS CMOS SOI
As far as decoupling capacitance and switching noise are concerned,
the SOI chip has less circuit capacitance , no n-well capacitance and
higher peak current due to its faster switching speed.

NOISE IN DEEP SUBMICRON TECHNOLOGY
Noise can be defined as anything that causes the voltage of an
evaluation node to deviate from the nominal supply or ground rails
when it should otherwise have a stable high or low value
Noise can be characterized by its peak magnitude relative to the
nominal supply and ground rails and its behavior in the time-domain.
An evaluation node is a circuit node that forms the connection
between channel connected components in the design.
NOISE SOURCES
VH : Noise sources that reduce an evaluation node voltage below the
supply level (VDD)
VL : noise sources that increase an evaluation node voltage above the
ground level (GND)
Noise may also be bootstrapping if it increases a node voltage above
the supply level (Vdd) or below the ground level
NOISE SOURCES IN DIGITAL SYSTEMS
LEAKAGE NOISE
CHARGE SHARING AND CROSSTALK NOISE
POWER SUPPLY NOISE
LEAKAGE NOISE
Leakage noise is due to the off current of FETs. It is largely due to
subthreshold current and is directly determined by the threshold voltage and
the temperature
Another leakage noise source is minority carrier back-injection into the
substrate due to bootstrapping. This is sometimes referred to as substrate
noise.
Leakage noise is a DC noise source because it changes the steady-state
logic high or low voltage value which is slowly varying with respect to the
system time
CHARGE SHARING AND CROSSTALK NOISE
It is produced by charge redistribution between a dynamic evaluation node
and internal nodes of the circuit
Crosstalk noise is the voltage induced on a node due to capacitive coupling
to a switching node of another net
Both crosstalk and charge-sharing noise are pulse noise sources, in which
the leading edge is determined by a switching signal on the chip and the
trailing edge is determined by the node impedance charging the capacitance
of the evaluation node.

POWER SUPPLY NOISE

The DC component of power supply noise is produced by the IR drop
through the power and ground nets.
The sinusoidal component of power supply noise comes from the RLC
response of the chip and package to current demands that peak at the
beginning of the clock cycle
Power supply variations vary slowly relative to circuit frequency response,
they are generally treated as DC
NOISE IN DIGITAL DYNAMIC CMOS LOGIC
Static vs Dynamic logic
Static logic always has a path from power or gnd to output
It is stable over long period and has simpler clocking schemes
Dynamic logic relies on capacitance of gates or other structures to hold
state
Dynamic logic has advantages of higher speed, lower area, low power
consumption but has a drawback of noise
STATIC VS DYNAMIC LOGIC
Static logic may recover from noise induced logic errors if there is no
loop in a circuit. Notice however that a static D flip-flop has a
feedback loop that cannot recover from noise induced errors.
Static logic contains both N and P structures that can be balanced to
obtain highest possible noise margin
If many nodes are precharged in dynamic logic, the noise levels might
be higher than for static logic.
REFERENCES
Noise in Digital Dynamic CMOS Circuits by Patrik Larsson and
Christer Svensson
Power Supply Noise Analysis Methodology for Deep-Submicron
VLSI Chip Design by Howard H. Chen and 'David D. Ling
Noise in Deep Submicron Digital Design by Kenneth L. Shepard
and Vinod Narayanan

THANK YOU!!