B.S.

Computer Science Project Report

8 BIT ADDER/SUBTRACTOR

Submitted By

Muhammad Hassan Farid

Muhammad Junaid
Huzaifa Khan
Rohail Yousaf
Muhammad Abdullah Sohail

DEPARTMENT OF COMPUTING
HAMDARD INSTITUTE OF ENGINEERING & TECHNOLOGY
HAMDARD UNIVERSITY ISLAMABAD
The design of 8-bit adder-subtractor is shown by using full adder and XOR gate. This 8-bit adder-
subtractor was programmed and simulated using DSCH v3.5, which was also demonstrated in Cadence
Virtuoso. The layout of 8-bit adder-subtractor and its components were created by using Microwind3.5
software. A Schematic simulation was run to ensure that the implementation is completely operational.
To achieve the desired output, the circuit must use determined functionality of Full adder and XOR
gates.

Table of contents:
1.Introduction

2. MATERIALS AND METHODS

3.RESULTS

4.ACKNOWLEDGEMENT

5.DISCUSSION

INTRODUCTION
1.Introduction
An 8-bit Adder-Subtractor is a circuit that is capable of performing both addition and
subtraction of binary numbers. The procedure that is performed is determined by the binary
value contained in the control signal. It is a part of the Arithmetic Logic Unit (ALU).
Complementary Metal Oxide Semiconductor (CMOS) is a manufacturing method for integrated
circuits. CMOS circuits are used in a variety of electronic components, including
microprocessors, batteries, and image sensors for digital cameras. The MOS in CMOS refers to
the transistors contained within a CMOS component, which are referred to as MOSFETs (Metal
Oxide Semiconductor Field Effect Transistor). The metal portion of the name is somewhat
misleading, as modern MOSFETs often use polysilicon as the conductive material. Each MOSFET
consists of two terminals (source and drain) and a gate that is isolated from the transistor's
body. Electrons will flow between the source and drain terminals when a sensible amount of
voltage is applied between the gate and body. The complementary component of a CMOS
circuit refers to the two distinct types of semiconductors contained within each transistor. N-
and P-type semiconductors have a higher concentration of electrons than holes or potential
electron locations. In P-type semiconductors, there are more holes than electrons. These two
semiconductors combine to form logic gates, depending on the circuit's architecture. This
project's primary objective is to develop an 8-bit adder -subtractor using CMOS

technology.

MATERIALS AND METHODS :

A Binary Adder-Subtractor is a type of digital circuit that is capable of performing both addition
and subtraction of binary numbers within the same circuit. The procedure that is performed is
determined by the binary value contained in the control signal. It is a part of the ALU
(Arithmetic Logic Unit). This circuit requires familiarity with the Exor Gate, binary addition and
subtraction, and the full adder. Two eight-bit binary numbers A and B are used as inputs to the
digital circuit for operation.
The digits are-
A0 A1 A2 A3 A4 A5 A6 A7 for A
B0 B1 B2 B3 B4 B5 B6 B7 for B
Due to the fact that we are operating on 8-bit numbers, the circuit contains eight complete full
adders. There is a control line S that contains a binary value of 0 or 1, indicating whether the
operation is addition or subtraction. C0 is serially transferred as one of the outputs of the
second full adder. The least important bit of the sum/difference
is stored as S0. A1, A2, A3, A4, A5, A6, A7 are direct inputs to the second, third, fourth, fifth,
sixth, and seventh complete adders, respectively. Then the B1, B2, B3, B4, B5, B6, B7 were
XORed with S to create the second, third, fourth, fifth, sixth, and
seventh complete adders. Carriers C1, C2, C3, C4, C5, and C6 are serially transferred as one of
the inputs to the successive complete adder. C7 becomes the sum/complete difference's carry.
The values of OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, and OUT7 are registered in order to
create the result with out0. The procedure is carried out in this circuit using a Full Adder and an
XOR gate. A brief explanation of these terms is given below.

XOR GATE:
For XOR gate the output is high when odd number inputs are high. For all other cases of inputs,
output is low. Equation: Y = A ⊕ B
Truth Table:
A B Output
0 0 0
1 0 1
0 1 1
1 1 0
XOR Gate Truth Table:

Full Adder:
The Full Adder is an adder that takes three inputs and outputs two values. A and B are the first
two inputs, while Cin is the third. The carry output is denoted by Cout, while the usual output is
denoted by S, which stands for SUM. A complete adder logic is constructed in such a way that it
can combine eight inputs to form a byte-wide adder and cascade the carry bit between adders.

Truth Table:
Input Input Input Output Output
A B Cin Sum Carry
0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1
ACKNOWLEDGEMENT:
Firstly, we want to show our gratefulness to the almighty Allah. Without His willingness this
project would not be possible to complete. Then we would like to express our sincere gratitude
to our course teacher Sir Abid Ali shah, Faculty of Engineering.

DISCUSSION
In this project, we used DSCH v3.5 and Cadence software to create an 8-bit Adder-Subtractor
with XOR Gate and Full Adder. An XOR gate and a full adder were combined together to make
an 8-bit Adder-Subtractor, which was repeated and ultimately created the 8-bit Adder-
Subtractor. We repeated the same logic 8 times. However, the output needs 9 bits instead of
just 8. There will be a carryout as two values are added. It doesn't matter if the carryout is 0,
but it does when it approaches 1. That’s why we use the Cout in the circuit. Finally, we tested
that the 8-bit Adder-Subtractor can successfully add and subtract. However, for some cases
such as greater than 28-1 or 255 is not acceptable in 8-bit Adder- Subtractor because maximum
range is 28-1 or 255.
PROJECT SOURCE CODE:

module par_addsub(a,b,cin,sum,cout);

input [7:0] a;

input [7:0] b;

input cin;

output reg [7:0] sum;

output reg cout;

reg [8:0] c;

integer i;

always @ (a or b or cin)

begin

c[0]=cin;

if (cin == 0) begin

for ( i=0; i<8 ; i=i+1)

begin

sum[i]= a[i]^b[i]^c[i];

c[i+1]= (a[i]&b[i])|(a[i]&c[i])|(b[i]&c[i]);

end

end

else if (cin == 1) begin

for ( i=0; i<8 ; i=i+1)

begin

sum[i]= a[i]^(~ b[i])^c[i];

c[i+1]= (a[i]&(~b[i]))|(a[i]&c[i])|((~b[i])&c[i]);
end

end

cout=c[8];

end

endmodule
Diagram:

Use of IC:

IC 7483
 IC 7483 is a 4 bit parallel adder which consists of four interconnected full adders along with the look ahead carry
circuit. The pin diagram of IC 7483 is shown above. It is a 16pin IC. The inputs to the IC are A, B and Cin0Cin0 while
outputs are S and Cout3Cout3.
 A3A2A1A0A3A2A1A0 is a 4 bit input word 'A' and B3B2B1B0B3B2B1B0 is the second 4 bit input word 'B'. Cin0Cin0 is
the input carry. The IC adds the two four bit words along with input carry to prooduce a 4 bit sum and a one bit carry-
out. Cout3Cout3 represents the output carry. S3,S2,S1,S0S3,S2,S1,S0 represents sum output with S3 as the MSB.
 In odrder to design an 8 bit adder, we require two IC 7483s cascaded as shown in the figure above.
 Adder-1 is the LSB adder and it adds the four LSB bits of the two 8-bit input words ie A3−A0A3−A0 and B3−B0B3−B0.
The carry input of first adder is supposed to be 0. Hence the carry in pin of LSB IC is connected to the ground. So the
first IC adds the LSB bits of A and B, and produces S3–S0S3–S0 that is, LSB of sum, along with a carry out Cout3Cout3.
 This Cout3Cout3 of adder-1 is connected to Cin0Cin0 input of Adder-2. The second adder adds this carry and the four
MSB bits of numbers A3−A0A3−A0 and B3−B0B3−B0 to produce MSB sum S7–S4S7–S4 along with final carry out
bit Cout7Cout7.
 Thus adder-1 and adder-2 when cascaded as shown in the figure can add two 8-bit words. Cout7Cout7 of adder-2 acts
as the final output carryand the sum output is from S7S7 though S0S0.