EEET

Experiment 4 : Full Adder Experiment

Name : Sakib Chowdhury
Student’s No. : F19010122
Instructor Name: Liuyan
Date of Submission: 10/05/2021
Experiment Principle:
The full-adder has three inputs and two outputs. The first two inputs are A and B
and the third input is an input carry. The second half adder logic can be used to add
input carry to the Sum produced by the first half adder to get the final sum output.

Experiment process and circuit diagram:

 At first take 74LS1138N from database.

 Take one ground, VCC.
 One Logic analyzer.
 One word generator.
 Then have to connect all the things like picture.
 We need six on page connector.
 After finish to connect everything.

Data Validation and Result:

This kind of adder is much harder than a half adder to introduce. The key
distinction between a half and an entire addition is that the complete
addition contains three inputs and two outputs. Inputs A and B are the first
two and inputs B is a C-IN input carrier. When complete adder logic is built,
we can string 8 to construct a byte-wide adder and cascade the carrying bit
from one adder to the next.
Full Adder Truth Table:

Inputs Outputs
A B C-IN SUM C-OUT
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

The whole adder logic can be applied from the above truth table. We can see that the
output S is an EXOR with B or C-IN input from input A to the half-adder Number. The
C-OUT will also apply only if any of the two out of the three inputs is Big.
So we can use two half adder circuits to implement a complete adder circuit. In order to
generate a partial Sum, the first half adds to add A and B. You can add C-IN to the sum
generated with the first half adder to get the final S output using the second half address
logic. If a carry is generated by any of the half adder logic, the output will be carried. C-
OUT therefore is an OR function for the half-adder execution.

Logical Expression for SUM:

= A’ B’ C-IN + A’ B C-IN’ + A B’ C-IN’ + A B C-IN
= C-IN (A’ B’ + A B) + C-IN’ (A’ B + A B’)
= C-IN XOR (A XOR B)
= (1,2,4,7)
Logical Expression for C-OUT:
= A’ B C-IN + A B’ C-IN + A B C-IN’ + A B C-IN
= A B + B C-IN + A C-IN
= (3,5,6,7)
Another form in which C-OUT can be implemented:
= A B + A C-IN + B C-IN (A + A’)
= A B C-IN + A B + A C-IN + A’ B C-IN
= A B (1 +C-IN) + A C-IN + A’ B C-IN
= A B + A C-IN + A’ B C-IN
= A B + A C-IN (B + B’) + A’ B C-IN
= A B C-IN + A B + A B’ C-IN + A’ B C-IN
= A B (C-IN + 1) + A B’ C-IN + A’ B C-IN
= A B + A B’ C-IN + A’ B C-IN
= AB + C-IN (A’ B + A B’)
Therefore COUT = AB + C-IN (A EX – OR B)

Show result in the picture:

Experiment Experience:
Through this experiment I have gained a new experience. This experience can be used in practice.