Course Title: Digital Design Lab

Course Code CEL122

Lab Journal

Group members:
MONEEBA HUSSAIN
FATIMA SAFA
WAHEEB AJMAL

Department of Computer Science

BAHRIA UNIVERSITY, ISLAMABAD
 Lab #: 06

Lab Title: Parity checkers and Generators

Objectives:

⮚ To learn the importance and the use of parity checkers and generators.

Tools Used:

⮚ Proteus Software ⮚ Integrated circuits

⮚ Virtual Breadboard ⮚ XOR Gate 2 input(4030)
⮚ LED indicator ⮚ NOT Gate (4069)
⮚ Input switches
⮚ Wires

Submission Date:

Evaluation: Signatures of Lab Engineer:

Task # 6.1

● Design a 3 bit even parity generator

Procedure/Program:

⮚ We design a parity generator by making its truth table and using a concept that number of 1’s of
A, B, C should be even. If it is even then the result will be 0 which means there is no error and if
it is odd then to make it even the output will be 1.
⮚ Then we simplified the expression by using Boolean algebra and its simplified form is:

P = m 1 + m2 + m4 + m7

= 001 + 010 + 100 + 111

=A’B’C + A’BC’ + AB’C’ + ABC

=A’(B’C + BC’) + A(B’C’ + BC)

= A’(B C) + A (B C)

=A B C

⮚ Lastly, we use 2 XOR gate to design a circuit diagram on proteus and breadboard.

Truth table:

A B C Parity
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
 P = ∑ (1, 2, 4, 7)

00 01 11 10
0 m0 1 m5 1
1 1 m3 1 m6
Cannot be simplified using K-map.

Circuit:

ICs of Gates:

Proteus software circuit:

Analysis/Conclusion:
The truth table is verified and done simplification through Boolean algebra.

Task # 6.2:

● Design a 3 bit odd parity generator

Procedure/Program:

⮚ We design a parity generator by making its truth table and using a concept that number of 1’s of
A, B, C should be odd. If it is odd then the result will be 0 which means there is an error and if it
is even then to make it odd the output will be 1.

P = m 0 + m3 + m5 + m6

= 000 + 011 + 101 + 110

= A’B’C’ + A’BC + AB’C + ABC’

= A’(B’C’ + BC) + A(B’C + BC’)

= A’(B C) + A(B C)

=A B C

⮚ Then we simplified the expression by using Boolean algebra and its simplified form is.
⮚ Lastly, we use 2 XOR Gate and 1 NOT Gate to design a circuit diagram on proteus and
breadboard.

Truth table:

A B C Parity
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
P = ∑ (0, 3, 5, 6)

00 01 11 10
 0 1 m1 1 m4
1 m2 1 m7 1

It cannot be simplified using K-map.

Circuit:

ICs of Gates:

Proteus software circuit:

Analysis/Conclusion:

⮚ The truth table is verified and done simplification through Boolean algebra.

Task # 6.3:

● Design a 3 bit even parity checker

Procedure/Program:

⮚ We design a parity checker by making its truth table and using a concept that number of 1’s of A,
B, C and Parity should be even. If it is even then the result will be 0 which means there is no
error and if it is odd then to make it even the output will be 1.
⮚ Then we simplified the expression by using Boolean algebra and its simplified form is.

Cp = m1 + m2 + m4 + m7 + m8 + m11 + m13 + m14

= 0001 + 0010 + 0100 + 0111 + 1000 + 1011 + 1101 + 1110

= A’B’C’P + A’B’CP’ + A’BC’P’ + A’BCP + AB’C’P’ + AB’CP + ABC’P + ABCP’

= A’B’(C’P +CP’) + A’B(C’P’ + CP) + AB’(C’P’+CP) + AB(C’P +_CP’)

 = A’B’ (C P) + A’B(C P) + AB’ (C P) + AB(C P)

= A’B’ (AB(C P) + A’B + AB’ (C P)

= (A B)(C P) +(A B)(C P)

= (A B) + (C P)

⮚ Lastly, we use 3 XOR gate to design a circuit diagram on proteus and breadboard.

Truth table:

Parity
A B C Parity
Checker
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0

Cp = ∑ (1, 2, 4, 7, 8, 11, 13, 14)

00 01 11 10
00 1 1
01 1 1
11 1 1
10 1 1

Cannot be further simplified using K-maps.

Circuit:

ICs of Gates:

Proteus software:
Analysis/Conclusion:

⮚ The truth table is verified and done simplification through Boolean algebra.

Task # 6.4:

● Design a 3 bit odd parity checker

Procedure/Program:

⮚ We design a parity generator by making its truth table and using a concept that number of 1’s of
A, B, C and Parity should be odd. If it is odd then the result will be 0 which means there is an
error and if it is even then to make it odd the output will be 1.
⮚ Then we simplified the expression by using Boolean algebra and its simplified form is.

Cp = m0 + m3 + m5 + m6 + m9 + m10 + m12 + m15

= 0000 + 0011 + 0101 + 0110 + 1001 + 1010 + 1100 + 1111

= A’B’C’P’ + A’B’CP + A’BC’P + A’BCP’ + AB’C’P + AB’CP’ + ABC’P’ + ABCP

= A’B’(C’P’ + CP) + A’B(C’P + CP’) + AB’(C’P + CP’) + AB(C’P’ + CP)

= A’B’(C P) + A’B(C P) + AB’ (C+P) AB(C P)

= A’B’ + AB(C P) + A’B + AB’ (C P)

= (A B)(C P) + (A B)(C P)

=(A B)+(A P)

⮚ Lastly, we use 3 XOR Gate and 1 NOT Gate to design a circuit diagram on proteus and
breadboard.

Truth table:

Parity
A B C Parity
Checker
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
 0 1 1 0 1
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1

Cp = ∑ (0, 3, 5, 6, 9, 10, 12, 15)

00 01 11 10
00 1 1
01 1 1
11 1 1
10 1 1
Cannot be further simplified using K-maps

Circuit:

ICs of Gates:
Proteus software

Analysis/Conclusion:

⮚ The truth table is verified and done simplification through Boolean algebra.