ECP2036 Microprocessor Systems and

Interfacing

Chapter 6:
Interfacing Examples

Objectives
At the end of this Chapter, students must be
able to interface an 8051 uC to:
Hex Keypad
LCD
External Memory
7-segment LED
8-bit ADC and DAC
8255 PPI

Definition
The interconnection, or linkage, between the microcontroller
with external devices is called interfacing.
Generally, an interface is a shared boundary between two or
more devices which involves sharing of information.
Other considerations in interfacing include synchronization,
direction of data transmission, and sometimes the
adjustment of signal levels or modes.
Address, data and control buses play an important role in
linking the parts of the system together.

ECP2036 Microprocessor and Interfacing

Real-World Interfacing
Seven
Segment

8051

LCD
Display

ADC

DAC

External address, data, & control buses

Hex
Keypad

ROM
RAM
Ex Memory

ECP2036 Microprocessor and Interfacing

I/O devices
Peripheral devices (also called I/O devices) are pieces of
equipment that exchange data with a CPU
Examples: switches, LED, CRT, printers, keyboard, keypad
Speed and characteristics of these devices are very
different from that of CPU so they cannot be connected
directly
Interface chips are needed to resolve this problem
Main function of an interface chip is to synchronize data
transfer between CPU and I/O device
Data pins of interface chip are connected to CPU data bus
and I/O port pins are connected to I/O device

ECP2036 Microprocessor and Interfacing

 Since a CPU may have multiple I/O devices, CPU

data bus may be connected to data buses of multiple
interface
An address decoder is used to select one device to
respond to the CPU I/O request
Different CPUs deal with I/O devices differently
Some CPUs have dedicated instructions for
performing input and output operations (isolated I/O)
Other CPUs use the same instruction for reading from
memory and reading from input devices, as well as
writing data into memory and writing data into output
devices (memory-mapped I/O)
8051 is memory mapped
ECP2036 Microprocessor and Interfacing

Microprocessor interfacing: I/O addressing

A microprocessor communicates with other devices using
some of its pins
Port-based I/O (parallel I/O)
Processor has one or more N-bit ports
Processors software reads and writes a port just like a
register
Bus-based I/O
Processor has address, data and control ports that
form a single bus
A single instruction carries out the read or write
protocol on the bus
ECP2036 Microprocessor and Interfacing

Types of bus-based I/O:

memory-mapped I/O and standard I/O

Processor talks to both memory and peripherals using same bus two ways to
talk to peripherals
Memory-mapped I/O
Peripheral registers occupy addresses in same address space as memory
e.g., Bus has 16-bit address
lower 32K addresses may correspond to memory
upper 32k addresses may correspond to peripherals
Standard I/O (I/O-mapped I/O)
Additional pin (M/IO) on bus indicates whether a memory or peripheral
access
e.g., Bus has 16-bit address
all 64K addresses correspond to memory when M/IO set to 0
all 64K addresses correspond to peripherals when M/IO set to 1
ECP2036 Microprocessor and Interfacing

Memory-mapped I/O vs. Standard I/O

Memory-mapped I/O
Requires no special instructions
Assembly instructions involving memory like MOV and
ADD work with peripherals as well
Standard I/O requires special instructions to move data
between peripheral registers and memory
Standard I/O
No loss of memory addresses to peripherals
Simpler address decoding logic in peripherals possible
When number of peripherals much smaller than address
space then high-order address bits can be ignored

ECP2036 Microprocessor and Interfacing

Compromises/extensions
Parallel I/O peripheral

Processor

When processor only supports bus-based I/O

but parallel I/O needed
Each port on peripheral connected to a
register within peripheral that is read/written
by the processor

Extended parallel I/O

When processor supports port-based I/O but
more ports needed
One or more processor ports interface with
parallel I/O peripheral extending total number
of ports available for I/O

Memory

System bus

Parallel I/O peripheral

Port A

Port B

Port C

Adding parallel I/O to a bus-based

I/O processor
Processor

Port 0
Port 1
Port 2
Port 3
Parallel I/O peripheral

Port A Port B Port C

Extended parallel I/O

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Serial communication - Review

Single data wire, possibly also control and power wires
Words transmitted one bit at a time
Higher data throughput with long distances
Less average capacitance, so more bits per unit of time

Cheaper, less bulky

More complex interfacing logic and communication
protocol
Sender needs to decompose word into bits
Receiver needs to recompose bits into word
Control signals often sent on same wire as data increasing
protocol complexity
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Parallel communication - Review

Multiple data, control, and possibly power wires
One bit per wire

High data throughput with short distances

Typically used when connecting devices on same
IC or same circuit board
Bus must be kept short
long parallel wires result in high capacitance values which
requires more time to charge/discharge
Data misalignment between wires increases as length increases

Higher cost, bulky

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Synchronization of CPU and interface chip

There must be a mechanism to make sure that there are
valid data in the interface chip when CPU reads them
Input synchronization: two ways of doing this
1. Polling method
interface chip uses a status bit to indicate if it has valid data
for CPU
CPU keeps checking status bit until it is set, and then reads
data from interface chip
Simple method, used when CPU has nothing else to do
2. Interrupt driven method: interface chip interrupts the
CPU when it has new data. CPU executes the ISR
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 Output synchronization: two ways of doing this

1. Polling method
interface chip uses a status bit to indicate that the data
register is empty
CPU keeps checking status bit until it is set, and then
writes data into interface chip
2. Interrupt driven method: interface chip interrupts the
CPU when it data register is empty. CPU executes the
ISR

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Synchronization of interface chip & I/O

device

Methods used to synchronize data transfer between interface chip and I/O
devices:
1. Brute force method:
- interface chip returns voltage levels in its input ports to CPU and makes
data written by CPU directly available on its output ports
- All 8051 port can perform brute force I/O
2. Strobe method:
- During input, the I/O device activates a strobe signal when data are stable.
Interface chip latches the data
- For output, interface chip places output data on output port. When data is
stable, it activates a strobe signal. I/O device latches the data
3. Handshake method: two handshake signals are needed
- One is asserted by interface chip and the other by I/O device

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Handshaking
A hardware method that can be used to achieve
synchronization is to use input/output lines, termed
handshake lines, between the microprocessor and the
peripheral to control the timing of data transfers; the
process is termed handshaking.
Handshaking usually uses two additional hardware lines,
one is called strobe and the other is called
acknowledge. The sender provides the signal to the
strobe line and the receiver provides the signal to the
acknowledge line.
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 Readiness to receive is indicated, then the data is sent. While it

is being received, the receiving device indicates not ready for
further data; the receiver indicates ready again when the
transfer has been completed.
Implementation of Handshaking
1) Hardware implementation
2) Software implementation
i) Polling - receiver polls the strobe line, sender polls the
acknowledge line
ii) Interrupt - interrupt occurs when the signal level changes

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1.

2.
3.

The sequence for an input to a microprocessor from a

peripheral:
The peripheral puts data on the data bus and sends a
DATA READY signal, also called the strobe, to the
microprocessor system.
When the CPU receives the DATA READY signal, it
knows there is data on the data bus.
The CPU then reads the data from the input/output
section and sends an INPUT ACKNOWLEDGE signal
to the peripheral. The signal indicates that the transfer
has been completed and the peripheral can send more
data.

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1.

2.
3.

The sequence for an output from a microprocessor to a

peripheral:
The peripheral sends an OUTPUT REQUEST or
PERIPHERAL READY signal to the input/output
section.
The CPU sees that the PERIPHERAL READY signal is
active and sends the data to the peripheral.
The peripheral may then send an acknowledge signal or
the next PERIPHERAL READY signal may be used to
inform the CPU that the transfer has been completed.

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 Handshaking can be implemented in 8051 by designating

two of the input/output lines for the strobe and
acknowledge signals.
DATA
EQU
STROBE EQU
ACK
EQU

WAIT

..
ORL
..
CLR
SETB
JNB
..

P1
P3.0
P3.1

P3, #03H
STROBE
STROBE
ACK, WAIT

; initial part of program

; set strobe and ack. high
; get and output data
; start strobe pulse
; finish strobe pulse
; wait for ack. signal
; continue program

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