INTERNSHIP PRESENTATION

ON ASIC DESIGN FLOW , CDC AND PLDRC TECHNIQUES

- BY

R.ROOPAK

- ICE 110113068

INTERNSHIP AT QUALCOMM
Qualcomm designs and markets wireless
telecommunication products and services.

Most of the smartphones use the chipset powered by

Qualcomm.

Worked on SOC Design

SOC System on Chip , integrated circuit that integrates all
components of a computer or other electronic system into a
single chip.

BASIC DESIGN FLOW DIAGRAM

ASIC DESIGN FLOW

 My work at Qualcomm was to analyse the design and report

the design issues.(Errors and Warnings)

Two terminologies used to analyse the design :

1. PLDRC(PROGRESSIVE LOGIC DESIGN RULE CHECK)
2.CDC(CLOCK DOMAIN CROSSING)

PLDRC
Detect issues during RTL Development.
Combines all checks into single common flow using predefined goals.
GOALS

1. Lint-Mustfix
2. Lint-Must
3. Lint-Review

4. Lint-Reset
5. DFT-Analysis
TOOL USED SPYGLASS Lint from Atrenta

CDC
A clock domain crossing occurs whenever data is transferred
from a flop driven by one clock to a flop driven by another clock.

Chip has many components, each of them powered by same

clock or different clocks.

CLOCK DOMAIN BASICS

A clock domain is a part of a design that has a clock that
operates asynchronous to, or has a variable phase
relationship with, another clock in the design.

A clock domain crossing signal is a signal from one clock

domain that is sampled by a register in another clock
domain.

IMPORTANCE OF CDC
Each component operates at its own frequency, when a CDC
signal is encountered there should be mechanism to make
the frequency in sync with other component, otherwise the
flops used will violate set up time and hold time violations
and hence output becomes metastable(0 or 1).

SYNCHRONIZERS
There are many techniques available currently for the
different schemes.

The main responsibility of a synchronizer is to allow sufficient

time such that any meta-stable output can settle down to a
stable value in the destination clock domain.
Eg

 2 FLIP FLOP SYNCHRONIZER USED IN PREVIOUS SLIDE

FIRST FLOP samples asynchronous input and waits for one
clock cycle.
SECOND FLOP sample the signal to ensure synchronized
signal is obtained.

 Different Synchronizers used:

1. 2 FF Synchronizer.
2. MUX Synchronizer
3. Handshaking data
4. FIFO
TOOL USED Questa CDC