PIC

Architecture

PIC - Harvard Architecture

ALU Features
Supports 8-bit operations
Internal data bus is of 8-bits
ALU operations between the Working register (W)
(accumulator) and register (or internal RAM) from a
register-file
ALU operations can also be between the W register and 8bits operand from instruction register.
Instruction Cycle Time - 200ns,5MIPS
The operations also use three flags Z, C and DC/borrow.
[Zero flag, Carry flag and digit (nibble) carry flag]

Data
(i) data memory for special function registers (SFR),
registers, internal RAM.
(ii) data memory EEPROM, and
(iii) separate address spaces for program memory,
interrupt vectors.
Separate internal buses
Address of 13-bit A0-A12 for the program address in
16F877.
Program code-bus of 14-bit
Data D0-D7 of 8-bit

Program Memory
Program memory 8 k 14. Program address fetch bus is of 13bit. There are thus 8192 program instruction addresses.
Program counter is thus of 13-bit word pointing to one of the
8 k (8192) addresses in program memory (flash).
Instruction
Instruction length 14-bit
Program-code bus 14-bit.
Flash saves 14-bits at each address

 MUX and ADDRMUX

-MUX takes 8-bit input from either 8 bit instruction
register during the instruction with immediate
addressing.
-ADDRMUX takes 8 bit input indirect address bits
or 7 bits direct address from IR(instruction register)
during instruction immediate addressing or branch
or call instruction. It gives 9-bit output address for
register/RAM

 Register File/RAM
4 banks
Each bank has 128 addresses and it can be accessed by the
RP1:RP0 bits in STATUS register.
B0: 00-7F (7 bit address),
B1: 80-FF , B2:100-17F,
B3: 180-1FF(9-bit address)
4 banks form 2 pairs of bank (lower:B0&B1, upper:B2&B3)

RAM/File Register Select(FSR)

- It provides the 8-bit address of RAM/register in the register file.
It is used for indirect addressing in the instruction

 STATUS REGISTER
-

Bit 0,1,2- C,DC(digit carry),Z

Bit 3- Power down; 0- sleep, 1- power up
Bit 4- Time out ; 0- WDT Time out occurred
Bit 5,6- RP0,RP1; 00-bank0, 01- bank1, 10- bank2,
11-bank3
- Bit 7- IRP(Indirect Register Pair); 0- lower bank pair
used, 1- upper bank pair used. For indirect
addressing(8 bit data)

 Memory and Peripherals in Architecture of

PIC16F877.
The synchronous serial port : Universal Asynchronous Receiver
Transmitter(USART).
There are two 8bit timers, TMR0 and TMR2 (2 X 8 bit).
There is one 16 bit timer, TMR1 (1 X 16 bit).
There is CCP1,2. It has two capture/compare/PWM peripherals
for input capture, out-compare and pulse width modulation
functions.
There is 8-input channel 10 bit ADC.

Ports:
There are five Ports 6 bit PORT A,
8-bit PORT B,
8-bit PORT C,
8 bit PORT D,
3 bit PORT E.
Each port has a data-direct register TRIS. TRIS (Transmit Receive
Input Select) bit controls the direction of a port pin, whether it will be
for input or for output.
Parallel Slave Port(Port D & E): PSP is handshake mode port in which
Port D pins are used for PSP input/output and Port E pins are used for
control signals RD,WR and CS.
PORT D can either function as general purpose port or PSP.

 There is interrupt control circuit. INTCON is used for

defining control bits for timer 0 overflow, port B input
change and external pin INT interrupts.
It also defines the global interrupt enable and peripherals
interrupt (service) enable.

PIC 16F877 Instruction Set

Pipeline and Superscalar Unit

Pipeline
Two instructions In and In+1 execute parallel at
separate execution units.

Superscalar Execution

 A Superscalar machine executes multiple independent

instructions in parallel.
They are pipelined as well.
Common instructions (arithmetic, load/store, conditional
branch) can be executed independently.
Equally applicable to RISC & CISC, but more straightforward
in RISC machines.
The order of execution is usually assisted by the compiler.
Two or more consecutive instructions in the original program
order can execute in parallel
- This is the dynamic execution order
N-way Superscalar
- Can issue up to N instructions per cycle
- 2-way, 3-way,

Example of Superscalar
Organization

2 Integer ALU pipelines,

2 FP ALU pipelines,
1 memory pipeline

Superscalar vs. Pipelining

Pipeline
fetch

decode
fetch

Superscalar:
fetch

decode
fetch
fetch

ld
decode
fetch
ld
decode
decode
fetch

time
add
decode
fetch
add
sub
decode

sub
decode

bne

bne

Superscalar v Superpipelined

Limitations of Superscalar
-

Data dependency

- Procedural dependency
- Resource conflicts

Data Dependency
LOAD
MOVE

r1, X

x (memory) r1

r3, r1

r1 r3

Cannot execute second instruction until first is finished

Second instruction is dependent on first (R after W)

ADD

R4, R3, 1

R3 + 1 R4

ADD

R3, R5, 1

R5 + 1 R3

Cannot complete the second instruction before the first has

read R3 ( R before W).

Procedural Dependency
Cant execute instructions after a branch in parallel
with instructions before a branch.
Also, if instruction length is not fixed, instructions
have to be decoded to find out how many fetches are
needed

Resource Conflict
Two or more instructions requiring access to the
same resource at the same time
- e.g. two arithmetic instructions need the ALU
Solution - Can possibly duplicate resources
- e.g. have two arithmetic units

View of Superscalar Execution

Superscalar Hardware Support

Facilities to simultaneously fetch multiple instructions
Logic to determine true dependencies involving register
values and Mechanisms to communicate these values
Mechanisms to initiate multiple instructions in parallel
Resources for parallel execution of multiple instructions
Mechanisms for committing process state in correct
order

Address Translation

Virtually addressed Memory System

MMU accepts logical addresses from the CPU. Logical addresses

refer to the programs abstract address space but do not correspond
to actual RAM locations.
The MMU translates them from tables to physical addresses that
do correspond to RAM.
By changing the MMUs tables, the physical location at which
the program resides can be changed, without modifying the
programs code or data.

 In a virtual memory system, the MMU keeps track of

which logical addresses are actually resident in main
memory; those that do not reside in main memory are
kept on the secondary storage device.
When the CPU requests an address that is not in main
memory, the MMU generates an exception called a
page fault.
The handler for this exception executes code that
reads the requested location from the secondary
storage device into main memory.

 Types of Address translation

- Segmented
A segment is usually
described by its start address
and size, allowing different
segments to be of different
sizes.
- Paged
. Pages are of uniform size,
which simplifies the
hardware required for
address translation.

page 1
page 2
segment 1
memory

segment 2

Segments and pages

Segment:
- designed to support a large, arbitrarily sized region of
memory
- specified by start address and size, thus allowing different
segments to be of different sizes

Pages:
- describe small, equally sized regions
- uniform size & simplifies the hardware required for
address translation

segmented, paged scheme:

- is created by dividing each segment into pages and using
two steps for address translation

Segment address translation

segment base address

logical address

segment lower bound

segment upper bound

range
check

physical address

2008 Wayne Wolf

Overheads for Computers as

Components 2nd ed.

range
error

 The MMU would maintain a segment register that

describes the currently active segment.
This register would point to the base of the current
segment.
The address extracted from an instruction (or from
any other source for addresses, such as a register)
would be used as the offset for the address.
The physical address is formed by adding the
segment base to the offset.
Most segmentation schemes also check the physical
address against the upper limit of the segment by
extending the segment register to include the segment
size and comparing the offset to the allowed size.

Page address translation

page

offset

page i base
concatenate

page

2008 Wayne Wolf

Overheads for Computers as

Components 2nd ed.

offset

 The logical address is divided into two sections,

including a page number and an offset.
The page number is used as an index into a page
table, which stores the physical address for the start
of each page.
MMU simply needs to concatenate the top bits of the
page starting address with the bottom bits from the
page offset to form the physical address.

Page table organizations

page
descriptor
page descriptor

flat
2008 Wayne Wolf

tree
Overheads for Computers as
Components 2nd ed.