Accessing I/O Devices

Processor Memory

BUS

I/O Device 1 I/O Device 2

 Parallel I/O
I/O devices connect to processor through PORTS
Ports are:
registers (part of the I/O interface)
8, 16, or 32 bits wide

Addressed in the range 0000-FFFFh

Accessed with 2 instructions IN, OUT
 Modes of I/O Instructions
Direct I/O the port address is one of the operands.
Address must be 00-FFh.
IN AL, 27h
Data flows through the accumulator
MOV AX, BX
OUT 26h, AX ; move 16-bit data from AX to port
; 26h (AL to 26h and AH to 27h)
Indirect I/O the port address is preloaded into DX
Address can be 0000-FFFFh
String I/O allows data to pass directly through the
accumulator (from I/O device to memory)
 80x86 I/O Instructions
Type Instruction Description
Direct IN AL, port input data to accumulator
IN AX, port port must be in range 00-FFh
IN EAX, port

OUT port, AL output data from accumulator

OUT port, AX port must be in range 00-FFh
OUT port, EAX

Indirect IN AL, DX input data to accumulator

IN AX, DX port address in DX must be in range 0000-FFFFh
IN EAX, DX

OUT DX, AL output data from accumulator

OUT DX, AX port address in DX must be in range 0000-FFFFh
OUT DX, EAX

String INSB input data to memory location DS:SI or DS:ESI

INSW port address in DX must be in range 0000-FFFFh
INSD

OUTSB output data from memory location DS:SI or DS:ESI

OUTSW port address in DX must be in range 0000-FFFFh
OUTSD
 Ways to Differentiate I/O
Memory-Mapped versus I/O-Mapped Ports
address of 80x86 processors is divided into 1M, 4GB,
or 64GB of memory space and 64K of I/O space.
Memory Space
20-, 32-, or 36-bit
address

I/O Space

address
16-bit
M/IO = 0
M/IO = 1
With memory-mapped I/O, because I/O ports are
mapped to a memory address, any of the memory
read/write instructions are available to use. Address
can be computed using any of the addressing modes.
With I/O mapped ports, restricted to simple IN/OUT
instructions. Address must be in DX.
 Memory-Mapped I/O
I/O Devices and memory share the same
address space.
Each I/O Device is assigned a unique set of addresses.
When the processor places a particular address on the
address lines, the device recognizing this address
responds to the commands on the control lines.
The processor requests either a read or a write
operation, and the requested data is transferred over the
data lines.
Any machine instruction that can access memory can
be used to transfer data to/from I/O devices.
Mov datain, R0
 Intel Architecture
Intel processors have a separate 16-bit address
bus for I/O devices
Designer has the option of
connecting I/O devices to use special address space
or simply incorporating them as part of the memory
address space.
The later approach leads to simpler software.
One advantage of a separate address bus for I/O is
reduced number of address lines needed for I/O
devices.
Not physically separate address lines on processor.
Special signal (I/OR or I/OW, MemR or MemW)
Ways to Drive Hardware Devices
using Parallel Buses
Programmed I/O through I/O ports

Interrupt I/O using (hardware) interrupts

Direct Memory Access

 Programmed I/O
(driving Hardware devices through I/O ports)

External devices are almost always connected not

directly to the system bus but to an INTERFACE.
Registers in the interface allow for a wide range
of possibilities for the designer to determine how
it is to interface to the bus.
TO avoid confusion with the main registers in the
8086, peripheral interface chip registers are
usually referred to as PORTS.
 Interface Ports
Typically consists of three registers
Control Port - the setting of which will determine if the
interface is to send or receive.
Data Port for the data element to be transmitted or to
hold a data element received.
Status Port used to obtain information such as
printer out of paper, dont send any more data or, for
a serial transmission, all the bits of the data element
havent yet been received
Simple interfaces may have status and control
combined into one port; sophisticated ports may have
multiple control and status ports.
 I/O Interface for an Input Device
Address Lines
Data Lines
Control Lines

Address Control Data and

Decoder Circuits Status Registers

I/O Interface

Input Device
 I/O Device Speeds
Processors can operate at speeds that are vastly
different than I/O speeds.
When a human is entering characters on a keyboard,
the processor can execute millions of instructions
between successive character entries.

So, how does the processor handle I/O inputs..

 Three types of I/O Strategies
Polled I/O

Interrupt Driven I/O

DMA I/O
Polled IO versus Interrupt Driven I/O
Polled IO processor continually checks IO
device to see if it is ready for data transfer
Inefficient, processor wastes time checking for ready
condition
Interrupt Driven IO IO device interrupts
processor when it is ready for data transfer
Processor can be doing other tasks while waiting for
last data transfer to complete very efficient.
 I/O Interfacing
A lot of handshaking is required between
the CPU and most I/O devices.
All I/O devices operate asynchronously
with respect to the CPU. The events that
determine when an input device has data
available or when an output device needs
data are independent of the CPU.
 Three I/O strategies
Must be capable of data rates fast enough to
keep up with the demands of the device, but
must not be allowed to transfer data faster
than the device can process it.
Polled waiting loops
Interrupt-driven I/O
Direct memory Access (DMA)
 Synchronization
The CPU must have some way of checking
the status of the device and waiting until it
is ready to transfer
 Transfer Rate
A measure of the number of bytes per
second transferred between the CPU and an
external device.
Maximum transfer rate a measure of the
bandwidth capability of a particular method
of doing I/O.
 Comparison of transfer rates
Polled waiting loops provide data rates that are a
bit slower, but still quite reasonable.
Interrupt-driven I/O requires overhead of saving
and restoring the machine state (significantly
degrades data rates unless more than one byte can
be transferred per interrupt.
DMA has fastest transfer rates (additional
hardware complexity needed.
 Latency
Measure of the delay from the instant that
the device is ready until the time the first
data byte is transferred. Latency is
equivalent to the response time
 Comparison of Latency
Polled Waiting Loops latency can be very
high (the computer may not even be
checking the device for new data when it
arrives).
Interrupt-driven I/O dramatically lower
than polled, but still imposes a software
overhead.
DMA very low (lower than the others)
 Polled Waiting I/O
Use software to test the status of a
device,before transferring each data byte.
Continuously checking the peripherals
BUSY/READY flag
Ties up the CPU no other tasks can be
performed.