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Superscalar Architecture
Superscalar Architecture
With Register Renaming, the first write to r3 maps to hw3,while the second write
maps to hw20.This converts four instruction dependency chain into 2 two instructions
chains, which can then be executed in parallel if the processor allows out of order
execution.
http://en.wikipedia.org/wiki/Superscalar
http://www.seas.gwu.edu/~bhagiweb/cs211/lectures/superscalar.pdf
LIMITATION OF SUPERSCALAR MICROPROCESSOR PERFORMANCE
THANG TRAN ,ADVANCED MICRO DEVICES, INC. AUSTIN, TEXAS 78741 AND CHUAN-LIN WU,DEPARTMENT OF ELECTRICAL
AND COMPUTER ENGINEERING