RISC CISC

MACHINE MACHINE INSTRUCTIONS

INSTRUCTIONS
MICROCODE
CONVERSION
INSTRUCTION MICROINSTRUCTION
EXECUTION
MICROINSTRUCTION
EXECITION
 RISC ARCHITECTURE
HARDWIRED
DATA PATH
CONTROL UNIT

INSTRUCTION
DATA CACHE
CACHE

MAIN MEMORY
 CISC ARCHITECTURE
INSTRUCTION
CONTROL UNIT
AND DATA PATH

MICROPROGRAM
CONTROL CACHE
MEMORY

MAIN MEMORY
8051 MICROCONTROLLER

TIMER 1
INTERRUPT CONTROL ROM RAM
TIMER 0

CPU
BUS I/O SERIAL
OSC CONTROL PORTS PORT
BASIC PROCESSOR

I/O
ALU PORTS

REGISTERS
FETCH

DECODE

EXECUTE

WRITE
Instruction
Fetch
Decode Non – pipelined
Execute
Write
Clock
Instruction
Fetch
Decode Pipelined
Execute
Write
Clock
 COMPILED AND
UPLOADEDCODES

HOST USB
SIGNALS

USB
CONNECTOR

SERIAL
INTERFACE

ARDUINO UNO
 CENTRAL PROCESSING UNIT

CONTROL UNIT

INPUT ARITHMETIC/LOGIC OUTPUT

DEVICE UNIT DEVICE

MEMORY UNIT
No. of transistors

Date that introduced

 INSTRUCTION
CONTROL UNIT
AND DATA PATH

CACHE

MAIN MEMORY