Semiconductor Manufacturing Technology:

Semiconductor Manufacturing Processes

Conrad T. Sorenson
Praxair, Inc.

 1999 Arizona Board of Regents for The University of Arizona

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NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 1
 Semiconductor Manufacturing Processes
Wafer
Design
Preparation
• Design
• Wafer Preparation Thin Films
Front-End
Processes
• Front-end Processes
• Photolithography Photo-
lithography
• Etch
• Cleaning
Ion
Etch
• Thin Films Implantation

• Ion Implantation
• Planarization Cleaning Planarization

• Test and Assembly

Test &
Assembly

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 Design

Wafer
Design
Preparation

• Establish Design Rules Thin Films

Front-End
Processes
• Circuit Element Design
• Interconnect Routing Photo-
lithography

• Device Simulation
• Pattern Preparation Ion
Implantation
Etch

Cleaning Planarization

Test &
Assembly

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 Pattern Preparation
Reticle

Chrome Pattern Pellicle

Quartz Substrate

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 Wafer Preparation

Wafer
Design
Preparation

• Polysilicon Refining Thin Films

Front-End
Processes

• Crystal Pulling
Photo-
• Wafer Slicing & Polishing lithography

• Epitaxial Silicon Deposition Ion

Etch
Implantation

Cleaning Planarization

Test &
Assembly

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 Polysilicon Refining

Chemical Reactions
Silicon Refining: SiO2 + 2 C  Si + 2 CO
Silicon Purification: Si + 3 HCl  HSiCl3 + H2
Silicon Deposition: HSiCl3 + H2  Si + 3 HCl

Reactants
H2
Silicon Intermediates
H2SiCl2
HSiCl3

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 Crystal Pulling
Quartz Tube
Rotating Chuck
Seed Crystal
Process Conditions
Flow Rate: 20 to 50 liters/min Growing Crystal
Time: 18 to 24 hours (boule)
Temperature: >1,300 degrees C
Pressure: 20 Torr

RF or Resistance
Heating Coils
Materials
Polysilicon Nodules * Molten Silicon
Ar * (Melt)
H2 Crucible

* High proportion of the total product use

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 Wafer Slicing & Polishing
silicon wafer

p+ silicon substrate

The silicon ingot is sliced into

individual wafers, polished, and
cleaned.

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3/15/98 PRAX01C.PPT Rev. 1.0
 Epitaxial Silicon Deposition
silicon wafer

Gas
p- silicon epi layer Susceptor Input Lamp
p+ silicon substrate
Module

Chemical Reactions Quartz

Silicon Deposition: HSiCl3 + H2  Si + 3 HCl Lamps
Process Conditions
Flow Rates: 5 to 50 liters/min
Temperature: 900 to 1,100 degrees C. Wafers
Pressure: 100 Torr to Atmospheric

Silicon Sources Dopants Etchant

SiH4 AsH3 HCl
H2SiCl2 B2H6 Carriers
Exhaust
HSiCl3 * PH3 Ar
SiCl4 * H2 *
N2 * High proportion of the total product use
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 Front-End Processes

Wafer
• Thermal Oxidation Preparation
Design

• Silicon Nitride Deposition Front-End

Thin Films
Processes
- Low Pressure Chemical Vapor
Deposition (LPCVD) Photo-
lithography
• Polysilicon Deposition
- Low Pressure Chemical Vapor Ion
Etch
Implantation
Deposition (LPCVD)
• Annealing Cleaning Planarization

Test &
Assembly

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 Front-End Processes
Vertical LPCVD Furnace

silicon dioxide (oxide)

Exhaust Via
Vacuum Pumps
and Scrubber
p- silicon epi layer
p+ silicon substrate
Chemical Reactions Quartz Tube
Thermal Oxidation: Si + O2  SiO2
Nitride Deposition: 3 SiH4 + 4 NH3  Si3N4 + 12 H2
Polysilicon Deposition: SiH4  Si + 2 H2 3 Zone
Process Conditions (Silicon Nitride LPCVD) Temperature
Flow Rates: 10 - 300 sccm Control
Temperature: 600 degrees C.
Pressure: 100 mTorr
Oxidation Polysilicon Nitride Annealing
Ar H2 NH3 * Ar
N2 N2 H2SiCl2 * He
H2O SiH4 * N2 H2 Gas Inlet
Cl2 AsH3 SiH4 * N2
H2 B2H6 SiCl4
HCl * PH3
O2 * * High proportion of the total product use
Dichloroethene * Sorenson
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 Photolithography

Wafer
Design
Preparation

• Photoresist Coating Processes Thin Films

Front-End
Processes
• Exposure Processes
Photo-
lithography

Ion
Etch
Implantation

Cleaning Planarization

Test &
Assembly

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 Photoresist Coating Processes

photoresist
field oxide

p- epi

p+ substrate

Photoresists
Negative Photoresist *
Positive Photoresist *
Other Ancillary Materials (Liquids)
Edge Bead Removers *
Anti-Reflective Coatings *
Adhesion Promoters/Primers (HMDS) *
Rinsers/Thinners/Corrosion Inhibitors *
Contrast Enhancement Materials *
Developers
TMAH *
Specialty Developers *
Inert Gases
Ar
N2
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 Exposure Processes

photoresist
field oxide

p- epi

p+ substrate

Expose
Kr + F2 (gas) *
Inert Gases
N2

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 Ion Implantation

Wafer
Design
Preparation

• Well Implants Thin Films

Front-End
Processes
• Channel Implants
• Source/Drain Implants Photo-
lithography

Ion
Etch
Implantation

Cleaning Planarization

Test &
Assembly

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 Ion Implantation Focus Beam trap and
gate plate
Neutral beam and
beam path gated

phosphorus
(-) ions photoresist mask

junction field oxide

depth
n-w ell p- epi
p-channel transistor
p+ substrate Neutral beam trap Y - axis X - axis Wafer in wafer
and beam gate scanner scanner process chamber
Process Conditions
Flow Rate: 5 sccm
Pressure: 10-5 Torr
Equipment Ground
Accelerating Voltage: 5 to 200 keV Resolving
Aperture 180 kV
Gases Solids
Ar Ga
AsH3 In Acceleration Tube
B11F3 * Sb
He Liquids 90° Analyzing Magnet
N2 Al(CH3)3
PH3 Terminal Ground
SiH4
SiF4 Ion Source 20 kV
GeH4 * High proportion of the total product use
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 Etch

Wafer
Design
Preparation

• Conductor Etch Thin Films

Front-End
Processes
- Poly Etch and Silicon Trench
Etch Photo-
lithography
- Metal Etch
• Dielectric Etch Ion
Implantation
Etch

Cleaning Planarization

Test &
Assembly

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 Conductor Etch
source-drain areas
gate linew idth Cluster Tool Etch
gate oxide Configuration Chambers
n-w ell p-w ell
p-channel transistor n-channel transistor Wafers
p+ substrate Transfer
Chamber
Chemical Reactions Loadlock
Silicon Etch: Si + 4 HBr  SiBr4 + 2 H2
Aluminum Etch: Al + 2 Cl2  AlCl4
Process Conditions
Flow Rates: 100 to 300 sccm RIE Chamber Gas Inlet
Pressure: 10 to 500 mTorr
RF Power: 50 to 100 Watts
Wafer
Transfer
Polysilicon Etches Aluminum Etches Chamber
HBr * BCl3 * RF Power
C2F6 Cl2
SF6 * Diluents
NF3 * Ar
O2 He Exhaust
N2 * High proportion of the total product use
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 Dielectric Etch
Contact locations

Cluster Tool Etch

Configuration Chambers
n-w ell p-w ell
p-channel transistor n-channel transistor Wafers
p+ substrate Transfer
Chamber
Chemical Reactions Loadlock
Oxide Etch: SiO2 + C2F6  SiF4 + CO2 + CF4 + 2 CO
Process Conditions
Flow Rates: 10 to 300 sccm
Pressure: 5 to 10 mTorr RIE Chamber Gas Inlet
RF Power: 100 to 200 Watts
Wafer
Transfer
Plasma Dielectric Etches Diluents Chamber
CHF3 * CO2 Ar RF Power
CF4 O2 He
C2F6 SF6 N2
C3F8 SiF4
CO * Exhaust
* High proportion of the total product use
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 Cleaning

Wafer
Design
Preparation

• Critical Cleaning Thin Films

Front-End
Processes

• Photoresist Strips
Photo-
• Pre-Deposition Cleans lithography

Ion
Etch
Implantation

Cleaning Planarization

Test &
Assembly

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 Critical Cleaning
Contact locations

n-w ell p-w ell

p-channel transistor n-channel transistor
p+ substrate

Process Conditions
1 2 3 4 5
Temperature: Piranha Strip is 180 degrees C.
1 Organics 2 Oxides 3 Particles 4 Metals 5 Dry
H2SO4 + HF + NH4OH + HCl + H2O or IPA +
H2O2 H2O H2O2 + H2O H2O2 + H2O N2
H2O Rinse H2O Rinse H2O Rinse H2O Rinse

RCA Clean Nitride Strip Dry Strip Solvent Cleans

SC1 Clean (H2O + NH4OH + H2O2) * H3PO4 * N2O NMP
* SC2 Clean (H2O + HCl + H2O2) * Oxide Strip O2 Proprietary Amines (liquid)
Piranha Strip HF + H2O * CF4 + O2 Dry Cleans
* H2SO4 + H2O2 * HFO3
O2 Plasma
Alcohol + O3 Sorenson
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 Thin Films

Wafer
• Chemical Vapor Deposition Preparation
Design

(CVD) Dielectric
Front-End
Thin Films
• CVD Tungsten Processes

• Physical Vapor Deposition Photo-

lithography
(PVD)
• Chamber Cleaning Ion
Etch
Implantation

Cleaning Planarization

Test &
Assembly

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 Chemical Vapor Deposition (CVD) Dielectric
insulator layer 2
Metal 1
Metering Inert Mixing
Pump Gas

n-w ell p-w ell TEOS

p-channel transistor n-channel transistor
p+ substrate
Source
Vaporizer
Chemical Reactions Direct
Si(OC2H5)4 + 9 O3  SiO2 + 5 CO + 3 CO2 + 10 H2O Liquid Process Gas
Process Conditions (ILD) Injection
Flow Rate: 100 to 300 sccm
Pressure: 50 Torr to Atmospheric LPCVD Gas Inlet
Chamber
CVD Dielectric
Wafer
O2 Transfer
O3 Chamber
TEOS * RF Power
TMP *

Exhaust
* High proportion of the total product use
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 Chemical Vapor Deposition (CVD) Tungsten
titanium tungsten

Input
Cassette
n-w ell p-w ell
p-channel transistor n-channel transistor
p+ substrate
Output
Cassette
Chemical Reactions
WF6 + 3 H2  W + 6 HF Wafer
Process Conditions Wafers
Hander
Flow Rate: 100 to 300 sccm
Pressure: 100 mTorr Multistation Sequential
Temperature: 400 degrees C. Deposition Chamber
CVD Dielectric
WF6 * Water-cooled
Ar Showerheads
H2
N2
Resistively
Heated Pedestal

* High proportion of the total product use

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 Physical Vapor Deposition (PVD)
Physical
Cluster Tool Vapor
Configuration Deposition
n-w ell p-w ell Chambers
p-channel transistor n-channel transistor Wafers
p+ substrate Transfer
Chamber

Loadlock
Process Conditions
Pressure: < 5 mTorr
Temperature: 200 degrees C.
RF Power: Reactive
PVD Chamber
Gases
N S N

Barrier Metals e-
Cryo Pump
Transfer
+
SiH4 Chamber
Wafer
Ar
N2
N2
Argon & Backside DC Power
Ti PVD Targets *
Nitrogen He Cooling Supply (+)

* High proportion of the total product use

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 Chamber Cleaning Multistation Sequential
Deposition Chamber

Water-cooled
Showerheads

Resistively
Heated Pedestal
Chemical Reactions
Oxide Etch: SiO2 + C2F6  SiF4 + CO2 + CF4 + 2 CO
Process Conditions
Flow Rates: 10 to 300 sccm
Pressure: 10 to 100 mTorr Aluminum
RF Power: 100 to 200 Watts
Surface Coating
Chamber Cleaning
C2F6 * Process Material Residue
NF3
ClF3
Chamber Wall Cross-Section

* High proportion of the total product use

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 Planarization

Wafer
Design
Preparation

• Oxide Planarization Thin Films

Front-End
Processes

• Metal Planarization
Photo-
lithography

Ion
Etch
Implantation

Cleaning Planarization

Test &
Assembly

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 Chemical Mechanical Planarization (CMP)
Platen
Head
Sweep Slide
Polishing
n-w ell p-w ell
Head
p-channel transistor n-channel transistor Load/Unload
p+ substrate
Station Pad
Process Conditions (Oxide) Conditioner
Flow: 250 to 1000 ml/min Wafer Handling Carousel
Particle Size: 100 to 250 nm Robot & I/O
Concentration: 10 to 15%, 10.5 to 11.3 pH
Process Conditions (Metal)
Flow: 50 to 100 ml/min
Particle Size: 180 to 280 nm Wafer
Concentration: 3 to 7%, 4.1 - 4.4 pH Carrier Polishing Pad
Slurry
Backing (Carrier) Film CMP (Oxide) Delivery
Polyurethane Silica Slurry *
Pad KOH * Wafer
Polyurethane NH4OH
Pad Conditioner H2O
Abrasive CMP (Metal) Platen
Alumina * * High proportion of the total product use.
FeNO3 Sorenson
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 Test and Assembly

Wafer
Design
Preparation

• Electrical Test Probe Thin Films

Front-End
Processes

• Die Cut and Assembly

Photo-
• Die Attach and Wire Bonding lithography

• Final Test
Ion
Etch
Implantation

Cleaning Planarization

Test &
Assembly

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 Electrical Test Probe
bonding pad
nitride
Metal 2

n-well p-well
p-channel transistor n-channel transistor
p+ substrate

Defective IC

Individual integrated circuits

are tested to distinguish good
die from bad ones.
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 Die Cut and Assembly

Good chips are attached

to a lead frame package.

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 Die Attach and Wire Bonding

lead frame gold wire

bonding pad

connecting pin

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 Final Test

Chips are electrically

tested under varying
environmental conditions.

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 References

1. CMOS Process Flow in Wafer Fab, Semiconductor Manufacturing Technology, DRAFT,

Austin Community College, January 2, 1997.
2. Semiconductor Processing with MKS Instruments, Inc.
3. Worthington, Eric. “New CMP architecture addresses key process issues,” Solid State
Technology, January 1996.
4. Leskonic, Sharon. “Overview of CMP Processing,” SEMATECH Presentation, 1996.
5. Gwozdz, Peter. “Semiconductor Processing Technology” SEMI, 1997.
6. CVD Tungsten, Novellus Sales Brochure, 7/96.
7. Fullman Company website. “Fullman Company - The Semiconductor Manufacturing
Process,” http://www.fullman.com/semiconductors/index.html, 1997.
8. Barrett, Craig R. “From Sand to Silicon: Manufacturing an Integrated Circuit,” Scientific
American Special Issue: The Solid State Century, January 22, 1998.

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