SOC & Embedding System Group

 Embedding System
 Embedded OS –
 Multimedia –
 Low power mobile –
 Storage – 張立平
 SOC Design & CAD
 Network – 林盈達
 Architecture and Systems – 鍾崇斌、單智君
 Wireless base-band Processor – 許騰尹
 Multimedia SOC Design – 蔡淳仁 , 彭文孝
 Electrical Design Automation – 李毅郎
 Research
Interests

Chien-Chao Tseng 曾建超

網路工程研究所
系統設計研究所

交通大學資訊學院
cctseng@csie.nctu.edu.tw
 Wireless Access to Internet
Internet WLAN/Bluetooth/
GPRS/3G/PHS/
WiMax/... PAN/...
Mobile NW

Ad hoc
: -) s
Ad hoc s ts o ff
Mesh
er e n d
I n t H a
y n d
•3G/GPRS/PHS M n g a
i
•WiMax/WLAN/Bluetooth/PAN
o am
R
Heterogeneous Wireless Overlay Networks
– Multi-interface Handheld Devices
 Embedded OS for Multi-interface Handh
eld Devices
 Cross-layer design for Real-time Applications
 Linux/Windows XP/CE
 Driver, Network, and Application Layers (VoIP)
 Heterogeneous Wireless Networks
 WLAN/WiMax/3G/GPRS/PHS3G/GPRS
PHS
 Roaming and Handovers
 Multi-tier Wireless Network
 WPAN, WLAN and Mobile Router
 Roaming and Routing
 Wireless Mesh and Sensor Networks
Embedded
WLAN
 Address Assignment and Routing
 Secured and Fast Accesses to Wireless
Network
Embedded Systems ( 曹孝櫟助理教授 )
Research Directions

 Embedded Software for B3G/4G Mobile Devic

es
 Protocol Stacks for 4G access
 Embedded Operating System and Device Driv
ers, and their Optimization for Mobile Device
s
 Cooperate with international and local vendor
s and institutes to development 4G/multimod
e radio SOC
 Establish the reference embedded software fo
r next generation mobile devices/Radio SoCs
 Embedded Systems ( 曹孝櫟助理教授 )
Low Power and Fast Handover
R&D Results - Cellular/WLAN Dual Model Mobiles
C e llu la r/ Vo WLAN in te g ra te d UA
Mo b ility Po w e r SIP/ SIMPLE C e llu la r
m a na g e m e nt m a na g e m e nt UA/ Sta c k c a ll c o n tro l

Win So c k
Win C E/ TAPI
TC P/ IP
Sm a rtp h o n e 2003
NDIS d rive r d e vic e d rive r
WLAN in te rfa c e G SM in te rfa c e
Power Consumption Evaluation
PDA/ Sm a rtp h o n e H/ W Pla tfo rm

System Architecture and

Prototype of Cellular/WLAN
Dual Mode Mobile

Awarded by Handover Latencies Evaluation

2005 Mobile Communications Contest of Industrial Development Bureau, MOEA
2005 Software Contest of National Center of High-Performance Computing
2006 Embedded Software Contest of MOE
Prof. Li-Pin Chang 張立平
 Recent research directions
 Embedded storage systems
 Real-time systems and scheduling
algorithms
 Hardware-software co-design
 Embedded Storage:
Efficient wear-leveling algorithm for flash memory
 To capture uneven usages from millions of blocks and to
level them
 Result: the most fast, effective, economic approach
available!!
40,000,000
160000

35,000,000
140000 Worn-out quickly!

Erase cycle #
30,000,000
120000

25,000,000
100000
LBA

20,000,000
80000

15,000,000
60000

10,000,000
40000

5,000,000
20000

0
0 500 1,000 1,500 2,000 2,500 3,000 3,500
0
1 18 35 52 69 86 103 120 137 154 171 188 205 222 239 256 273 290 307 324 341

Time Block #

Access pattern Block usage

 Real-Time Systems:
Overload Management for Real-Time Object Tracking

Inter-arrival time of frames : 4ms. Workload-scaling factor: 4/7 (57%)

Average RMS error Firm-real-time: Average RMS error Proportional Adjustment:

(c,4)((4,7),c,4) (c,4)(c,7)

(1,4) (1,4)
 
i i

drop drop
FE PP
'
" ((4,7),2,4) j (2,7)
j
Hardware-Software Co-design
Reconfigurable computing for overload management

 Reconfigurable computing for overloa

d management
 Past achievement:
 Overload management for event-driven

real-time embedded systems

 Working-in-progress:
 To deal with transient workload bursts

with hardware acceleration

 Move critical tasks onto FPGA

• Computing resource reclamation

• On-line floor planning
• On-line topology reconfiguration for networ
k-on-chip (NoC)
Embedded Systems ( 蔡文錦 ) -
Research Directions
 Low-power embedded systems
 Video compression/decompression
Plan in the near future

 Low-power AVC/H.264 video CODEC

algorithm and system design
Multimedia Embedded Systems Lab
( 蔡淳仁 ) – Research Directions

 SoC Design for Advanced Video Codecs

 DVB/MHP middleware & Java Runtime
 Java Processor for DVB/MHP
 Flexible Multimedia Codec SoC Platforms
 OS Kernel Scheduler for Tightly-coupled H
eterogeneous Multi-core Platforms
Multimedia Embedded Systems Lab
R&D Results
 H.264 Codec Accelerators on ARM Integra
tor
 Java Processor Accelerating Technologies
on Spartan 3 and ML-310 Platforms (base
d on the open source JOP project)
 Video Rate Control for HW/SW Co-design
ed SoCs (patent application)
 Tightly-coupled H.264 encoder on TI-OMA
P 5912
 Tightly-coupled kernel scheduler module f
or ARM-Linux on TI-OMAP 5912
Future Plans
 Implementation a flexible multimedia
codec SoC platform
 Design of a new Java Processor for D
VB/MHP
 Design of Hardware-Friendly Psychovi
sual-models for Video Codec
 Clean Design of a Multi-core OS kerne
l suitable for Tightly-Coupled Task Sc
heduling
Architecture and Systems
Research Directions ( 單智君 鍾崇斌 )

 Embedded processor and SoC

 Java processor, JIT compilation &VM
 DSP designs and compilation
 Low-power systems
 Graphic processor
 Superscalar ARM processor
 Reconfigurable computing
Architecture and Systems
R&D Results
 ARM9-compatible processor with
video/audio capabilities
 Java stack operations folding
 Memory Constrained Java Just-in-time
Compiler
 DSP– instruction set extensions
 Low-power Branch-Target-Buffer
 Low-power bus encodings
 Low-power cache memory
 Graphic processor design techniques
 Superscalar ARM
 Reconfigurable computing
ARM9-compatible Processor with
Audio/Video Capabilities
 ARMAVP (ARM Audio Video Processor) 為
32 位元微處理器，採用負載平衡良好的五階管
線設計，分別為 Fetch Unit 、 Decoder Unit
、 Execution Unit 、 Memory access Unit
以及 Write Back Unit 。對各階的設計進行效
能的最佳化，以提高時脈頻率，並提供有效率的
機制，降低了因為記憶體速度太慢對微處理機效
能上的影響
 特性
 支援 Conditional Execution
 ABP 緩衝器設計
 改良指令抓取所需時間
 精確中斷控制結構
 非同步的記憶體存取
 動態暫存器組的映射
 分支指令的快速處理
 多功能有效率的執行路徑
 分散式指令控制編碼
 功能驗證與評估
 所有功能已在 Altera EP20K600EBC652-1 上完
成驗證。根據 Decode Stage 之模擬結果，在 FP
GA 上可工作於 45MHz ，預期實做為晶片時可達
210MHz
DSP– Instruction Set Extensions
 Current research topics
 Multiple-issue architecture
 Exploring ISE in a multiple-issue architecture, s
uch as superscalar or Very Long Instruction Wor
d (VLIW)
 Hardware reusebility
 Reuse same or similar hardware resources in dif
ferent ASFUs while keep same performance
 Overcome register file read/write port constraint
 Try to schedule the input and output of ASFU at
different time slots
Low-power Bus Encodings
 在此我們針對不同的匯流排架構的特性，提出了不同的低電耗匯
流排編碼系統。我們的編碼系統利用了各種編碼方法，將藉由匯
流排傳輸的資料，以最具有電耗效率的方式來傳送，達到省電的
效果。 匯流排編碼架構
傳送端 接收端
編碼過的資料
原始資料 編碼器 解碼器 原始資料
額外控制線路

 低電耗匯流排編碼系統
資料位址匯流排 指令位址匯流排
資料 T0_BI_1,Variable-Stride,SRWEC T0 + Discontinuous Address Table 指令
資料匯流排 處理器 指令匯流排
記憶體 記憶體
Leading-bytes encoding BIBITS with Register Relabling

指令、位址混和之位址匯流排
I/D Selector,T0 DAT+Stride-Table
處理器 指令、位址混和之匯流排 記憶體
I/D Selector,BIBITS_RR+Leading-bytes
Low-power Cache Memory
 快取記憶體佔有整體處理
器超過 50% 之功耗 Power Manager

 低功耗快取記憶體設計
Low-power mode
 Loop Buffer: 將 loop normal Normal mode
code 置入低耗電存取之 accesses

loop buffer 中以節省指 30%

Low-power mode

令擷取之功耗 CPU Normal mode

 Power Manager: 將不 Low-power mode

常使用之快取記憶體區 low-power
accesses
塊置入低耗電模式以節 Loop Buffer
省快取記憶體之靜態功 70%

號。
Graphic Processor
V.S. 3 P.S. 4
研究目的︰
Prog.
2 Prog.
進行新一代繪圖處理器架構研
5
Texture 究，於像素著色器 (Pixel Shad
Vertex Vertex Shader Pixel Depth
Shader Clip
Triangle
Setup Shader Processing
Final
Pixel er) 、材質 (Texture) 及深度
Color
Shader 處理 (Depth Processing) 等三
Vertex
Processing
Pixel 大方向提出硬體架構及軟體驗
Processing 6
1 證環境。
Rendering 目前成果分項說明如下︰

1. A dynamically reconfigurable graphics hardware for resourc

e reallocatable rendering pipeline
2. A Reconfigurable Texture Mapping Architecture
3. Implementation of texture Compression by GPU Driver
4. Register Renaming for Pixel Shaders data/value manageme
nt
5. Instruction scheduling mechanism for 3D GPU pixel shader
6. An Efficient Texture Memory System Designs
7. Alpha Blending without Z Sort
 Superscalar ARM
 Goal: a superscalar embedded processor featuring
 800MHz clock rate @ 0.13um
 1.8DMIPS / MHz – superscalar performance under tough pipeline
latency
 800K gate count – cost-effective design
 Directions and achievements
 Micro-architecture
 A 12-stage dual-issue superscalar processor with good instruction f
etch rate, issue rate, and efficient forwarding
 Simulator
 A cycle-accurate simulator modeling more details than the well-kn
own simplescalar simulator
 Compiler
 Working on GCC machine description to optimize performance
Reconfigurable Computing (1/2)

Motivations:
 Improving the Design
Methodology of Embedded Processor Configuration Reconfigurable
System Hardware (ARM7 / MIPS) Controllor Logic

 Providing a Better Data bus

Performance with Low Main bus

Development Cost
On-Chip Mem /
 Shorting the Time-to- Cache Mem
Data Engine
Market of SoC Products
Memory-mapped
IO Memory Management Unit
Research Issues:
 Hardware/Software External bus

Partition
 Synthesize Technology Off-Chip
 Reconfigurable Processing Memory
Element Design

Reconfigurable Architecture
Research overview in SOC and Emb
edded Systems ( 林盈達 )
 Research theme:
 Content networking with deep packet inspection by softw
are and hardware solutions; with applications in Internet
security (intrusion detection, anti-virus, anti-spam, conte
nt filtering, MSN/P2P management)
 Embedded software
 Embedded Linux solutions: 7-in-1  10-in-1
 A startup company, L7 Networks (L7-Networks.com),
2002, for all-in-one security gateways
 SoC
 Key component in content networking: string matching
 hardware acceleration needed!
 FPGA-based development to accelerate Aho Crosaic an
d Bloom Filtering algorithms
Embedded and SoC Group
Selected R&D Results (2/2)
 7-in-1 integrated security gateway
 String Matching Engine to Accelerate Aho Corasi
c Machine
 Unified Content Filtering Hardware Platform
 String Matching Hardware with Bloom Filters
7-in-1 Integrated Security Gateway

• 7-in-1: VPN, Firewall, NAT, Routing, Content Filtering, Intrusion Detection, Bandwidth Management
• Launched a startup in 2002: L7 Networks Inc.

LAN/DMZ WAN
LAN/DMZ to WAN Outbound Traffic
MAC In-LAN Policy Out-WAN IPsec Bandwidth
Filter
Redirect Route NAT
Filter Route Filter VPN Mgt.
Y Y Y
FTP/POP3/SMTP/
Web/URL Filter with
Many-to-One NAT Alerting Intrusion sniff
System Detection

Y Y
Bandwidth Out-LAN In-WAN IPsec
Filter Route Redirect deNAT deVPN
Mgt. Filter

WAN to DMZ/LAN Inbound Traffic

String Matching Engine to Accel
erate Aho Corasic Machine
 New Parallel Architecture with Pre-Hashing and Root-
Indexing
String Matching
… …
Coprocessor Bit vector
Text
table

Bus
H1 H2
. .
Load
… … . .
Root-Indexing bit
. .
vector
matching
Text Root Pre-Hashing Bit
next . . . .
matching vectors
table . . . .
. . . . .
Current
Processor . Index state Possibly
. Matched?
Root index tables
Next state
of AC
Next state of Root- Load
Compute
Indexing 1 0 state .
next state
Next .
state .
Next state
. address
.

Root next Root index

.
AC State table
table table Next State matching
state table
address
Unified Content Filtering
Hardware Platform
Matched_Interrupt

String Matching Specific DMA

Matched_Pattern_ID
 Resolve content Matched_Text_ID

String Matching Engine

filtering issues
Text_Start_Address Matched_Text_Offset
Text_End_Address Finished_Interrupt
CPU Matched_Address Start
Register Start
 Match without File Status
interrupt CPU
Address1 Address2

Dual Port SRAM

Start

DMA/SM
Data1 Data2

Write Read
 Multiple
connections
management Content Filtering Hardware

 On-fly match non Text

Status Length
First Matched Last Match
Text Pointer FA State
-fixed payload ID Offset Offset
Text First Matched Last Match
Status Length Offset
Text Pointer FA State
ID Offset
.
 Multiple patterns .
and multiple .

matched outputs Text

Status Length
First Match Last Match
Text Pointer FA State
ID Offset Offset

Text Descriptors in DRAM

 String Matching Hardware with
Bloom Filters

shift controller

Leaving Entering
byte byte

Feature Set:
1. Allow maximum shift distance if possible.
2. Reconfigure rules easily.
3. Keep constant hardware complexity.

Bloom filter(1)
Bloom filter(2)
Bloom filter(3)
Platform:
Xilinx ML310 Embedded Development Platfor detect prefix(p,1)
m detect prefix(p,2)
with embedded PowerPC 405 processor detect factor
Xilinx Virtex-II Pro XC2VP30 FPGA in p
MontaVista Linux Professional Edition 3.0
 Embedded and SoC Group
Major Projects
 Excellence Project: Next Generation Information Communication
Networks ( 卓越後續計劃 , 國科會 2004~2008):
 林盈達，曾文貴 (with 24 faculty members)
 Network Benchmarking Lab ( 工研院交大網路測試中心 ,
www.nbl.org.tw, 經濟部工業局 , 2003~2007)
 林盈達
 Attack Session Extraction and Comparison with Nessus (Cisco Sa
n Jose, 2005~2006)
 林盈達
 Content-based Network Security - Content Classification: Design,
Implementation, and Evaluation ( 整合型計劃 , 國科會 , 2004~2006)
 林盈達 (with 李程輝 , 孫雅麗 )
 Open Source Product Testing Tools: In-Lab Live Testing ( 國科會 ,
2005~2006)
 林盈達
 Biography of Ying-Dar Lin 林盈達
 Areas of research interests
 B.S., NTU-CSIE, 1988
 Ph.D., UCLA-CS, 1993
 Professor, NCTU-CS, 1999~
 Founder and Director, ITRI-NCTU Net
work Benchmarking Lab (NBL;
www.nbl.org.tw), 2002~
 Co-Founder, L7 Networks Inc. (
www.L7.com.tw), co-invested by D-Lin
k, ZyXEL, and Advantech, 2002  Publications
 Consultant, CCL/ITRI, 2002~
 Well-cited paper: Multihop Cellular:
A New Architecture for Wireless Com
munications, INFOCOM 2000, YD Lin
and YC Hsu; # of citations: 150
 Design, implementation, analysis, b
enchmarking of Internet gateway d
evices (10-in-1: routing, NAT, fire
wall, VPN, IDP, CF, anti-virus, anti-
spam, IM, P2P, bandwidth manage
ment, link load balance, etc.)
 Internet security and QoS
 Content networking
 Test technologies of switch, router,
WLAN, security, and VoIP
 International journal: 39
 International conference: 33
 IETF Internet Draft: 1
 Industrial articles: 124
 Books: 2
 Patents: 16
 Tech transfers: 8
Wireless Baseband Processor ( 許騰
尹)

 MIMO OFDM PHY

 Ultra Low-power PHY
 Generic PHY architecture
 Chip Implementations
Wireless Baseband Processor
Spreading
Spreading
PAM
PAMMatch
MatchFilter Gate
Filter GateCount
Count:500
:500
Gate
GateCount
Count:4800 Max.
:4800 Max.Freq
Freq::80MHz
80MHz
Max.
Max.Freq
Freq::80MHz
80MHz

g
Spreadin
PAM Match Filter
Clock
ClockGenerator
Generator
Gate
GateCount
Count:2600
:2600
CTRL
CTRL Clock Generator Max.
Max.Freq
Freq::165MHz
Gate
GateCount
Count:1500
:1500 CTRL 165MHz
Max.
Max.Freq
Freq::80MHz
80MHz Clock
Divider
Recovery
Data
DataRate
Rate 4/2/1
4/2/1Mbps
Mbps
PN
PNLength
Length 11
11Chips
Chips
Freq.
Freq.(MHz)
(MHz)44(outer)/132(inner)
44(outer)/132(inner)
Clock
ClockRecovery
Recovery
Gate Max.
Max.IF 22MHz
GateCount
Count:1500
:1500 Digital
DigitalDivider
Divider
IF 22MHz
2
Max. Core
CoreSize 3700X3700um
Max.Freq
Freq::178MHz
178MHz Gate
GateCount
Count:900
:900 Size 3700X3700um2
Max. Freq : 60MHz Power
Power 420mW
420mW@4Mbps
@4Mbps
Max. Freq : 60MHz
Proto-type 802.11b Baseband+MAC chip
Item Specification

Technology 0.25um CMOS 1P5M

D/A A/D (Q)

VLSI Type Cell-Based Design

Function 802.11b Baseband+MAC

System 44MHz

A/D (I)
Frequency

Package 208 QFP

Gate Count Not available

Chip Size Not available

PLL Power supply 2.5V (digital)

3.3V (analog)

Power 650mW
Dissipation
Architecture and Systems
R&D Results

 ARM9-compatible processor with

video/audio capabilities (technology
transferring)
 Java stack operations folding (patents)
 Asynchronous 8051 on FPGA
 Low-power Branch-Target-Buffer (patent
application)
 Low-power bus encodings (patent
applications)
 Graphic processor design techniques
SOC Electrical Design Automation
( 李毅郎 ) – Research Directions

 Reliable Interconnect Design

 Crosstalk-driven Interconnect Design
 Design-for-Manufacture (DFM)
Interconnect Design
 Layout Migration
 VLSI Cell Migration with Topology
Preservation
 Post-Layout Platform for Verification
and Optimization
SOC Electrical Design Automation–
RD Results

 Tile-based Gridless ECO Router with Graph

Reduction
 Two times faster than existing tile-based routers.
 NEMO: A New Full-Chip Gridless Router
 Faster than all academic gridless routers
 Crosstalk-driven Track Assignment
 Pre-Detailed Routing Design Flow Considerin
g Capacitive- and Inductive-Noise Constraint
s
SOC EDA Group RD Results - New
ECO Routing Design Flow
SOC EDA Group RD Results – Full-C
hip Gridless Router
Electronic System Level Design
( 彭文孝 ) http://mapl.nctu.edu.tw

R e q u ire m e n t D e fin itio n R e q u ire m e n t D e fin itio n

Traditional
Design Flow
S p e c ific a tio n
D e ve lo p m e n t S p e c ific a tio n

Design Flow D e ve lo p m e n t

S p e c if ic a t io n
with ESL
M odel
S p e c i f ic a t i o n
M odel
S y s te m A rc h ite c tu re D e s ig n r e g r e s s io n
M o d e l D e ve lo p m e n t

S y s te m A rc h ite c tu re a n d
T L M D e ve lo p m e n t
H ardw are FPGA
R T L D e ve lo p m e n t P ro to ty p e

S y n th e s is S o ftw a re D e ve lo p m e n t
TL M
System Level
SW
D e s ig n
Verification H W and
V e rific atio n
R e f i n e m e n t Integration
S y s t e m I n t e g r a t io n and E n viro n m e n t
H W
a n d V e r if ic a t io n w it h R T L D e ve lo p m e n t D e ve lo p m e n t

System Level
P lac e m e n t an d R o u te
Verification and R TL

C h ip F a b rac tio n
Integration
First Time Silicon Success
 Design Practice: Transaction Level Mo
deling for H.264 Decoder ( 彭文孝 )
64
http://mapl.nctu.edu.tw
64 Bank Bank Bank Bank Bank Bank Bank Bank
0 1 0 1 0 1 0 1

1 B1  (1  n)q1 B1 1 Bank
2
Bank
3
Bank
2
Bank
3
Bank
2
Bank
3
Bank
2
Bank
3 0 0 0 0 0 0 0 0 0 0 0 0

nP1 Bank
0
Bank
1
Bank
0
Bank
1
Bank
0
Bank
1
Bank
0
Bank
1
0
1
0
1
0
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 (1  n) q 2  nP 2 2
1 1 1 1 1 1 1 1 1 1 1 1
2 B2
Bank Bank Bank Bank Bank Bank Bank Bank

B2  (1 -n ) n
2 3 2 3 2 3 2 3 0 0 0 0 0 0 0 0 0 0 0 0

M em o ry Bank
0
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Bus
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2 3 2 3 2 3 2 3 0 0 0 0 0 0 0 0 0 0 0 0

Cache
Bank Bank Bank Bank Bank Bank Bank Bank 0 0 0 0 0 0 0 0 0 0 0 0

 (1  n) qM  nP N
0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1

N BM BN N Bank
2
Bank
3
Bank
2
Bank
3
Bank
2
Bank
3
Bank
2
Bank
3
1 1 1 1 1 1 1 1 1 1 1 1

Arbitration
SDRAM S D R A M 0 S D R A M 1 S D R A M 2 S D R A M 3

Controller H a r d d w a r e In p u t In te r fa c e
M , M
E x te r n a l M e m o r y In te r fa c e
S

Subblock Processing Unit S ync

F IF O

N A L 1 2 8 - b it A H B D a ta B u s
P a r s in g

Video Pipe
IIP
F IF O

Data B it- s tr e a m
F IF O
M B
M o t io n D a ta F e tc h
In tr a / In t e r
P r e d ic t io n
D B
F IF O
D I
F IF O H D M I
In te r fa c e

Transaction
S
B u ffe r S

C A B A C S u b b lo c k
R e c o n s tru c t D e B lo c k in g D e I n t e r la c e r
C A V LC S ,M S ,M
S B u ffe r

M B
T e x tu re IQ /ID C T
B u ffe r S

Control 3 2 - b it A H B C o n tr o l B u s

Bus In s tr u c tio n
M e m o ry
D a ta
M e m o ry
A R M 9
C P U
M Output
CPU Interface
 SoC for Multi-Standard Video Co
dec ( 彭文孝 ) http://mapl.nctu.edu.tw

Video Color
Codec Transform
HD
Embedded
Capturing
SRAM and
Ob-Chip
System on Bus
Chip Networking

ARM-9 Bus
CPU Arbitration

3-A Architecture
Functionalities C Model
VLSI/SOC Research for Graphics Sy
stem ( 范倫達老師 )
VLSI Information Processing LAB
Advisor: Lan-Da Van (
ldvan@cs.nctu.edu.tw)

3-D Graphics Demo Here!

 VLSI/SOC Research for Adaptive Co
mmunications ( 范倫達老師 )
 虛擬系統單晶片平台 (Virtual SOC Platform) 建置 – 使用 CoWare Platform Architec
t
 提供虛擬系統平台供軟體人員程式開發
 提升系統模擬之層級以提高系統驗證效率
 發展效能評估指標 : 根據效能評估指標的模擬結果進而得到系統架構的最佳配置，以供系
統開發時有所依據
 在不同的軟硬體組態，模擬各功能函數所花費的時間

Block diagram of platform
在不同的軟硬體組態，計算模組對 bus 之進行存取次數
Memory
location (size)
AddrBits / DataBits
AHB
R8- MULT
FFT
ROM 0x0
20 / 32 (0x100000)
SW
ARM926
IU CU

32 / 32
stub Instruction 20 / 32 RAM
IP
0x400 0000 DFM
RAM
(0x100000)
Data
32 / 32 Implement
ation
clock FFT HW 0x1000 0000
APB (0x4) FFT/IFFT Chip Design
reset
iTCM dTCM
1/8
din
0xc000 0000
(0x1)
Display
Virtual SOC Verification Platform