Decoders/DeMUXs

CS370 – Spring 2003

 Decoders/Demultiplexers
Decoder: single data input, n control inputs, 2 n outputs

control inputs (called select S) represent Binary index of output to which

the input is connected

data input usually called "enable" (G)

3:8 Decoder:

1:2 Decoder: O0 = G S0  S1  S2

O0 = G  S; O1 = G  S O1 = G S0 S1  S2

2:4 Decoder: O2 = G S0  S1  S2

O0 = G  S0  S1 O3 = G  S0  S1  S2
O1 = G  S0  S1 O4 = G  S0  S1 S2
O2 = G  S0  S1 O5 = G  S0  S1 S2
O3 = G  S0  S1 O6 = G  S0  S1 S2

O7 = G  S0  S1 S2
 Decoders/Demultiplexers
Alternative Implementations

G /G
Output0 Select Output0
Select

Output1 Output1

1:2 Decoder, Active High Enable 1:2 Decoder, Active Low Enable
G /G
Output0 Output0

Output1 Output1

Output2 Output2

Output3 Output3

Select0 Select1 Select0 Select1

2:4 Decoder, Active High Enable 2:4 Decoder, Active Low Enable
Decoder/Demultiplexer
Decoder as a Logic Building Block

0 ABC
1 ABC
2 ABC Decoder Generates Appropriate
Enb Minterm based on Control Signals
3:8 3 ABC
dec 4 ABC If Enb = 0, no outputs are generates.
If Enb = 1, the Decoder is active.
5 ABC
6 ABC
S2 S1 S0 7 ABC

A B C

Example Function:
F1 = A' B C' D + A' B' C D + A B C D
F2 = A B C' D' + A B C
F3 = (A' + B' + C' + D')
Decoder/Demultiplexer
Decoder as a Logic Building Block
0 A B CD
1 A B CD
F1
2 A B CD
3 A B CD
4 A B CD
5 A B CD
Enb 6 A B CD
4:16
7 A B CD
dec
8 A B CD F2
9 A B CD
10 A B CD
11 A B CD
12 AB CD
13 AB CD
14 AB CD
F3
S3 S2 S1 S0 15 AB CD

A B C D
If active low enable, then use NAND gates!
 Multiplexers/Decoders
Alternative Implementations of 32:1 Mux

EN 1 1G 1Y3 7 7 EN 146
I31 7 151 6 5
1391Y2 I31 7 151 154
EN 1 65 A 3 1B 1Y1 5
6 13
2 1A 1Y0 4 7 EN
14 4
I23 7 151 Y5 B I5 145 2 2
6 51 3 W 6 15 2G 2Y3 9 I23 7 I4151 154 3 1 Y 5
EN 1 5 2 2 2Y2 10 6 I3 13 40
7 EN 14 6
I15 7 151 1 4 31Y 5 13 2B 2Y1 11 I5 5 I2 2 2 9 CW
1 6 451 3 4 0 14 2A 2Y0 12 I15 7 151I4 15 4 I1 3 1 5
Y 10B
EN 1 5 2 2 9 W 6 1 GA 6 I3 13 I0 4 0 W 116A
31 3 C 153 7 EN 2
I7 7 15141 4 4 10 Y 15 B 3 A3 I5 145 I2 2 C 9 C
154 I1 31Y 10
S2 F(A, B, C, D, E)
I6 6 53 W 1 6A 4 A2 I7 7 I4151 5 BS1
I5 5 2 2 9 C 01 5 A1 YA 7 F(A, B, C, D, E) I6 6 I3 1 3 I0 40WD 116A
I4 4 3 1 Y 15 6 A0 I5 5 I2 2 2 C 9C S2E S0
I3 13 4 0 1 6AB I4 4 I1 3 1 Y 105B
I2 2 9 CW 01 13 B3 I3 3 I0 4 0 WD 11S1
6A
I1 1 1B 12 B2 I2 2 C 9 S2 E S0
I0 0 1A 11 B1 YB 9 I1 1 10B C
C S2 01 10 B0 I0 0 D 11AS1
D S1 1 GBS1SO C S2E S0
E S0 5 D S1
2 14
A B E S0

Multiplexer Only Multiplexer + Decoder

Multiplexers/Decoders

G1 Y7 \Y 31
5:32 Decoder \EN 1G 1Y 3 G2A Y6
Y5
\Y 30
\Y 29
S4 139 1Y 2 G2B
S3 1B 1Y 1 Y4 \Y 28
1A 1Y 0
138 Y 3 \Y 27
S2 C Y2 \Y 26
2G 2Y 3 S1 Y1 \Y 25
2Y 2 B
S0 Y0 \Y 24
2B 2Y 1 A
\EN \Y31 2A 2Y 0

G1 Y7 \Y 23
G2A Y6 \Y 22
5:32 . G2B Y5 \Y 21

Decoder . Y4
138 Y 3
\Y 20
\Y 19
Subsystem . S2 Y2 \Y 18
S1 C
B Y1 \Y 17
S0 Y0 \Y 16
A
\Y0
S4 S3 S2 S1 S0 G1 Y7
\Y 15
\Y 14
G2A Y 6
\Y 13
G2B Y 5
\Y 12
138 Y 4 \Y 11
Y3
S2 \Y 10
C Y2
S1 B Y1 \Y 9
S0 A Y0 \Y 8

\Y 7
G1 Y 7
\Y 6
G2A Y 6 \Y 5
G2B Y 5
\Y 4
138 Y 4 \Y 3
Y3
S2 \Y 2
C Y2
S1 Y1 \Y 1
B
S0 Y0 \Y 0
A