Chapter 3:

Hardware and Software Subsystems

of Mixed-Signal Architectures
(Part I)

Alex Doboli, Ph.D.

Department of Electrical and Computer Engineering
State University of New York at Stony Brook
Email:adoboli@ece.sunysb.edu

©Alex Doboli
 Overview of the chapter

• Presents main hardware and software components in

an embedded system:
– Sensing, processing, control, data communication,
actuation

– Analog subsystem (programmable CT & SC blocks)

– Digital subsystem (CPU, memory, programmable
digital blocks, customized blocks)
– Interrupt system
– General I/O ports
– System buses
– System clocks

©Alex Doboli
Mixed-signal processing flow

©Alex Doboli
 Mixed-signal processing flow

1. Sensing of analog signals

• Sampled, event-driven
• I/O ports, signal conditioning, filtering, ADC, DAC,
• Drivers, ISRs
• Switched-capacitor, continuous-time

2. Sensing of digital signals

• Circuits (glue logic)
• Standard interfacing protocols (I2C, UART)
• Drivers, ISRs

©Alex Doboli
Mixed-signal processing flow

3. Programming/implementing control algorithms

• CPU, DSP, reconfigurable
• Timers, watchdog circuits (real-time, debugging)
• Customized digital circuits
• Software routines
• OS & middleware routines (conversion, calibration)
• Low power (frequency & voltage scheduling)

4. Generating actuation signals

• Interfacing logic, buffers, ports
• drivers
©Alex Doboli
Overview of the PSoC architecture

©Alex Doboli
Overview of the PSoC architecture

• Main features
– Hardware programmability
• Programmable analog blocks
• Programmable digital blocks
• Programmable interconnect
• Programmable I/Os
• Programmable clocks
• Selectable power supply

– Integration as an SoC

©Alex Doboli
Array of configurable analog blocks

©Alex Doboli
Array of configurable analog blocks

• The configurable (programmable) analog blocks

are used to implement application-specific analog
circuits with customized functionality and
performance

©Alex Doboli
Array of configurable analog blocks

• Analog blocks are programmable

– Programmable functionality (control registers)
– Programmable inputs & outputs
• Analog blocks of two types
– Continuous time blocks
– Switched capacitor blocks (type C and type D)
• Connected to programmable I/O ports
• Programmable interconnect
– Three kind of programmable interconnect
(input, local, output)

©Alex Doboli
Array of configurable digital blocks

©Alex Doboli
Array of configurable digital blocks

• The configurable (programmable) digital blocks

are used to implement application-specific digital
circuits with customized functionality and
performance

©Alex Doboli
Array of configurable digital blocks

• Configurable digital blocks:

• Digital blocks of two types: Type B and type C

©Alex Doboli
Other programmable subsystems

• Programmable General I/O Ports (GIOPs):

– I or O ports
– Connected to CPU, digital resources, programmable analog
blocks
– Driving capabilities
– Can originate interrupt signals

• System buses:
– GIOPs to CPU, programmable analog & digital blocks,
customized blocks
– Maximum data communication rates (parallelism)

• System clocks:
– IMO (moderate & high precision mode)
– Programmable clocks (variable clock frequency)

©Alex Doboli
Embedded software

1. Boot program:
• Initializes general-purpose resources (registers,
memory)
• Configures the application-specific blocks
• Configures system interconnect, system clocks and
supply voltage
• Initializes software runtime environment (data
structures & global variables)
• Calls the main program

2. Embedded control algorithm

– Input sampling (discrete-time systems)
– Event driven (reactive systems)

©Alex Doboli
Embedded software

3. Drivers, API (low-level & high-level middleware)

– Input & output data channels
– Channels are manipulated through high-level methods
(APIs): instantiate a new channel, initialize channel,
modify & retrieve channel parameters, read, write

4. ISR (Interrupt Service Routines)

5. Real-time OS

©Alex Doboli
Embedded software

©Alex Doboli
Embedded software layers

©Alex Doboli
Interrupt system

• Interrupts vs. exceptions & abnormal execution

• Interrupt system includes

– Priority encoder
• Multiple interrupts

– Interrupt table
• Links interrupts & ISRs
• Interrupt vector

– Support for enabling/disabling interrupts

©Alex Doboli
Interrupt system

©Alex Doboli
 Interrupt system

Interrupt name Semantics Priority Interrupt address

Reset/Supply Upon system 0/1 0000H / 0004H
voltage monitor reset/Supply voltage
Analog column 0 By analog column 0 2 0008H
Analog column 1 By analog column 1 3 000CH
Analog column 2 By analog column 2 4 0010H
Analog column 3 By analog column 3 5 0014H
VC3 Variable clock VC3 6 0018H
GPIO GPIO ports 7 001CH
Block DBB00 By digital block 8 0020H
Block DBB01 By digital block 9 0024H
Block DCB02 By digital block 10 0028H
Block DCB03 By digital block 11 002CH
Block DBB10 By digital block 12 0030H
©Alex Doboli
 Interrupt system

Interrupt name Semantics Priority Interrupt address

Block DBB11 By digital block 13 0034H
Block DCB12 By digital block 14 0038H
Block DCB13 By digital block 15 003CH
Block DBB20 By digital block 16 0040H
Block DBB21 By digital block 17 0044H
Block DCB22 By digital block 18 0048H
Block DCB23 By digital block 19 004CH
Block DBB30 By digital block 20 0050H
Block DBB31 By digital block 21 0054H
Block DCB32 By digital block 22 0058H
Block DCB33 By digital block 23 005CH
I2C / Sleep timer I2C / sleep timer 24 / 25 0060H / 0064H

©Alex Doboli
Interrupt system

Related registers:

•INT_MSK3, INT_MSK2, INT_MSK1, INT_MSK0

• INT_CLR3, INT_CLR2, INT_CLR1, INT_CLR0

• INT_VC

©Alex Doboli
 Interrupt system

Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INT_MS ENSW - - - - - - I2C

K3 INT

INT_MS DCB3 DCB32 DBB31 DBB30 DCB23 DCB23 DBB21 DBB20

K2 3

INT_MS DCB1 DCB12 DBB11 DBB10 DCB03 DCB02 DBB01 DBB00

K1 3

INT_MS VC3 Sleep GPIO Analog Analog Analog Analog VMonit

K0 column column column column or
3 2 1 0

©Alex Doboli
 Interrupt system

Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INT_CLR3 - - - - - - - I2C

INT_CLR2 DCB33 DCB32 DBB31 DBB30 DCB23 DCB23 DBB21 DBB20

INT_CLR1 DCB13 DCB12 DBB11 DBB10 DCB03 DCB02 DBB01 DBB00

INT_CLR0 VC3 Sleep GPIO Analog Analog Analog Analog VMonit

column column column column or
3 2 1 0

©Alex Doboli
 Interrupt system

• Steps executed during interrupt handling:

1. Finish the execution of the current instruction
2. Following 13 clock cycles execute the internal
interrupt routine (push on the stack PC & CPU_F, set
CPU_F to zero, set PC[15:8] to zero, load interrupt
vector to PC[7:0])
3. Execution jumps to the ISR
4. ISR is executed
5. RETI instruction is executed at the end of ISR (PC &
CPU_F are restored to their saved values)
6. Interrupted program resumes execution

©Alex Doboli