MSP430 Design Workshop

MSP430 Families

Low Power +
Performance

Ultra Low Security

Power + Comm
 F5xx Key Features
Ultra-Low Power
MSP430F5xx Block Diagram
 160 μA/MIPS
Unified Clock 16-bit
 2.5 μA standby mode System RISC CPU
DMA
Flash
Controller
 Integrated LDO, BOR, WDT+, RTC Enhanced
Power Management Embedded
Module Emulation System
 12 MHz @ 1.8V Control/
Supply Supervisors JTAG Watchdog RAM
 Wake up from standby in <5 μs Supply Monitors Spy Bi-Wire
Interface
Brownout

Increased Performance Computation Timing and Control Signal Chain Communication I/O & Display

 Up to 25 MHz Hardware General Purpose Universal Serial General

Timers Capture/ Communication Purpose I/O,
32x32 Comparators
Compare PWM Interfaces Pull-Up/Down,
 1.8V ISP Flash erase and write Multiplier Outputs (SPI, UART, I2C) High Drive

 Fail-safe, flexible clocking system CRC

Basic Timer
+ ADC
USB 2.0
(Full Speed)
Segmented
LCD, Static,
RTC Engine + PHY Muxed
 User-defined Bootstrap Loader
 Up to 1MB linear memory addressing AEC DAC RF Transceivers

Innovative Features
Operational
 Multi-channel DMA supports data Amplifiers

movement in standby mode

 Industry leading code density
 More design options including USB,
RF, encryption, LCD interface
Looking at the 'FR59xx...
 MSP430 CPU
 Efficient, ultra-low power CPU
 C-compiler friendly
 RISC architecture
 51 instructions
 7 addressing modes
 Constant generator

 Single-cycle register operations

 Bit, byte and word processing
 1MB unified memory map
 No paging
 Extended addressing modes
 Page-free 20-bit reach
 Improved code density
 Faster execution
 100% code compatible with
earlier versions
 Unified Memory Map
In-System Prog (ISP) ‘F5529 Memory Map
 Write using: User
program, JTAG, BSL
Bytes MSP430 Memory
 Unified memory map
 Byte, word, long-word (program or data)
 Erase one (or all)  Absolutely no paging
segments at a time
Flash 128K
Main Flash
 512 byte segments
 Start address moves
according to RAM 0xFFFF RAM
0xFF80 INT Vectors 80  Always a contig. block
Info Memory  If enabled, USB port
 Use for your own uses first 2K
calibration data, etc.  RAM segments can be
 4 segments (A-D) RAM 8K powered down
0x2400
 128 byte segments
0x01C0 USB RAM 2K
Boot Loader (BSL) Info Memory 512 Device Descriptors (TLV)
 Program Flash/RAM Boot Loader 2K  Factory calibration
with serial (slau319) data, periph support,…
 Password protected Peripherals 4K  Found in peripherals
 512 byte segments 0x0000 (at 0x1A00)
 MSP430 GPIO (Chapter 3)
GPIO
CH 3

GPIO (Chapter 3)
 Independently programmable
 Any combination of input, output,
interrupt and peripheral is possible
 Each I/O has an individually
programmable pull-up/pull-down
resistor
 Many devices can lock pin values
‘F5529 block diagram during low-power modes
 Some devices support touch-sense
capability built into the pins
 MSP430 Timers (Chapters 3, 5, 6, 8)
Watchdog GPIO
CH 3 & 5 CH 3

Timers (Chapters 3, 5, 6, 8)
 Timer_A: 16-bit timer/counter
 Multiple capture/compare registers
 Generates PWM and other complex
waveforms & interrupts
 Directly trigger GPIO, DMA, ADC, etc.
 Timer_B: Same as A; improved PWM
 Timer_D: Same as B; with hi-res timing
‘F5529 block diagram  RTC: Real-time clock with calendar &
CH 6 CH 8 alarms – runs in LPM3 low power mode
Timer A & B RTC  Watch: Watchdog or interval functions
MSP430 Clocking & Power Mgmt (Ch 4)
Clocks Power
CH 4 CH 4

Clocking (Chapter 4)
 Three Internal Clocks provide for
CPU, fast and slow peripherals
 Many clock sources (internal and
external) provide cheap and accurate
clks with quick wake-up
 Clock defaults and failsafe’s improve
system robustness

Power Mgmt
 Brown-out reset on all devices
 Many provide LDO’s and power
‘F5529 block diagram supervisors
 On-chip power gating drives ULP
 MSP430 Analog
Clocks Power Watchdog GPIO
CH 4 CH 4 CH 3 & 5 CH 3

Analog
 Families ADC converter options:
10 or 12-bit SAR (ADC10, ADC12)

16 or 24-bit Sigma-Delta (SD16, SD24)

Slope converters

 DAC converters: 12-bit DAC12
 Comparators
 Voltage REFerences
 Features in common:
 Analog mux supporting multiple input chan’s
 DMA can read/write samples without CPU
‘F5529 block diagram
 Precise timing when using timer to trigger
CH 6
 Generate interrupts to CPU
Timers
 Low power dissipation
 MSP430 Communication
Clocks Power Watchdog GPIO USB
CH 4 CH 4 CH 3 & 5 CH 3 CH 10

Communications
 USB (Chapter 10)
 USB 2.0 at Full speed (12Mbps)
 Includes PHY, LDO, PLL, PUR
 Serial ports
 USI: SPI, I2C
 USCI: SPI, I2C, IrDA, UART
 eUSCI: enhanced USCI
 Radio Frequency
 CC430 and RF430 devices include
‘F5529 block diagram
Sub-1GHz or NFC radios CH 6
 WiFi, BLE, ANT, BluetoothTimers
& Sub1GHz
communications via TI SimpleLink
 MSP430 Accelerators
Clocks Power Watchdog GPIO USB
CH 4 CH 4 Accelerators
CH 3 & 5 CH 3 CH 10

 DMA (“hardware memcpy”)

 Copy from memory to memory
 Faster copies than with CPU
 Supports periph’s (ADC, UART)
 MPY32 (8/16/32 Multiplier)
 MAC, fractional, saturation support
 CRC: Single-cycle CRC generation
 AES: 128, 192, 256 bit encryption
 LCD: Automatic with up-to 160-bit

‘F5529 block diagram

MSP430 Peripherals (and In-Depth Chapters)
Clocks Power Watchdog GPIO USB
CH 4 CH 4 CH 3 & 5 CH 3 CH 10

‘F5529 block diagram

CH 6 CH 8
Timer A & B RTC
 Ultra-low Power Activity Profile
Active Active
170 A

Standby (LPM3)
0.4 A

32768 MSP430 Leave On the Slow Clock

ACLK  Low power clock and peripherals
low-power peripherals interrupt CPU only for processing
On-Demand CPU Clock
MCLK
DCO  DCO starts immediately
CPU and peripherals
 CPU processes data and quickly
returns to Low Power Mode
 Low-Power Modes

Self Wakeup
CPU (MCLK)

Retention
SMCLK
Operating

ACLK

RAM

BOR
Mode Interrupt Sources

Active     
LPM0     
Timers, ADC, DMA, WDT, I/0,
LPM1      External Interrupt, COMP,
Serial, RTC, other
LPM2    
LPM3    
LPM3.5   External Interrupt, RTC
LPM4   External Interrupt
LPM4.5  External Interrupt

LPM is great, but waking up...

Further Reading…
MSP430 Microcontroller Basics by John H. Davies,
(ISBN-10 0750682760) Link

Microcontroller Programming and Interfacing:

Texas Instruments MSP430 (Synthesis Lectures on
Digital Circuits and Systems)
by Steven Barrett and Daniel Pack ,
(ISBN-10 0750682760) Link
MSP-EXP430F5529LP Launchpad
MSP-EXP430F5529LP Overview
 Lab 1 – Run Out-of-Box Demo

 Verify tool installation

 Review Launchpad kit
contents
 Connect hardware
 Try out preloaded software
using Quick Start Guide

Agenda …