DESIGN AND IMPLEMENTATION OF FPGA

BASED CYCLIC CODE ENCODER/DECODER

Presented by:-
Prashant Pathak(P18VL009)
Gyaneshwar P. Rathore(P18VL013)
 Definition
An (n,k) linear code C is cyclic if every cyclic shift
of a codeword in C is also a codeword in C.
A (n,k) cyclic code can be generated by a
polynomial g(x) which has
– degree n-k and
– is a factor of xn - 1.

 Call it the generator polynomial.

 Cyclic Code
Encoding Procedure:
Let u(x) is message polynomial and g(x) is generator
polynomial
1. Multiply u(X) by Xn-k
2. Divide Xn-k u(X) by g(X), obtaining the remainder b(X).
3. Add b(X) to Xn-k u(X), obtaining c(X) in systematic form.

Where,
b(X) = Rem[Xn-k u(X)/g(X)]
Decoding procedure

 Received word: r(X) = r0 + r1X +….+ rn-1Xn-1

 If r(X) is a correct codeword, it is divisible by g(X). Otherwise:
 r(X) = q(X)g(X) + s(X).
 s(X) = Rem[r(X)/g(X)]
 s(X) is called the syndrome polynomial.
 Relevance

Cyclic codes are error-correcting codes that have algebraic properties

that are convenient for efficient error detection and correction

Cyclic code is mainly used in data communication, data storage,

magnetic and optical storage(CD)
Block Diagram
Feasibility on Basys 3

Basys 3 has 16 switches and 16 LEDs

which can be utilized for this project.
 Test Plan

The input port can be mapped to available switches on the

board.

On and off state of switch will represent logic 1 and logic 0
respectively.

The output port can be mapped to LEDs

Encoder circuit
Syndrome calculator
Information Coding scheme of code rate Information
rate(Rb) k/n rate=RB * k/n
 APPLICATION

IEEE802.11a (WLAN) operates in the 5 GHz band with a maximum net data rate
of 54 Mbit/s, plus error correction code, which yields realistic net achievable
throughput in the mid-20 Mbit/s.

Error control codes can be used in physical layer of protocol for

secure communication
THANK YOU