DEPARTMENT OF TECHNICAL EDUCATION

ANDHRA PRADESH
Name : CH. Rajendra Prasad
Designation : Senior Lecturer in ECE
Branch : Electronics & communication Engg.
Institute : QQ. Govt . Polytechnic, Hyderabad
Year/Semester : IV Semester
Subject : Microprocessors
Subject Code : CM 405
Topic : Introduction and Architecture
Duration : 100Mts
Sub Topic : Bus Cycle And Timing Diagram
Revised by :K.Srikanth,Lecturer,GPT, Nizamabad

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Objectives

On completion of this topic you would be able to

understand

• Bus cycles and timing diagram of 8086 microprocessor

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 Recap

In the previous class, you have studied about

• Pin diagram of 8086

• Functions of various pins

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Bus cycles

• The bus cycle of 8086 contains 4T-states (T1, T2,T3,T4)

• If the clock frequency is 5MHz.Each T-state = 1/5MHz

= 0.2ms

• Each bus cycle requires 0.8ms

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Bus cycles (contd.)

• If a device connected to the 8086 is slow, then wait

state(s) (Tw) are introduced between T3and T4

• Status of T3 will be maintained in Tw’s

• When the data is ready T4 is completed

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Timing diagram

• It includes the following signals and their state with

respect to the bus cycle

• ALE, M/IO, A19, A0, D15-D0, RD, WR, DT/R

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Timing Diagram For Read Operation

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Timing Diagram for Write Operation

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Summary
In this lesson we have discussed about:

• Bus cycles and timing diagram

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Frequently Asked Question

1. Explain how even and odd bank addressing is used in

8086

2. Draw the timing diagram of memory read bus cycle

3. Draw the timing diagram of memory write bus cycle

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