2 VLSI Design | Very Large Scale Integration | Integrated Circuit

VLSI Design

VLSI Design

Integrated Circuits

First transistor

First IC

Number of applications needs Integrated circuits such as : ‡ High performance computing. ‡ Telecommunications. ‡ Consumer Electronics.

to handle real-time video).Why do we need Integration? For information services there are important characteristics that must be achieved ‡ Increasing need for very high processing power and bandwidth (i. ‡ Need for more personalized (which means devices be more intelligent to answer individual demands & must be portable to allow more flexibility/mobility) .e.

.Why do we need Integration? (Cont. ‡ SO.the need to integrate these functions in a small system/package is also increasing.) ‡ To achieve the previous characteristics more & more complex functions are required.

000.000 gate) 1964 1967 1972 1978 1989 .000-10.000 gate) ‡ ULSI (500. ‡ SSI (2-20 gate) ‡ MSI (20-200 gate) ‡ LSI (200-2000 gate) ‡ VLSI (2000-500.Levels of integration Level of integration is measured by the No. of logic gates in a chip.

Integration Provides ‡ Less area/volume ‡ Less power consumption ‡ Higher speed ‡ Significant cost saving ‡ Less testing requirements as system level ‡ Higher reliability (due to improved interconnections) .

3µm expected around year 2000. . But the actual development was minimum length of 0. Number of components per chip increase year by year. Minimum feature size( transistor length or interconnect length) decrease year by year.25µm was reached by year 1994.Trend of integration In early 1980s minimum feature size of 0.

of transistors double every 3 years ( recently 2. cost per function has dropped exponentially . ‡ Intel¶s Gordon Moore in early 80¶s predicted that this trend would continue ‡ Cost of printing process has grown modestly Thus.3 years) ‡ Feature size has shrunk by 0. ‡ No.Moore¶s Law The number of transistors that can be integrated on a single IC grows exponentially with time.7 times every 3 years.

) ‡ At each new generations.Moore¶s Law (Cont. ‡ Cost of manufacturing ICs have remained flat but design cost has not . each gate cost about 1/ 2 what it did 3 years a go.


Schottky ‡ ECL ‡ Dual Junction.PMOS ‡ CMOS ‡ Single Junction voltage controlled devices ‡ GaAs (typically JFET¶s) . current controlled devices ‡ NMOS.Technologies ‡ Bipolar (BJT) ‡ TTL.

Why CMOS Technology ? ‡ Simple (low cost) ‡ Small area and low power(High Density) ‡ Wafer size: 8 inch ‡ chip size: 1.5 X 1.5 cm² .

What Are On ICs? ‡ Conducting layers which form wires ‡ Many layers of wires (4-5 metal layers) which has electrical properties such as resistance and capacitance ‡ Contacts and insulators between layers ‡ Transistors (³free´ things that fit under the wires) .

‡ logic design. ‡ architecture. .VLSI Design Major steps ‡ specification. ‡ circuit design. ‡ layout (physical design).).

system specification Behavioral Representation Functional (architecture) Design Functional verification Logic (gate-Level) Representation Circuit Representation Layout Representation Logic Design Logic Verification gates+ registers Circuit Design Circuit Verification Transistors Physical Design Layout Verification Device .

‡ Some Classical techniques of reducing the complexity are: ‡ Hierarchy ‡ Regularity ‡ Modularity ‡ Locality .Design complexity ‡ Regardless of the size of the project. reducing the complexity of IC improve the prospects of success.

In the physical domain when getting the functional blocks.1. . this will provide a valuable guidance of the actual realization on chip (approximate size & shape). Design Hierarchy It¶s dividing a module into sub-modules and then repeating this operation on the sub-modules until the complexity of smaller parts becomes manageable.

add4 add add add add carry sum carry sum carry sum carry sum and or and or and or and or .

Regularity ‡ Means that the hierarchical decomposition is not only simple but also similar blocks.2. ‡ Extended use of regularity simplifies the design process ‡ Regularity can exist at all levels of design hierarchy Transistor level : uniform sized transistors simplifies the design Logic Level:identical gate structures can be used .

3. Modularity Various blocks which make up larger system must have well-defined functions and interfaces. Each block or module can be designed relatively independent since there¶s no ambiguity about the function and interface of these blocks All of the blocks can be combined at the end of the design process to form a larger system. .

. Time locality:modules see a common clock and synchronous timing is applied.4. To avoid excessive interconnect delays long-distance connections must be avoided as much as possible. locality The concept ensures that the connections are mostly between neighboring modules.

VLSI Design Styles ‡ Full Custom Mask Design ‡ Standard Cell Design ‡ Gate Arrays ‡Programmable Logic Design Investment Increasing (for a given application) .

‡ Design time can be very long and so fabrication time (at least 6-8 weeks).1. . ‡ Smallest die area (high transistors density) ‡ Very high development cost. Full custom design ‡ Designers hand draws geometries which specify transistors and other devices for an integrated circuit (transistor/circuit level).

Mask layout of Pentium II micro-processor .‡ The first custom chip cost is very high but each one after is much cheaper so high volume products is designed (memory chips.micro-processors). ‡ Memory chips are the most popular designs done with full custom designs.

characterized and stored in standard cell library. xor.2. nor. Standard Cell Design Almost like the full custom design but commonly used logic cells are developed . latches. ‡ MSI logic: decoders. buffers. Standardization is achieved at the logic or function level (transistor). ROM . encoders. comparators ‡ Memories: RAM. inverters. adders. registers. Example on standard cell contents : ‡ SSI logic: nand.

To enable automated placement and routing of inter-cell connections . Standard cell Standard cell row . each cell layout has fixed height so cells can be abutted side-by-side.

3. Gate arrays The design is mapped onto an array of transistors which is already created on a wafer GA implementation require two-step manufacturing : ‡ Array of uncommitted transistors on the GA chip (manufacture) ‡ Defining the metal interconnects between the transistors of array(user) .

Uncommitted cell Committed cell 4-input (NOR) .

‡ Depending on the particular device. the program is: .'burned¶ as part of a board assembly process . FPGA What does 'Field Programmable' mean? ‡ A typical integrated circuit (IC) performs a particular function defined at the time of manufacture. ‡ A program written by someone other than the device manufacturer defines the FPGA¶s function.loaded from an external memory each time the device is powered up .4.

Four main categories of FPGA currently available : Logic block interconnections Symmetric array Row-based Logic block interconnections Sea-of-gates Hierarchical PLD .

transmission gates or multiplexers controlled by SRAM cells (determine logic functions & interconnections).Currently there are four technologies in use : ‡ Static RAM cells Connection are made using transistors. .or can be programmed into low-impedance (fused) ‡ EPROM/EEPROM transistors Same method as EPROM memories. ‡ Anti-Fuse Resides in high-impedance state.

The FPGA has 3 configurable elements : ‡ Configurable Logic Block (CLB) ‡ Input/Output Block (IOB) ‡ Interconnections .

CLB ‡ Provides the functional elements for constructing user¶s logic. ‡ May be physically implemented using LUT. IOB ‡ Provides the interface between the package pins and internal signal lines.multiplexers and gates. .

‡ Composed of metal segments with programmable switching points to implement the desired routing .Programmable interconnections ‡ Provide routing paths to connect the inputs and outputs of CLB and IOB.

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