VLSI Design

Integrated Circuits

First IC
First transistor

Number of applications needs Integrated

circuits such as :
• High performance computing.
• Telecommunications.
• Consumer Electronics.
Why do we need Integration?

For information services there are important

characteristics that must be achieved

• Increasing need for very high processing power

and bandwidth (i.e. to handle real-time video).

• Need for more personalized (which means

devices be more intelligent to answer individual
demands & must be portable to allow more
flexibility/mobility)
Why do we need Integration? (Cont.)

• To achieve the previous characteristics more &

more complex functions are required.

• SO,the need to integrate these functions in a

small system/package is also increasing.
Levels of integration

Level of integration is measured by the No. of

logic gates in a chip.

• SSI (2-20 gate) 1964

• MSI (20-200 gate) 1967

• LSI (200-2000 gate) 1972

• VLSI (2000-500,000 gate) 1978
• ULSI (500,000-10,000,000 gate) 1989
Integration Provides

• Less area/volume
• Less power consumption

• Higher speed

• Significant cost saving

• Less testing requirements as system level

• Higher reliability (due to improved interconnections)

Trend of integration

In early 1980s minimum feature size of 0.3µm expected

around year 2000.

But the actual development was minimum length of

0.25µm was reached by year 1994.

Number of components per chip increase year by year.

Minimum feature size( transistor length or interconnect

length) decrease year by year.
 Moore’s Law
The number of transistors that can be integrated on a
single IC grows exponentially with time.
• No. of transistors double every 3 years
( recently 2.3 years)
• Feature size has shrunk by 0.7 times every 3 years.

• Intel’s Gordon Moore in early 80’s predicted that

this trend would continue
• Cost of printing process has grown modestly
Thus, cost per function has dropped exponentially
 Moore’s Law (Cont.)
• At each new generations, each gate cost about 1/ 2
what it did 3 years a go.

• Cost of manufacturing ICs have remained flat but

design cost has not
 Why CMOS Technology ?

• Simple (low cost)

• Small area and low power(High Density)

• Wafer size: 8 inch

• chip size: 1.5 X 1.5 cm²
What Are On ICs?
• Conducting layers which form wires
• Many layers of wires (4-5 metal layers) which has
electrical properties such as resistance and
capacitance
• Contacts and insulators between layers

• Transistors (“free” things that fit under

the wires)
 VLSI Design

Major steps

• specification;
• architecture;
• logic design;
• circuit design;
• layout (physical design).).
 system specification

Functional
Behavioral (architecture) Design

Representation
Functional verification

Logic Logic Design

(gate-Level)
Representation
Logic Verification gates+ registers

Circuit Design
Circuit
Representation Circuit Verification

Transistors
Layout Physical Design

Representation Layout Verification

Device
 Design complexity
• Regardless of the size of the project, reducing the
complexity of IC improve the prospects of success.

• Some Classical techniques of reducing the complexity

are:
• Hierarchy

• Regularity
• Modularity
• Locality
 1. Design Hierarchy

It’s dividing a module into sub-modules and then

repeating this operation on the sub-modules until the
complexity of smaller parts becomes manageable.

In the physical domain when getting the functional

blocks, this will provide a valuable guidance of the
actual realization on chip (approximate size & shape).
 add4

add add add add

carry sum carry sum carry sum carry sum

and or and or and or and or

 2. Regularity
• Means that the hierarchical decomposition is not only
simple but also similar blocks.

• Extended use of regularity simplifies the design process

• Regularity can exist at all levels of design hierarchy

Transistor level : uniform sized transistors simplifies the design

Logic Level:identical gate structures can be used

 3. Modularity
Various blocks which make up larger system must have
well-defined functions and interfaces.

Each block or module can be designed relatively

independent since there’s no ambiguity about the
function and interface of these blocks

All of the blocks can be combined at the end of the

design process to form a larger system.
 4. locality
The concept ensures that the connections are mostly
between neighboring modules.

To avoid excessive interconnect delays long-distance

connections must be avoided as much as possible.

Time locality:modules see a common clock and

synchronous timing is applied.
 VLSI Design Styles

• Full Custom Mask Design

Design
• Standard Cell Design Investment
Increasing (for
a given
• Gate Arrays
application)

•Programmable Logic
 1. Full custom design
• Designers hand draws geometries which specify
transistors and other devices for an integrated
circuit (transistor/circuit level).

• Smallest die area (high transistors density)

• Very high development cost.

• Design time can be very long and so fabrication time

(at least 6-8 weeks).
• The first custom chip cost is very high but each one
after is much cheaper so high volume products is
designed (memory chips,micro-processors).

• Memory chips are the most popular designs done with

full custom designs.

Mask layout of Pentium II

micro-processor
 2. Standard Cell Design
Almost like the full custom design but commonly used
logic cells are developed ,characterized and stored in
standard cell library.

Standardization is achieved at the logic or function level

(transistor).

Example on standard cell contents :

• SSI logic: nand, nor, xor, inverters, buffers, latches, registers.
• MSI logic: decoders, encoders, adders, comparators
• Memories: RAM, ROM
To enable automated placement and routing of inter-cell
connections , each cell layout has fixed height so cells
can be abutted side-by-side.

Standard cell

Standard cell row

 3. Gate arrays
The design is mapped onto an array of transistors
which is already created on a wafer

GA implementation require two-step manufacturing :

• Array of uncommitted transistors on the GA chip
(manufacture)

• Defining the metal interconnects between the

transistors of array(user)
Uncommitted Committed cell
cell 4-input (NOR)
 4. FPGA
What does 'Field Programmable' mean?

• A typical integrated circuit (IC) performs a particular

function defined at the time of manufacture.

• A program written by someone other than the device

manufacturer defines the FPGA’s function.

• Depending on the particular device, the program is:

- 'burned’ as part of a board assembly process

- loaded from an external memory each time the

device is powered up
Four main categories of FPGA currently available :

Logic
block

interconnections

Symmetric array Row-based

Logic
block

interconnections

Sea-of-gates Hierarchical PLD

Currently there are four technologies in use :

• Static RAM cells

Connection are made using transistors,transmission gates or multiplexers controlled
by SRAM cells (determine logic functions & interconnections).

• Anti-Fuse
Resides in high-impedance state,or can be programmed into low-impedance (fused)

• EPROM/EEPROM transistors
Same method as EPROM memories.
The FPGA has 3 configurable elements :

• Configurable Logic Block (CLB)

• Input/Output Block (IOB)
• Interconnections
 CLB
• Provides the functional elements for constructing user’s logic.

• May be physically implemented using LUT,multiplexers and

gates.

IOB
• Provides the interface between the package pins and internal
signal lines.
 Programmable interconnections
• Provide routing paths to connect the inputs and outputs of CLB
and IOB.

• Composed of metal segments with programmable switching

points to implement the desired routing