A Bulk-Driven Self-Biased Rail-to-Rail

Input Range Operational

Transconductance Amplifier (OTA) with
High-Speed Block (HSB) Implemented
in 65 nm CMOS Process

AN UNDERGRADUATE THESIS

by

Garyl Jay N. Pepito

SYSTEM BLOCK DIAGRAM

Figure 1 System block diagram architecture of the proposed OTA design

PMOS BULK-DRIVEN PSEUDO
DIFFERENTIAL PAIR

Figure 2 Schematic of the PMOS Bulk-Driven Pseudo Differential

Pair
COMMON SOURCE WITH A CURRENT
MIRROR LOAD

Figure 3 Schematic of the common source with a current mirror

load
HIGH SPEED BLOCK

Figure 4 Schematic of the high speed block

THE PROPOSED CIRCUIT

Figure 5 Schematic of the proposed OTA

RESULTS
 Pre-Simulation Results

Figure 6 Pre-Simulation Results for Gain

Figure 7 Pre-Simulation Results for the Unity Gain
Bandwidth
Table 1 Pre-Simulation Results

Parameter Value

Gain 65.1 dB

Bandwidth 33.2 MHz

 Post-Simulation Results

Figure 8 Post-Simulation Results for Gain

Figure 9 Post-Simulation Results for the Unity Gain
Bandwidth
 Table 2 Post-Simulation Results

Parameter Value

Gain 64.3 dB

Bandwidth 30.8 MHz

 Pre-Simulation Versus Post-Simulation
Results

Figure 10 Overlaid Pre- and Post-Simulation Waveforms

Table 3 Comparison of Pre- and Post-Simulation Results

Parameter Pre-Sim Post-Sim Difference

Gain 65.1 dB 64.3 dB 0.8 dB

Bandwidth 33.2 MHz 30.8 MHz 2.4 MHz

 Process Corner Variations

Figure 11 TT Waveform
 Table 4 TT Corner Simulation Results

Parameter Value

Gain 64.3 dB

Bandwidth 30.8 MHz

 OTA Layout

Figure 12 Floor Plan

Figure 13 OTA Layout
 Work Comparison

Table 5 Comparison with Previous Works

CONCLUSION

 This study has designed a Bulk-Driven Operational

Transconductance Amplifier that offers a bandwidth
of up to 30.8 MHz which is desirable for use in high
frequency applications. The designed OTA uses
bandwidth enhancement techniques in order to
achieve a bandwidth that is appropriate for use in
high frequency applications.
CONCLUSION

 The design is implemented in 65 nm CMOS

technology using Custom Designer for Synopsys.
The use of CMOS technology in designing an
OTA minimizes the cost of OTA as compared to
any other CMOS technology sizes.
CONCLUSION

 Aside from cost advantages, CMOS processes

also offers lower power advantages as compared
to power consumption of OTAs implemented in
other technology sizes.