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RISC-V I Class Processor Design

This document describes the SHAKTI processor series developed at RISE Lab, IIT Madras. It includes C class microcontrollers, I class processors, and other classes up to H class. The document focuses on the features of the I class processor, including its RISC-V ISA, out-of-order dual issue pipeline, CAM-based load store unit, and bypass network. It also describes the fault tolerant variant of the C class microcontroller which can tolerate single bit errors and one ALU failure using techniques like Hamming codes and dual modular redundancy in the ALU design.

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124 views15 pages

RISC-V I Class Processor Design

This document describes the SHAKTI processor series developed at RISE Lab, IIT Madras. It includes C class microcontrollers, I class processors, and other classes up to H class. The document focuses on the features of the I class processor, including its RISC-V ISA, out-of-order dual issue pipeline, CAM-based load store unit, and bypass network. It also describes the fault tolerant variant of the C class microcontroller which can tolerate single bit errors and one ALU failure using techniques like Hamming codes and dual modular redundancy in the ALU design.

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anon_112674435
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SHAKTI PROCESSORS

RAHUL BODDUNA
RISE LAB, IIT MADRAS

rahul.bodduna@gmail.com
SHAKTI SERIES
• C Class microcontrollers
– Fault Tolerant Variant
• I Class processors
• M Class processors
• S Class processors
• H Class processors
I Class Processor -Features
• Based on RISC-V ISA
• Dual Fetch out-of-order issue using merged register file
approach.
• Parameterized pipeline and Issue Queue.
• CAM based speculative load store unit.
• Inter-functional unit bypass network.
• Tournament Branch Predictor.
Design
Pipeline Stages

1. FETCH
2. DECODE
3. MAP
4. SELECT AND GRANT
5. DATA READ AND DRIVE
6. EXECUTE
7. COMMIT
Instruction Issue and Bypass Network
• Instruction Issue:
– Age based Issue
– Position Based Issue
• Bypass Network
CAM based Load Store Unit
• Each memory access
instruction is allotted an entry
in one of LS queues.

• The value from the store is


forwarded in case of address
match.

• Alias bit is set in case of


wrong speculation and
pipeline is flushed at the time
of commit.
Verification Environment
• Automatic Assembly
Program Generator(AAPG) AAPG
generates random
assembly instruction –
written in python.
• Instruction Set
Simulator(ISS) – functional Instructions ISS Initialiased
memory
equivalent of processor in
C.
• Register dump after every
instruction is matched Match
no
against each other for ?

verification. modify

I-Cache Processor D-Cache


IPC for AAPG Test Cases
• IPC variation based on issue queue size.
Using Bypass network….
Frequency recorded

65 nm UMCIP Standard cell library with operating


conditions 1.32 V supply voltage and 110 0F is used.
Dhrystone Results
Fault Tolerant Variant of C Class
• 32-bit 5 stage pipeline with branch prediction.
• Supports all integer instructions.

• Resilient against hard and soft errors.


• Tolerate single bit error from fetch stage to writeback stage.
• Tolerate one ALU failure in the execution unit.
Single Bit Error Mitigation.
• Hamming Codes are used for Single Error Correction(SEC) and
Double Error Detection(DEC) techniques to mitigate errors in
Memories and Registers.
• SEC-DED logic is placed in the design after inter stage buffer (ISB)
and before the combinational logic.
Fault Tolerance in ALU Design.
• All types of functions in ALU are in dual modular redundant
(DMR) configuration with fault handling logic.
 Adder Functional Unit:
Function Instructions handled of RISC-V ISA
ft_add_sub LUI, AUIPC, ADD, ADDI, SUB Addition/Substraction related
ft_adder Load & store, Jump, Branch Effective Address Calculation

 Normal Computation : 𝐹𝑛 = OP1 ± OP2.


 Re-computation : 𝐹𝑟 = (~OP1+1) ± ~OP2.
As 𝐹𝑛 & 𝐹𝑟 are complementary, stuck at failure at any bit position
will be known.
 Multiplier Functional Unit:
Function Instructions Handled of RISC-V ISA Remarks
ft_multiplier MUL, MULH, MULHSU, MULHU Multiplication Instructions

 Normal Computation : 𝐹𝑛 = OP1*OP2


 Recomputation : 𝐹𝑟 = (2’s complement of OP1)*(OP2)
Fault handling logic will check if the result of normal
computation matches with 2’s complement of result of
recomputation.

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