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Shakti Processors: Rahul Bodduna Rise Lab, Iit Madras
Shakti Processors: Rahul Bodduna Rise Lab, Iit Madras
RAHUL BODDUNA
RISE LAB, IIT MADRAS
rahul.bodduna@gmail.com
SHAKTI SERIES
• C Class microcontrollers
– Fault Tolerant Variant
• I Class processors
• M Class processors
• S Class processors
• H Class processors
I Class Processor -Features
• Based on RISC-V ISA
• Dual Fetch out-of-order issue using merged register file
approach.
• Parameterized pipeline and Issue Queue.
• CAM based speculative load store unit.
• Inter-functional unit bypass network.
• Tournament Branch Predictor.
Design
Pipeline Stages
1. FETCH
2. DECODE
3. MAP
4. SELECT AND GRANT
5. DATA READ AND DRIVE
6. EXECUTE
7. COMMIT
Instruction Issue and Bypass Network
• Instruction Issue:
– Age based Issue
– Position Based Issue
• Bypass Network
CAM based Load Store Unit
• Each memory access
instruction is allotted an entry
in one of LS queues.
verification. modify