Instructions: Language of

the Computer
CHAPTER 2
Course Instructor: Engr. Afshan Jamil

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 Software
Compiler Assembler

Application software, MIPS compiler output, MIPS binary machine code:

a program in C: assembly language program:
00000000101000010000000000011000
00000000000110000001100000100001
swap (int v[ ], int k) swap; 10001100011000100000000000000000
{int temp; muli $2, $5, 4 10001100111100100000000000000100
10101100111100100000000000000000
temp = v[k]; add $2, $4, $2 10101100011000100000000000000100
v[k] = v[k+1]; lw $15, 0 ($2) 00000011111000000000000000001000
v[k+1] = temp; lw $16, 4 ($2)
} sw $16, 0 ($2)
sw $15, 4 ($2)
jr $31

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 Computer Architecture
• Architecture: System attributes that have a
direct impact on the logical execution of a
program
• Architecture is visible to a programmer:
– Instruction set
– Data representation
– I/O mechanisms
– Memory addressing

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 Computer Organization
• Organization: Physical details that are
transparent to a programmer, such as
– Hardware implementation of an instruction
– Control signals
– Memory technology used

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 Instruction
• It is a bit stream of zeros and ones having
multiple fields and can be understood by a
computer
– Opcode: operation to be performed
– Address Fields: Memory or Register Address
– Mode: specifies the way the address field is to be
interpreted.
– Special Fields
• field that gives the number of positions to shift in a
shift-type instruction
• An operand field in an immediate operand instruction

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 Register Set
• Register set consists of all registers in the CPU
that are accessible to the programmer
– General Purpose registers
– Processor status register (PSR)
– Stack pointer (SP)

• Instruction register, registers in the register

file that are accessible only to hardware
controls and/or micro-programs, and pipeline
registers are not part of the register set

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 Instruction Set Architecture (ISA)
• ISA= All of the programmer visible components and operations
of the computer.
• Memory organization
– Address space: how many locations can be addressed?
– Addressability: how many bits per location?
• Register Set
– How many? What size? How are they used?
• Instruction set
– Opcodes (Operation codes)
– Data types
– Addressing modes

• ISA provides all information needed for someone that wants

to write a program in machine language or translate from a
high level language to machine language.
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 ISA
• Instruction set architecture is concerned with
– Organization of programmable storage: Includes amount
of addressable memory and number of available registers.
– Data types & Data structures.
– Instruction set: what operations are supported.
– Instruction formats.
– Data transfer modes between registers, memory and I/O.
– Exceptional conditions.
• Types of ISA: RISC, CISC, VLIW, Superscalar

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 Operand Address
• Implied Address
– Address is specified either by the Opcode of the
instruction or by an address assigned to one of the
other operands.
– No need for a memory or register address field for
the operand in the instruction

• Explicit Address
– Operand has an address in the instruction

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 ISA Design Issues
• Where are operands stored?
– registers, memory, stack, accumulator
• How many explicit operands are there?
– 0, 1, 2, or 3
• How is the operand location specified?
– register, immediate, indirect, . . .
• What type & size of operands are supported?
– byte, int, float, double, string, vector. . .
• What operations are supported?
– add, sub, mul, move, compare . . .

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 Classifying ISA
• In a stack architecture, operands are implicitly taken
from the stack.
– A stack cannot be accessed randomly.
• In an accumulator architecture, one operand of a binary
operation is implicitly in the accumulator.
– One operand is in memory, creating lots of bus traffic.
• In a general purpose register (GPR) architecture,
registers can be used instead of memory.
– Faster than accumulator architecture.
– Efficient implementation for compilers.
– Results in longer instructions.

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 CONTD…
• Most systems today are GPR systems.
• There are three types:
– Memory-memory where two or three operands may be in
memory.
– Register-memory where at least one operand must be in a
register.
– Load-store/Register-register where no operands may be
in memory.
• The number of operands and the number of available
registers has a direct effect on instruction length.

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 Instruction Formats
• Basic components in each architecture:
GPR register-
Stack Accumulator GPR load/store
memory
architecture architecture architecture
architecture
Main Main Main Main
Memory Memory Memory Memory

Stack
reg reg
AC
reg reg
reg reg

ALU ALU
ALU ALU

Stack: AC: Multiple registers: Multiple registers:

An abstract entity, may Physically located in Physically located in Physically located in
be in memory or CPU CPU CPU
registers (if big enough)

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 Instruction Formats
Q: Show the source and destination operands in each architecture:
GPR register-
Stack Accumulator GPR load/store
memory
architecture architecture architecture
architecture
Main Main Main Main
Memory Memory Memory Memory

Stack
reg reg
AC
reg reg
reg reg

ALU ALU
ALU ALU

Source operand(s): Source operand(s): Source operand(s): Source operand(s):

Destination operand: Destination operand: Destination operand: Destination operand:

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 Instruction Formats
A: Show the source and destination operands in each architecture:
GPR register-
Stack Accumulator GPR load/store
memory
architecture architecture architecture
architecture
Main Main Main Main
Memory Memory Memory Memory

Stack
reg reg
AC
reg reg
reg reg

ALU ALU
ALU ALU

Source operand(s): Source operand(s): Source operand(s): Source operand(s):

top of stack; AC and memory; registers and memory; registers;
Destination operand: Destination operand: Destination operand: Destination operand:
top of stack; AC; registers; registers;
Memory not used Memory not used
except when load/store except when load/store
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 Instruction Formats
Q: Show how the statement C = A + B may be implemented in each of
these architectures.

GPR reg- Main GPR

Stack Main Accu. Main Main
mem load/store
arch. Memory Arch. Memory Memory Memory
arch arch.

Stack
reg reg
AC
reg reg
reg reg

ALU ALU
ALU ALU

Source operand(s): Source operand(s): Source operand(s): Source operand(s):

top of stack; AC and memory; registers and memory; registers;
Destination operand: Destination operand: Destination operand: Destination operand:
top of stack; AC; registers; registers;
Memory not used Memory not used
except when load/store except when load/store

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 Instruction Formats
Q: Show how the statement C = A + B may be implemented in each of
these architectures.

GPR reg- Main GPR

Stack Main Accu. Main Main
mem load/store
arch. Memory Arch. Memory Memory Memory
arch arch.

Stack
reg reg
AC
reg reg
reg reg

ALU ALU
ALU ALU
Answers:

Push A Load A Load R1 A Load R1 A

Push B Add B Add R2 R1 B Load R2 B
Add Store C Store R2 C Add R3 R1 R2
Pop C Store R3 C

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 X = (A + B) x(C +D): Three-Address
Instructions
Memory-to-Memory Architecture
•ADD T1, A, B M[T1] ← M[A] +M[B]
•ADD T2, C, D M[T2] ← M[C] + M[D]
•MUL X, T1, T2 M[X] ← M[T1] x M[T2]

Register-Memory Architecture
•ADD R1, A, B R1 ← M[A] +M[B]
•ADD R2, C, D R2←M[C] + M[D]
•MUL X, R1, R2 M[X]←R1 x R2

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X = (A + B) x(C + D): Two-Address
Instructions
Memory-to-Memory Architecture

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X = (A + B) x(C + D): One-Address
Instructions
Accumulator Architecture

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X = (A +B) x(C +D): Zero-Address
Instructions
Stack Architecture

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 Addressing Modes
• Implied Mode
– needs no address field at all
– operand is specified implicitly in the definition of the
opcode
• Examples
– instruction that uses an accumulator without a second
operand is an implied-mode instruction
• Complement accumulator
– data-manipulation instructions in a stack computer
• ADD (the operands are implied to be on top of stack)

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 Addressing Modes
Immediate Mode:
opcode R1 R2 600

Direct Mode:
opcode R1 R2 600 Memory

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Indirect Mode:

opcode R1 R2 600 Memory

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Register Direct Mode:

opcode R1 R2 600

Processor Registers

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Register Indirect Mode:

opcode R1 R2 600

Processor Registers Memory

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Relative Addressing Mode:

opcode R1 R2 600

Memory

PC

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Indexed Addressing Mode:

opcode R1 R2 600

Memory

IR

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 Addressing Modes (Summary)
Direct, ACC <- 800
Immediate, ACC <- 500
Indirect, ACC <- 300
Relative, ACC <- 600
Index, ACC <- 200
assuming R1 as an index register

Register, ACC <- 400

assuming R1 register holds operand

Register Indirect, ACC <- 700

assuming R1 register holds the effective address

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 Class Task

Memory IR: 200 Mode Value loaded

800 50 in ACC
900 1000 Immediate 900
1000 1400 Direct 1000
1100 120 Indexed 120
1200 570 Addressing

1300 30 Indirect 1400

1400 60

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 MIPS Architecture
• MIPS stands for microcomputer without interlocked pipeline
stages
• All MIPS arithmetic instructions have 3 explicit operands.
(Design Principle 1: Simplicity favors regularity)
• MIPS is a load/store architecture.
• Operands must be in registers – only 32 registers provided.
(Design Principle 2: Smaller is faster)
• For MIPS, a word is 32 bits or 4 bytes.
– loading words but addressing bytes
0 32 bits of data
4 32 bits of data
Registers correspondingly hold 32 bits of data
8 32 bits of data
12 32 bits of data
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 Alignment Restrictions
• Bytes in a word can be numbered in two ways:
– byte 0 at the leftmost (most significant) to byte 3 at the rightmost
(least significant), called big-endian
– byte 3 at the leftmost (most significant) to byte 0 at the rightmost
(least significant), called little-endian

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 Operations of the computer
Hardware
• Operand order is fixed (e.g., destination first)
• Example:

C code: A = B + C

MIPS code: add $s0, $s1, $s2

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 Operands of the Computer
Hardware
• Arithmetic instructions operands must be in registers
– MIPS has 32 registers
• Compiler associates variables with registers (e.g. $)
• What about programs with lots of variables (arrays, etc.)?
– Use memory,
• Remember MIPS arithmetic operands are registers, not
memory locations therefore, words must first be moved from
memory to registers using loads before they can be operated
on; then result can be stored back to memory

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 Load Instruction
“Used to load a word from memory”
•lw $rt, offset($rs)
•The address is computed by adding the contents of
register $rs to the sign-extended offset (which is an
immediate value).
•Value from address computed above is then loaded
into register $rt
•Example:
• lw $t0, 20($s0) # $t0 = Memory[$s0 + 20]

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 STORE Instruction
“Used to store a word to memory”
•sw $rt, offset($rs)
•The address is computed by adding the contents of
register $rs to the sign-extended offset (which is an
immediate value).
•Value from register $rt is then copied to the memory
address computed.
•Example:
• sw $t0, 20($s0) # Memory[$s0 + 20] = $t0
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 Immediate Operands
• An instruction may require a constant as input. An
immediate instruction uses a constant number as one of
the inputs (instead of a register operand)
• Design Principle # 3:
• “Make the common case fast”
• Example:
• addi $s2, $s0, 4
• There is no “subtract immediate” instruction ! Subtract is
“add a negative”
• addi $s2, $s0, -4

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 Constant 0
• MIPS register 0 ($zero) is the constant 0 !
• Cannot be overwritten !
• Useful for common operations ! e.g.,
• move between registers
• add $t2, $s1, $zero

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 Compiling C code into MIPS
assembly
• f=(g+h)-(i+j);
• g=h+A[8];
• A[12]=h+A[8];

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 Instruction Formats
• Instructions are represented as 32-bit numbers (one
word), broken into 6 fields. Two types of instruction
formats:

• R-format
• I-format

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 R-format

Instruction fields !
• op: operation code (opcode) !
• rs: first source register number !
• rt: second source register number !
• rd: destination register number !
• shamt: shift amount (00000 for now) !
• funct: function code (extends opcode)

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 I-format

• Immediate arithmetic and load/store

instructions
• rt: destination or source register number !
• Address: offset added to base address in rs !
• Design Principle 4:
“Good design demands good compromises.”
• Different formats complicate decoding
• Keep formats as similar as possible
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 Logical Operations

Operation C++ MIPS

instructions
Shift left logical << sll
Shift right logical >> srl
Bit-by bit AND & and, andi
Bit-by-bit OR | or, ori
Bit-by-bit NOT ~ nor
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 Instructions for making decisions

• Branch to a labeled instruction if a condition is true

otherwise, continue sequentially
• beq rs, rt, L1
– if (rs == rt) branch to instruction labeled L1;
• bne rs, rt, L1
– if (rs != rt) branch to instruction labeled L1;
• j L1
– unconditional jump to instruction labeled L1

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 Instructions for making decisions
• Branch instructions specify
• Opcode, two registers, target address

• PC-relative addressing
• Target address = PC + offset × 4 (PC already
incremented by 4 by this time)

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 CONTD….
• Jump (j and jal) targets could be anywhere in text
segment.

• Direct jump addressing !

• Target address = PC31…28 : (address × 4)

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 CONTD…
• EXAMPLE
• C code:
if (i==j) bne $s3, $s4, Else
f = g+h; add $s0, $s1, $s2
else j Exit
f = g-h; Else: sub $s0,$s1,$s2
Exit:

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 CONTD…
EXAMPLE
C code: Loop: sll $t1, $s3, 2
while(save[i]==k) add $t1, $t1, $s6
i += 1; lw $t0, 0($t1)
bne $t0, $s5, Exit
addi $s3, $s3, 1
j Loop
Exit:

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 CONTD…
• Set result to 1 if a condition is true
– Otherwise, set to 0
• slt rd, rs, rt
– if (rs < rt) rd = 1; else rd = 0;
• slti rt, rs, constant
– if (rs < constant) rt = 1; else rt = 0;
• Use in combination with beq, bne
slt $t0, $s1, $s2 # if ($s1 < $s2)
bne $t0, $zero, L # branch to L

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 Procedure calling
Steps required
1. Place parameters in registers
2. Transfer control to procedure
3. Acquire storage for procedure
4. Perform procedure’s operations
5. Place result in register for caller
6. Return to place of call

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 Register usage
• $a0 – $a3: arguments (reg’s 4 – 7)
• $v0, $v1: result values (reg’s 2 and 3)
• $t0 – $t9: temporaries
– Can be overwritten by callee
• $s0 – $s7: saved
– Must be saved/restored by callee
• $gp: global pointer for static data (reg 28)
• $sp: stack pointer (reg 29)
• $fp: frame pointer (reg 30)
• $ra: return address (reg 31)

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 Procedure call instructions
• Procedure call: jump and link
• jal ProcedureLabel
– Address of following instruction put in $ra
– Jumps to target address
• Procedure return: jump register
• jr $ra
– Copies $ra to program counter
– Can also be used for computed jumps
• e.g., for case/switch statements

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 Example
• procedure adds 10 to input parameter
int main()
{ int i, j;
i = 5;
j = add10(i);
i = j;
}
int add10(int i)
{ return (i + 10);}

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 Contd…
• main:
addi $s0, $0, 5
add $a0, $s0, $0
jal add10
add $s1, $v0, $0
add $s0, $s1, $0
• add10:

addi $sp, $sp, -4

sw $s0, 0($sp)
addi $s0, $a0, 10
add $v0, $s0, $0
lw $s0, 0($sp)
addi $sp, $sp, 4
jr $ra
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 CLASS TASK
C code:
•
• int leaf_example (int g, h, i, j)
{
• int f;
f = (g+h)–(i+j);
return f;
}

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 CONTD…
• add $t0, $a0, $a1
add $t1, $a2, $a3
sub $s0, $t0, $t1
•
addi $sp, $sp, -12
sw $t1,8($sp)
• sw $t0,4($sp)
• sw $s0,0($sp)
add $v0, $s0, $zero
•
lw $s0, 0($sp)
• lw $t0, 4($sp)
• lw $t1, 8($sp)
addi $sp, $sp, 12
•
jr $ra

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