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Tag 22 bit 2 bit
Set Associative Cache
• In order to provide some degree of • We can expand this to:
variability in placement, we need – 4-way set associative
more than a direct-mapped cache – 8-way set associative
– A 2-way set associative cache – 16-way set associative, etc
provides 2 refill lines for each line
number
• As the number increases,
• Instead of n refill lines, there are now
the hit rate improves, but
n / 2 sets, each set storing 2 refill lines the expense also increases
– We can think of this as having 2 and the hit time gets worse
direct-mapped caches of half the size
• Because there are ½ as many refill • Eventually we reach an n-
lines, the line number has 1 fewer bits way cache, which is a fully
and the tag number has 1 more associative cache
Address 1010 is
page 101, item 0
Here, we have 13 bits for our addresses even though main memory is only 4K = 212
The Full
Paging
Process
We want to avoid memory accesses
(we prefer cache accesses) – but if
every memory access now requires
first accessing the page table, which
is in memory, it slows down our
computer
Two on-chip caches: one for data, one for instructions with part of each cache
Reserved for a TLB
One off-chip cache to back-up both on-chip caches
Main memory, backed up by virtual memory