System Timing Diagrams

T-State:
• One clock period is referred to as a T-State

CPU Bus Cycle:

• A bus cycle consists of 4 T-States

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System Bus Timing

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3
4
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 Memory Read Timing Diagrams
• If data are read from the memory of the microprocessor:
– outputs the memory address on the address bus
– issues a read memory signal (RD)
– and accepts the data via the data bus
– IO/M = 1 & RD=0

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 Memory Write Timing Diagrams
• If data are written to memory the processor:
– outputs the memory address on the address bus
– outputs the data to be written on the data bus
– issues a write (WR) to memory
– IO/M = 1 and WR=0

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 Setup & Hold Time

• Setup time –The time before the rising edge of the

clock, while the data must be valid and constant
• Hold time –The time after the rising edge of the clock
during which the data must remain valid and constant

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 Basic Configuration
• 1.Minimum Mode
• 2.Maximum Mode

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Minimum Mode

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 1.Minimum Mode
During T 1 :
The address is placed on the Address/Data bus.
Control signals M/IO, ALE and DT/R specify memory or I/O, latch the address onto the address bus
and set the direction of data transfer on data bus.

During T 2 :
8086 issues the RD or WR signal, DEN, for a write or read the data .
• DEN enables the memory or I/O device to receive the data for writes and the 8086 to
receive the data for reads.

During T 3 :
This cycle is provided to allow memory to access data.
READY is sampled at the end of T2 .
• If low, T3 becomes a wait state.
• Otherwise, the data bus is sampled at the end of T3 .

During T 4 :
All bus signals are deactivated, in preparation for next bus cycle.
Data is sampled for reads, writes occur for writes.

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Memory READ in Minimum Mode

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 Memory Read
• The read cycle begins in T1 with the assertion of the address latch enable
(ALE) signal and also M/IO* signal.
• During the negative going edge of this signal, the valid address is latched on
the local bus.
• The BHE* and A0 signals address low, high or both bytes.
• From T1 to T4, the M/IO* signal indicates a memory or I/O operation.
• At T2 the address is removed from the local bus and is sent to the output.
• The bus is then tristated. The read (RD*) control signal is also activated in T2.
• The read (RD) signal causes the addressed device to enable its data bus
drivers. After RD* goes low, the valid data is available on the data bus.
• The addressed device will drive the READY line high, when the processor
returns the read signal to high level, the addressed device will again tristate
its bus drivers.

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Memory WRITE in Minimum Mode

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Maximum Mode

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2.Maximum Mode

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2.Maximum Mode

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 Memory Write
• A write cycle also begins with the assertion of ALE and
the emission of the address.
• The M/IO* signal is again asserted to indicate a
memory or I/O operation.
• In T2 after sending the address in T1 the processor
sends the data to be written to the addressed location.
• The data remains on the bus until middle of T4 state.
The WR* becomes active at the beginning of T2.
• The BHE* and A0 signals are used to select the proper
byte or bytes of memory or I/O word to be read or
written.

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