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Logic Design
Medium Scale Integration and
Programmable Logic Devices
Part I
Review
• We have studied and developed several techniques for simplifying
Boolean expressions.
• These are based on the axioms, definitions and theorems of the
Boolean Algebra, applied through the Boolean Calculus.
• Powerful tabular techniques have been developed for rapid
reduction to some minimal cost forms (ie. Karnaugh maps)
• Assume that A and B each represent a single data bit, with possible
numeric values 0 and 1.
Circuit # 1 : Half-Adder
• We begin by designing a circuit that will perform numeric (integer)
addition of two input values.
• Assume that A and B each represent a single data bit, with possible
numeric values 0 and 1.
• Assume that A and B each represent a single data bit, with possible
numeric values 0 and 1.
• Assume that A and B each represent a single data bit, with possible
numeric values 0 and 1.
• Assume that A and B each represent a single data bit, with possible
numeric values 0 and 1.
A B S C
0 0 0 0 0 + 0 = 0 (no carry)
Circuit # 1 : Half-Adder
• We begin the design by constructing a 2-input/2-output truth table
A B S C
0 0 0 0
0 1 1 0 0 + 1 = 1 (no carry)
Circuit # 1 : Half-Adder
• We begin the design by constructing a 2-input/2-output truth table
A B S C
0 0 0 0
0 1 1 0
1 0 1 0 1 + 0 = 1 (no carry)
Circuit # 1 : Half-Adder
• We begin the design by constructing a 2-input/2-output truth table
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1 1 + 1 = 0 (with a carry = 1)
Circuit # 1 : Half-Adder
• We begin the design by constructing a 2-input/2-output truth table
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
S = A’B + AB’
Circuit # 1 : Half-Adder
• We begin the design by constructing a 2-input/2-output truth table
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
C = AB
Circuit # 1 : Half-Adder
• We begin the design by constructing a 2-input/2-output truth table
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
C = AB
A HA
S
C
Circuit # 1 : Half-Adder
• Using the S and C circuit expressions for the Half-Adder circuit:
S = A’B + AB’ = A r B A
S
HA
B
C = AB
C
A HA A HA
S S
B B
C C
Circuit # 2 : Full-Adder
Circuit # 2 : Full-Adder
• The problem is to design a circuit, called a Full-Adder, that is able
to model the addition operation, assuming:
• Assume that A, B and Cin each represent a single data bit, with
possible numeric values 0 and 1. The input Cin corresponds to a
carry bit generated from prior bit additions.
Circuit # 2 : Full-Adder
• The problem is to design a circuit, called a Full-Adder, that is able
to model the addition operation, assuming:
• Assume that A, B and Cin each represent a single data bit, with
possible numeric values 0 and 1. The input Cin corresponds to a
carry bit generated from prior bit additions.
Cin A B S Cout
Circuit # 2 : Full-Adder
• We begin the design by constructing a 3-input/2-output truth table:
Cin A B S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
Circuit # 2 : Full-Adder
• We begin the design by constructing a 3-input/2-output truth table:
Cin A B S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Circuit # 2 : Full-Adder
• We begin the design by constructing a 3-input/2-output truth table:
Cin A B S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Cin A B S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Cin A B S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0 Cin
0 1 1 0 1 S
A FA
1 0 0 1 0 Cin
1 0 1 0 1 B
1 1 0 0 1
1 1 1 1 1
= AB + CinB + CinA
Circuit # 2 : Full-Adder
• The representation of the Full-Adder circuit using gate logics is:
Cin
S
A FA
Cout
B
Circuit # 2 : Full-Adder
• The representation of the Full-Adder circuit using gate logics is:
FA
Cin Cin
S
A FA A S
Cout B
B
Cout
Circuit # 2 : Full-Adder
• Adapting the notation to a general set of input and output bits:
FA
CK CK
SK SK
AK FA AK
CK+1 BK
BK
CK+1
Circuit # 3 : Multi-bit Adder
Circuit # 3 : Multi-bit Adder
• We may now use the previous results to construct a circuit to
perform addition of two multi-bit inputs, A and B.
Circuit # 3 : Multi-bit Adder
• We may now use the previous results to construct a circuit to
perform addition of two multi-bit inputs, A and B.
Cout C3 C2 C1
A3 A2 A1 A0
+ B3 B2 B1 B0
S3 S2 S1 S0
Circuit # 3 : Multi-bit Adder
• We may now use the previous results to construct a circuit to
perform addition of two multi-bit inputs, A and B.
Cout C3 C2 C1
A3 A2 A1 A0
+ B3 B2 B1 B0
S3 S2 S1 S0
Cout C3 C2 C1
A3 A2 A1 A0
+ B3 B2 B1 B0
S3 S2 S1 S0
Cout C3 C2 C1
A3 A2 A1 A0 A
HA S
+ B3 B2 B1 B0 B
S3 S2 S1 S0 C
There is no
initial Carry bit.
– Outputs: S = { S3, S2, S1, S0 } and Cout.
Circuit # 3 : Multi-bit Adder
• We may now use the previous results to construct a circuit to
perform addition of two multi-bit inputs, A and B.
Cout C3 C2 C1
A3 A2 A1 A0
+ B3 B2 B1 B0
S3 S2 S1 S0
Cout C3 C2 C1
CK
SK A3 A2 A1 A0
AK FA
CK+1 + B3 B2 B1 B0
BK
S3 S2 S1 S0
Cout C3 C2 C1
CK
SK A3 A2 A1 A0 A
AK HA S
FA
CK+1 + B3 B2 B1 B0 B
BK
S3 S2 S1 S0 C
CK Cout C3 C2 C1 A
S
SK HA
AK FA A3 A2 A1 A0 B
CK+1
BK + B3 B2 B1 B0 C
S3 S2 S1 S0
B3 B2 B1 B0
A3 A2 A1 A0
Cout
S3 S2 S1 S0
Circuit # 3 : Multi-bit Adder
• Applying our previously determined HA and FA circuits:
CK Cout C3 C2 C1 A
S
SK HA
AK FA A3 A2 A1 A0 B
CK+1
BK + B3 B2 B1 B0 C
S3 S2 S1 S0
B3 B2 B1 B0 B3 B2 B1 B0 A3 A2 A1 A0
A3 A2 A1 A0
Cout Cout
S3 S2 S1 S0 S3 S2 S1 S0
Summary - Part I
• We have begun to study logic design in the contexts of Medium
Scale Integration (MSI) of gate devices and programmable logic
devices (PLD).
– 1-bit Half-Adder
– 1-bit Full-Adder
– Multi-bit Ripple Adder